package core:rexcode/isa/x86

Source

Addr_Size :: enum u8 {
	DEFAULT, // whatever the mode/prefix selects; the form does not care
	A16,     // 16-bit addressing (CX)
	A32,     // 32-bit addressing (ECX)
	A64,     // 64-bit addressing (RCX); long mode only
}

BND :: enum u8 {
	BND0, 
	BND1, 
	BND2, 
	BND3, 
}

Broadcast :: enum u8 {
	NONE   = 0, // No broadcast (full vector load)
	B1TO2  = 1, // Broadcast 1 element to 2 (64-bit element to 128-bit vector)
	B1TO4  = 2, // Broadcast 1 element to 4 (32-bit to 128-bit, or 64-bit to 256-bit)
	B1TO8  = 3, // Broadcast 1 element to 8 (32-bit to 256-bit, or 64-bit to 512-bit)
	B1TO16 = 4, // Broadcast 1 element to 16 (32-bit to 512-bit)
}

CREG :: enum u8 {
	CR0 = 0, 
	CR2 = 2, 
	CR3 = 3, 
	CR4 = 4, 
	CR8 = 8, 
}

Clobber :: struct {
	written:      Operand_Set,
	read:         Operand_Set,
	implicit_wr:  Clobber_Regs,
	implicit_rd:  Clobber_Regs,
	flags_wr:     Clobber_Flags,
	flags_undef:  Clobber_Flags,
	flags_rd:     Clobber_Flags,
	writes_mem:   bool,
	reads_mem:    bool,
	side_effects: Side_Effects,
}

Clobber_Flag :: enum u8 {
	CF, 
	PF, 
	AF, 
	ZF, 
	SF, 
	OF, 
	DF, 
	IF, 
	TF, 
}

Clobber_Flags :: distinct bit_set[Clobber_Flag; u16]

Clobber_Reg :: enum u8 {
	RAX, 
	RBX, 
	RCX, 
	RDX, 
	RSI, 
	RDI, 
	RSP, 
	RBP, 
	R11, 
	XMM0, 
	VECTOR, 
	MXCSR, 
	FPU_ST, 
	FPU_SW, 
}

Clobber_Regs :: distinct bit_set[Clobber_Reg; u16]

DREG :: enum u8 {
	DR0, 
	DR1, 
	DR2, 
	DR3, 
	DR6, 
	DR7, 
}

Decode_Entry :: struct {
	esc:      Escape,
	prefix:   u8,
	opcode:   u8,
	ext:      u8,
	mnemonic: Mnemonic,
	ops:      [4]Operand_Type,
	enc:      [4]Operand_Encoding,
	flags:    Encoding_Flags,
}

Decode_Index :: struct {
	start: u16,
	count: u8,
}

Decoder_State :: struct {
	data:       []u8,
	// Input bytes
	position:   int,
	// Current position
	mode:       Mode,
	// Decoded prefix state
	rex:        u8,
	prefix_66:  bool,
	prefix_f2:  bool,
	prefix_f3:  bool,
	prefix_67:  bool,
	// Address size override
	segment:    Register,
	has_lock:   bool,
	opcode_reg: u8,
	// VEX/EVEX state
	vex_type:   VEX_Type,
	vex_r:      bool,
	// VEX.R (inverted)
	vex_x:      bool,
	// VEX.X (inverted)
	vex_b:      bool,
	// VEX.B (inverted)
	vex_w:      bool,
	// VEX.W
	vex_l:      u8,
	// VEX.L (0, 1, or 2 for EVEX)
	vex_vvvv:   u8,
	// VEX.vvvv register
	vex_pp:     u8,
	// VEX.pp (implied prefix)
	vex_mmmmm:  u8,
	// EVEX specific
	evex_r2:    bool,
	// EVEX.R'
	evex_v2:    bool,
	// EVEX.V'
	evex_z:     bool,
	// EVEX.z (zeroing)
	evex_b:     bool,
	// EVEX.b (broadcast/rc/sae)
	evex_aaa:   u8,
}

Encode_Run :: struct {
	start: u32,
	count: u32,
}

Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2 bytes
	ops:      [4]Operand_Type,
	// 4 bytes - operand types
	enc:      [4]Operand_Encoding,
	// 4 bytes - operand encodings
	opcode:   u8,
	// 1 byte - primary opcode byte
	ext:      u8,
	// 1 byte - ModR/M reg extension (/0-/7) or secondary opcode
	flags:    Encoding_Flags,
}

Encoding_Flags :: distinct bit_field u32 {
	esc:            Escape | 2,
	prefix:         u8 | 2,
	vex_type:       VEX_Type | 2,
	vex_w:          VEX_W | 2,
	vex_l:          VEX_L | 2,
	default_64:     bool | 1,
	force_rex_w:    bool | 1,
	opsize_16:      bool | 1,
	no_rex:         bool | 1,
	lock_ok:        bool | 1,
	rep_ok:         bool | 1,
	modrm_reg_ext:  bool | 1,
	mode_32_only:   bool | 1,
	addr_size:      Addr_Size | 2,
	explicit_count: u8 | 3,
	has_implicit:   bool | 1,
	op_count:       u8 | 3,
	needs_modrm:    bool | 1,
}

Error :: rexcode_isa.Error

Error_Code :: rexcode_isa.Error_Code

Escape :: enum u8 {
	NONE,  // single-byte opcode
	_0F,   // 0F xx
	_0F38, // 0F 38 xx
	_0F3A, // 0F 3A xx
}

Form_Recipe :: struct {
	prefix:     u8,
	// mandatory legacy prefix emitted before REX (0 = none)
	opcode:     [3]u8,
	// escape + opcode: [op] / [0F,op] / [0F,38,op] / [0F,3A,op]
	opcode_len: u8,
	// 1..3
	ext:        u8,
	// ModR/M reg ext digit (when reg_from_ext) or /digit source
	rm_op:      i8,
	// user operand index -> ModR/M r/m field   (-1 = none)
	reg_op:     i8,
	// user operand index -> ModR/M reg field   (-1 = none)
	opr_op:     i8,
	// user operand index -> +rb opcode register (-1 = none)
	imm_op:     i8,
	// user operand index -> immediate          (-1 = none)
	imm_size:   u8,
	// 1/2/4/8 when imm_op >= 0
	flags:      Recipe_Flags,
}

GPR16 :: enum u8 {
	AX, 
	CX, 
	DX, 
	BX, 
	SP, 
	BP, 
	SI, 
	DI, 
	R8W, 
	R9W, 
	R10W, 
	R11W, 
	R12W, 
	R13W, 
	R14W, 
	R15W, 
}

GPR32 :: enum u8 {
	EAX, 
	ECX, 
	EDX, 
	EBX, 
	ESP, 
	EBP, 
	ESI, 
	EDI, 
	R8D, 
	R9D, 
	R10D, 
	R11D, 
	R12D, 
	R13D, 
	R14D, 
	R15D, 
}

GPR64 :: enum u8 {
	RAX, 
	RCX, 
	RDX, 
	RBX, 
	RSP, 
	RBP, 
	RSI, 
	RDI, 
	R8, 
	R9, 
	R10, 
	R11, 
	R12, 
	R13, 
	R14, 
	R15, 
}

GPR8 :: enum u8 {
	AL, 
	CL, 
	DL, 
	BL, 
	SPL, 
	BPL, 
	SIL, 
	DIL, 
	R8B, 
	R9B, 
	R10B, 
	R11B, 
	R12B, 
	R13B, 
	R14B, 
	R15B, 
}

GPR8H :: enum u8 {
	AH = 4, 
	CH = 5, 
	DH = 6, 
	BH = 7, 
}

Instruction :: struct #packed {
	ops:           [4]Operand `fmt:"v,operand_count`,
	// 48 bytes
	mnemonic:      Mnemonic,
	//  2 bytes
	operand_count: u8,
	//  1 byte
	flags:         Instruction_Flags,
	//  1 byte
	length:        u8,
	//  1 byte (filled by decoder, used for iteration)
	enc_hint:      u16,
	//  2 bytes (pre-matched form, +1 biased; 0 = none)
	_:             [9]u8,
}

Instruction_Flags :: distinct bit_field u8 {
	lock:    bool | 1,
	rep:     Rep | 2,
	segment: u8 | 3,
	addr32:  bool | 1,
	data16:  bool | 1,
}

Instruction_Info :: struct {
	offset:   u32,
	// Prefix info
	rex:      u8,
	// REX byte (0 if none)
	has_lock: bool,
	rep:      Rep,
	// Rep prefix (uses same enum as Instruction_Flags)
	segment:  Register,
	// VEX/EVEX info
	vex_type: VEX_Type,
	vex_l:    VEX_L,
	vex_w:    VEX_W,
	evex_b:   bool,
	// EVEX broadcast
	evex_z:   bool,
	// EVEX zeroing
	opmask:   u8,
}

KREG :: enum u8 {
	K0, 
	K1, 
	K2, 
	K3, 
	K4, 
	K5, 
	K6, 
	K7, 
}

Label_Definition :: rexcode_isa.Label_Definition

Label_Map :: rexcode_isa.Label_Map

Label_Names :: map[rexcode_isa.Label_Offset]string

Label_Offset :: rexcode_isa.Label_Offset

MM :: enum u8 {
	MM0, 
	MM1, 
	MM2, 
	MM3, 
	MM4, 
	MM5, 
	MM6, 
	MM7, 
}

Mem128 :: struct {
	mem: Memory,
}

Mem16 :: struct {
	mem: Memory,
}

Mem256 :: struct {
	mem: Memory,
}

Mem32 :: struct {
	mem: Memory,
}

Mem512 :: struct {
	mem: Memory,
}

Mem64 :: struct {
	mem: Memory,
}

Mem8 :: struct {
	mem: Memory,
}

Mem80 :: struct {
	mem: Memory,
}

Memory :: distinct bit_field u64 {
	base_hw:            u8 | 5,
	base_ext:           bool | 1,
	index_hw:           u8 | 5,
	index_ext:          bool | 1,
	scale_enc:          u8 | 2,
	disp:               i32 | 32,
	segment:            u8 | 3,
	addr_size_override: bool | 1,
	base_class:         u8 | 5,
	index_class:        u8 | 5,
	disp_is_label:      bool | 1,
}

Mnemonic :: enum u16 {
	INVALID          = 0, 
	// -------------------------------------------------------------------------
	// SECTION: 4.1 Data Transfer Instructions
	// -------------------------------------------------------------------------
	MOV, 
	MOVABS, 
	MOVZX, 
	MOVSX, 
	MOVSXD, 
	XCHG, 
	PUSH, 
	POP, 
	LEA, 
	// -------------------------------------------------------------------------
	// SECTION: 4.2 Arithmetic Instructions
	// -------------------------------------------------------------------------
	ADD, 
	ADC, 
	SUB, 
	SBB, 
	MUL, 
	IMUL, 
	DIV, 
	IDIV, 
	INC, 
	DEC, 
	NEG, 
	CMP, 
	// -------------------------------------------------------------------------
	// SECTION: 4.3 Logical Instructions
	// -------------------------------------------------------------------------
	AND, 
	OR, 
	XOR, 
	NOT, 
	TEST, 
	// -------------------------------------------------------------------------
	// SECTION: 4.4 Shift and Rotate Instructions
	// -------------------------------------------------------------------------
	SHL, 
	SHR, 
	SAR, 
	SAL, 
	ROL, 
	ROR, 
	RCL, 
	RCR, 
	SHLD, 
	SHRD, 
	// -------------------------------------------------------------------------
	// SECTION: 4.5 Bit Operations
	// -------------------------------------------------------------------------
	BT, 
	BTS, 
	BTR, 
	BTC, 
	BSF, 
	BSR, 
	POPCNT, 
	LZCNT, 
	TZCNT, 
	// -------------------------------------------------------------------------
	// SECTION: 4.6 Control Flow Instructions
	// -------------------------------------------------------------------------
	JMP, 
	JA, 
	JAE, 
	JB, 
	JBE, 
	JC, 
	JE, 
	JZ, 
	JG, 
	JGE, 
	JL, 
	JLE, 
	JNA, 
	JNAE, 
	JNB, 
	JNBE, 
	JNC, 
	JNE, 
	JNZ, 
	JNG, 
	JNGE, 
	JNL, 
	JNLE, 
	JNO, 
	JNP, 
	JNS, 
	JO, 
	JP, 
	JPE, 
	JPO, 
	JS, 
	JCXZ, 
	JECXZ, 
	JRCXZ, 
	LOOP, 
	LOOPE, 
	LOOPNE, 
	CALL, 
	RET, 
	IRET, 
	IRETD, 
	IRETQ, 
	INT, 
	INT3, 
	INTO, 
	SYSCALL, 
	SYSRET, 
	SYSENTER, 
	SYSEXIT, 
	// -------------------------------------------------------------------------
	// SECTION: 4.7 Conditional Set Instructions (SETcc)
	// -------------------------------------------------------------------------
	SETA, 
	SETAE, 
	SETB, 
	SETBE, 
	SETC, 
	SETE, 
	SETG, 
	SETGE, 
	SETL, 
	SETLE, 
	SETNA, 
	SETNAE, 
	SETNB, 
	SETNBE, 
	SETNC, 
	SETNE, 
	SETNG, 
	SETNGE, 
	SETNL, 
	SETNLE, 
	SETNO, 
	SETNP, 
	SETNS, 
	SETNZ, 
	SETO, 
	SETP, 
	SETPE, 
	SETPO, 
	SETS, 
	SETZ, 
	// -------------------------------------------------------------------------
	// SECTION: 4.8 Conditional Move Instructions (CMOVcc)
	// -------------------------------------------------------------------------
	CMOVA, 
	CMOVAE, 
	CMOVB, 
	CMOVBE, 
	CMOVC, 
	CMOVE, 
	CMOVG, 
	CMOVGE, 
	CMOVL, 
	CMOVLE, 
	CMOVNA, 
	CMOVNAE, 
	CMOVNB, 
	CMOVNBE, 
	CMOVNC, 
	CMOVNE, 
	CMOVNG, 
	CMOVNGE, 
	CMOVNL, 
	CMOVNLE, 
	CMOVNO, 
	CMOVNP, 
	CMOVNS, 
	CMOVNZ, 
	CMOVO, 
	CMOVP, 
	CMOVPE, 
	CMOVPO, 
	CMOVS, 
	CMOVZ, 
	// -------------------------------------------------------------------------
	// SECTION: 4.9 STring Operations
	// -------------------------------------------------------------------------
	MOVS, 
	MOVSB, 
	MOVSW, 
	MOVSD, 
	MOVSQ, 
	CMPS, 
	CMPSB, 
	CMPSW, 
	CMPSD, 
	CMPSQ, 
	SCAS, 
	SCASB, 
	SCASW, 
	SCASD, 
	SCASQ, 
	LODS, 
	LODSB, 
	LODSW, 
	LODSD, 
	LODSQ, 
	STOS, 
	STOSB, 
	STOSW, 
	STOSD, 
	STOSQ, 
	// -------------------------------------------------------------------------
	// SECTION: 4.10 Flag Operations
	// -------------------------------------------------------------------------
	CLC, 
	STC, 
	CMC, 
	CLD, 
	STD, 
	CLI, 
	STI, 
	LAHF, 
	SAHF, 
	PUSHF, 
	PUSHFD, 
	PUSHFQ, 
	POPF, 
	POPFD, 
	POPFQ, 
	// -------------------------------------------------------------------------
	// SECTION: 4.11 Miscellaneous Instructions
	// -------------------------------------------------------------------------
	NOP, 
	HLT, 
	WAIT, 
	LOCK, 
	UD0, 
	UD1, 
	UD2, 
	CPUID, 
	RDTSC, 
	RDTSCP, 
	RDPMC, 
	XGETBV, 
	XSETBV, 
	// -------------------------------------------------------------------------
	// SECTION: 4.12 Conversion Instructions
	// -------------------------------------------------------------------------
	CBW, 
	CWDE, 
	CDQE, 
	CWD, 
	CDQ, 
	CQO, 
	// -------------------------------------------------------------------------
	// SECTION: 4.13 BMI1/BMI2 Instructions
	// -------------------------------------------------------------------------
	ANDN, 
	BEXTR, 
	BLSI, 
	BLSMSK, 
	BLSR, 
	BZHI, 
	PDEP, 
	PEXT, 
	RORX, 
	SARX, 
	SHLX, 
	SHRX, 
	MULX, 
	// -------------------------------------------------------------------------
	// SECTION: 4.14 ADX Instructions
	// -------------------------------------------------------------------------
	ADCX, 
	ADOX, 
	// -------------------------------------------------------------------------
	// SECTION: 4.15 SSE Instructions
	// -------------------------------------------------------------------------
	MOVAPS, 
	MOVUPS, 
	MOVAPD, 
	MOVUPD, 
	MOVSS, 
	MOVDQA, 
	MOVDQU, 
	MOVQ, 
	MOVD, 
	MOVLPS, 
	MOVHPS, 
	MOVLPD, 
	MOVHPD, 
	MOVLHPS, 
	MOVHLPS, 
	MOVMSKPS, 
	MOVMSKPD, 
	MOVNTPS, 
	MOVNTPD, 
	MOVNTDQ, 
	MOVNTDQA, 
	ADDPS, 
	ADDPD, 
	ADDSS, 
	ADDSD, 
	SUBPS, 
	SUBPD, 
	SUBSS, 
	SUBSD, 
	MULPS, 
	MULPD, 
	MULSS, 
	MULSD, 
	DIVPS, 
	DIVPD, 
	DIVSS, 
	DIVSD, 
	SQRTPS, 
	SQRTPD, 
	SQRTSS, 
	SQRTSD, 
	RCPPS, 
	RCPSS, 
	RSQRTPS, 
	RSQRTSS, 
	MAXPS, 
	MAXPD, 
	MAXSS, 
	MAXSD, 
	MINPS, 
	MINPD, 
	MINSS, 
	MINSD, 
	ANDPS, 
	ANDPD, 
	ANDNPS, 
	ANDNPD, 
	ORPS, 
	ORPD, 
	XORPS, 
	XORPD, 
	CMPPS, 
	CMPPD, 
	CMPSS, 
	COMISS, 
	COMISD, 
	UCOMISS, 
	UCOMISD, 
	SHUFPS, 
	SHUFPD, 
	UNPCKLPS, 
	UNPCKHPS, 
	UNPCKLPD, 
	UNPCKHPD, 
	CVTPS2PD, 
	CVTPD2PS, 
	CVTSS2SD, 
	CVTSD2SS, 
	CVTPS2DQ, 
	CVTPD2DQ, 
	CVTDQ2PS, 
	CVTDQ2PD, 
	CVTSS2SI, 
	CVTSD2SI, 
	CVTSI2SS, 
	CVTSI2SD, 
	CVTTPS2DQ, 
	CVTTPD2DQ, 
	CVTTSS2SI, 
	CVTTSD2SI, 
	// -------------------------------------------------------------------------
	// SECTION: 4.16 SSE2 Integer Instructions
	// -------------------------------------------------------------------------
	PADDB, 
	PADDW, 
	PADDD, 
	PADDQ, 
	PSUBB, 
	PSUBW, 
	PSUBD, 
	PSUBQ, 
	PADDSB, 
	PADDSW, 
	PADDUSB, 
	PADDUSW, 
	PSUBSB, 
	PSUBSW, 
	PSUBUSB, 
	PSUBUSW, 
	PMULLW, 
	PMULHW, 
	PMULHUW, 
	PMULUDQ, 
	PMADDWD, 
	PAND, 
	PANDN, 
	POR, 
	PXOR, 
	PSLLW, 
	PSLLD, 
	PSLLQ, 
	PSRLW, 
	PSRLD, 
	PSRLQ, 
	PSRAW, 
	PSRAD, 
	PCMPEQB, 
	PCMPEQW, 
	PCMPEQD, 
	PCMPGTB, 
	PCMPGTW, 
	PCMPGTD, 
	PACKSSWB, 
	PACKSSDW, 
	PACKUSWB, 
	PUNPCKLBW, 
	PUNPCKLWD, 
	PUNPCKLDQ, 
	PUNPCKLQDQ, 
	PUNPCKHBW, 
	PUNPCKHWD, 
	PUNPCKHDQ, 
	PUNPCKHQDQ, 
	PSHUFD, 
	PSHUFHW, 
	PSHUFLW, 
	PSHUFW, 
	PEXTRW, 
	PINSRW, 
	PMOVMSKB, 
	PAVGB, 
	PAVGW, 
	PMAXUB, 
	PMAXSW, 
	PMINUB, 
	PMINSW, 
	PSADBW, 
	MASKMOVDQU, 
	LFENCE, 
	SFENCE, 
	MFENCE, 
	PAUSE, 
	CLFLUSH, 
	// -------------------------------------------------------------------------
	// SECTION: 4.17 SSE3/SSSE3 Instructions
	// -------------------------------------------------------------------------
	ADDSUBPS, 
	ADDSUBPD, 
	HADDPS, 
	HADDPD, 
	HSUBPS, 
	HSUBPD, 
	MOVDDUP, 
	MOVSLDUP, 
	MOVSHDUP, 
	LDDQU, 
	PSHUFB, 
	PHADDW, 
	PHADDD, 
	PHADDSW, 
	PHSUBW, 
	PHSUBD, 
	PHSUBSW, 
	PMADDUBSW, 
	PMULHRSW, 
	PSIGNB, 
	PSIGNW, 
	PSIGND, 
	PABSB, 
	PABSW, 
	PABSD, 
	PALIGNR, 
	// -------------------------------------------------------------------------
	// SECTION: 4.18 SSE4.1/SSE4.2 Instructions
	// -------------------------------------------------------------------------
	BLENDPS, 
	BLENDPD, 
	BLENDVPS, 
	BLENDVPD, 
	PBLENDW, 
	PBLENDVB, 
	DPPS, 
	DPPD, 
	EXTRACTPS, 
	INSERTPS, 
	MPSADBW, 
	PACKUSDW, 
	PEXTRB, 
	PEXTRD, 
	PEXTRQ, 
	PHMINPOSUW, 
	PINSRB, 
	PINSRD, 
	PINSRQ, 
	PMAXSB, 
	PMAXSD, 
	PMAXUW, 
	PMAXUD, 
	PMINSB, 
	PMINSD, 
	PMINUW, 
	PMINUD, 
	PMOVSXBW, 
	PMOVSXBD, 
	PMOVSXBQ, 
	PMOVSXWD, 
	PMOVSXWQ, 
	PMOVSXDQ, 
	PMOVZXBW, 
	PMOVZXBD, 
	PMOVZXBQ, 
	PMOVZXWD, 
	PMOVZXWQ, 
	PMOVZXDQ, 
	PMULDQ, 
	PMULLD, 
	PTEST, 
	ROUNDPS, 
	ROUNDPD, 
	ROUNDSS, 
	ROUNDSD, 
	PCMPEQQ, 
	CRC32, 
	PCMPESTRI, 
	PCMPESTRM, 
	PCMPISTRI, 
	PCMPISTRM, 
	PCMPGTQ, 
	// -------------------------------------------------------------------------
	// SECTION: 4.19 AES-NI and SHA Instructions
	// -------------------------------------------------------------------------
	PCLMULQDQ, 
	AESDEC, 
	AESDECLAST, 
	AESENC, 
	AESENCLAST, 
	AESIMC, 
	AESKEYGENASSIST, 
	SHA1MSG1, 
	SHA1MSG2, 
	SHA1NEXTE, 
	SHA1RNDS4, 
	SHA256MSG1, 
	SHA256MSG2, 
	SHA256RNDS2, 
	// -------------------------------------------------------------------------
	// SECTION: 4.20 AVX Instructions
	// -------------------------------------------------------------------------
	VADDPS, 
	VADDPD, 
	VADDSS, 
	VADDSD, 
	VSUBPS, 
	VSUBPD, 
	VSUBSS, 
	VSUBSD, 
	VMULPS, 
	VMULPD, 
	VMULSS, 
	VMULSD, 
	VDIVPS, 
	VDIVPD, 
	VDIVSS, 
	VDIVSD, 
	VSQRTPS, 
	VSQRTPD, 
	VSQRTSS, 
	VSQRTSD, 
	VRCPPS, 
	VRCPSS, 
	VRSQRTPS, 
	VRSQRTSS, 
	VMAXPS, 
	VMAXPD, 
	VMAXSS, 
	VMAXSD, 
	VMINPS, 
	VMINPD, 
	VMINSS, 
	VMINSD, 
	VANDPS, 
	VANDPD, 
	VANDNPS, 
	VANDNPD, 
	VORPS, 
	VORPD, 
	VXORPS, 
	VXORPD, 
	VCMPPS, 
	VCMPPD, 
	VCMPSS, 
	VCMPSD, 
	VCOMISS, 
	VCOMISD, 
	VUCOMISS, 
	VUCOMISD, 
	VSHUFPS, 
	VSHUFPD, 
	VUNPCKLPS, 
	VUNPCKHPS, 
	VUNPCKLPD, 
	VUNPCKHPD, 
	VBLENDPS, 
	VBLENDPD, 
	VBLENDVPS, 
	VBLENDVPD, 
	VDPPS, 
	VDPPD, 
	VROUNDPS, 
	VROUNDPD, 
	VROUNDSS, 
	VROUNDSD, 
	VEXTRACTPS, 
	VINSERTPS, 
	VMOVAPS, 
	VMOVUPS, 
	VMOVAPD, 
	VMOVUPD, 
	VMOVSS, 
	VMOVSD, 
	VMOVDQA, 
	VMOVDQU, 
	VMOVQ, 
	VMOVD, 
	VMOVLPS, 
	VMOVHPS, 
	VMOVLPD, 
	VMOVHPD, 
	VMOVLHPS, 
	VMOVHLPS, 
	VMOVMSKPS, 
	VMOVMSKPD, 
	VMOVNTPS, 
	VMOVNTPD, 
	VMOVNTDQ, 
	VMOVNTDQA, 
	VADDSUBPS, 
	VADDSUBPD, 
	VHADDPS, 
	VHADDPD, 
	VHSUBPS, 
	VHSUBPD, 
	VLDDQU, 
	VMOVDDUP, 
	VMOVSLDUP, 
	VMOVSHDUP, 
	VPCMPESTRI, 
	VPCMPESTRM, 
	VPCMPISTRI, 
	VPCMPISTRM, 
	VPBROADCASTB, 
	VPBROADCASTW, 
	VPBROADCASTD, 
	VPBROADCASTQ, 
	VCVTPS2PD, 
	VCVTPD2PS, 
	VCVTSS2SD, 
	VCVTSD2SS, 
	VCVTPS2DQ, 
	VCVTPD2DQ, 
	VCVTDQ2PS, 
	VCVTDQ2PD, 
	VCVTSS2SI, 
	VCVTSD2SI, 
	VCVTSI2SS, 
	VCVTSI2SD, 
	VCVTTPS2DQ, 
	VCVTTPD2DQ, 
	VCVTTSS2SI, 
	VCVTTSD2SI, 
	VPADDB, 
	VPADDW, 
	VPADDD, 
	VPADDQ, 
	VPSUBB, 
	VPSUBW, 
	VPSUBD, 
	VPSUBQ, 
	VPMULLW, 
	VPMULHW, 
	VPMULHUW, 
	VPMULUDQ, 
	VPMADDWD, 
	VPAND, 
	VPANDN, 
	VPOR, 
	VPXOR, 
	VPSLLW, 
	VPSLLD, 
	VPSLLQ, 
	VPSRLW, 
	VPSRLD, 
	VPSRLQ, 
	VPSRAW, 
	VPSRAD, 
	VPCMPEQB, 
	VPCMPEQW, 
	VPCMPEQD, 
	VPCMPEQQ, 
	VPCMPGTB, 
	VPCMPGTW, 
	VPCMPGTD, 
	VPCMPGTQ, 
	VPACKSSWB, 
	VPACKSSDW, 
	VPACKUSWB, 
	VPACKUSDW, 
	VPUNPCKLBW, 
	VPUNPCKLWD, 
	VPUNPCKLDQ, 
	VPUNPCKLQDQ, 
	VPUNPCKHBW, 
	VPUNPCKHWD, 
	VPUNPCKHDQ, 
	VPUNPCKHQDQ, 
	VPSHUFD, 
	VPSHUFHW, 
	VPSHUFLW, 
	VPEXTRB, 
	VPEXTRW, 
	VPEXTRD, 
	VPEXTRQ, 
	VPINSRB, 
	VPINSRW, 
	VPINSRD, 
	VPINSRQ, 
	VPMOVMSKB, 
	VPTEST, 
	VPSHUFB, 
	VPHADDW, 
	VPHADDD, 
	VPHADDSW, 
	VPHSUBW, 
	VPHSUBD, 
	VPHSUBSW, 
	VPMADDUBSW, 
	VPMULHRSW, 
	VPSIGNB, 
	VPSIGNW, 
	VPSIGND, 
	VPABSB, 
	VPABSW, 
	VPABSD, 
	VPALIGNR, 
	VPBLENDW, 
	VPBLENDVB, 
	VMPSADBW, 
	VPHMINPOSUW, 
	VPMAXSB, 
	VPMAXSD, 
	VPMAXUW, 
	VPMAXUD, 
	VPMINSB, 
	VPMINSD, 
	VPMINUW, 
	VPMINUD, 
	VPMOVSXBW, 
	VPMOVSXBD, 
	VPMOVSXBQ, 
	VPMOVSXWD, 
	VPMOVSXWQ, 
	VPMOVSXDQ, 
	VPMOVZXBW, 
	VPMOVZXBD, 
	VPMOVZXBQ, 
	VPMOVZXWD, 
	VPMOVZXWQ, 
	VPMOVZXDQ, 
	VPMULDQ, 
	VPMULLD, 
	VMASKMOVDQU, 
	VPCLMULQDQ, 
	VAESDEC, 
	VAESDECLAST, 
	VAESENC, 
	VAESENCLAST, 
	VAESIMC, 
	VAESKEYGENASSIST, 
	VBROADCASTSS, 
	VBROADCASTSD, 
	VBROADCASTF128, 
	VEXTRACTF128, 
	VINSERTF128, 
	VPERM2F128, 
	VMASKMOVPS, 
	VMASKMOVPD, 
	VTESTPS, 
	VTESTPD, 
	VZEROALL, 
	VZEROUPPER, 
	// -------------------------------------------------------------------------
	// SECTION: 4.21 AVX2 Instructions
	// -------------------------------------------------------------------------
	VBROADCASTI128, 
	VEXTRACTI128, 
	VINSERTI128, 
	VPERM2I128, 
	VPERMD, 
	VPERMPS, 
	VPERMQ, 
	VPERMPD, 
	VPBLENDD, 
	VPSLLVD, 
	VPSLLVQ, 
	VPSRLVD, 
	VPSRLVQ, 
	VPSRAVD, 
	VPMASKMOVD, 
	VPMASKMOVQ, 
	VGATHERDPS, 
	VGATHERDPD, 
	VGATHERQPS, 
	VGATHERQPD, 
	VPGATHERDD, 
	VPGATHERDQ, 
	VPGATHERQD, 
	VPGATHERQQ, 
	// -------------------------------------------------------------------------
	// SECTION: 4.22 FMA Instructions
	// -------------------------------------------------------------------------
	VFMADD132PS, 
	VFMADD213PS, 
	VFMADD231PS, 
	VFMADD132PD, 
	VFMADD213PD, 
	VFMADD231PD, 
	VFMADD132SS, 
	VFMADD213SS, 
	VFMADD231SS, 
	VFMADD132SD, 
	VFMADD213SD, 
	VFMADD231SD, 
	VFMSUB132PS, 
	VFMSUB213PS, 
	VFMSUB231PS, 
	VFMSUB132PD, 
	VFMSUB213PD, 
	VFMSUB231PD, 
	VFMSUB132SS, 
	VFMSUB213SS, 
	VFMSUB231SS, 
	VFMSUB132SD, 
	VFMSUB213SD, 
	VFMSUB231SD, 
	VFNMADD132PS, 
	VFNMADD213PS, 
	VFNMADD231PS, 
	VFNMADD132PD, 
	VFNMADD213PD, 
	VFNMADD231PD, 
	VFNMADD132SS, 
	VFNMADD213SS, 
	VFNMADD231SS, 
	VFNMADD132SD, 
	VFNMADD213SD, 
	VFNMADD231SD, 
	VFNMSUB132PS, 
	VFNMSUB213PS, 
	VFNMSUB231PS, 
	VFNMSUB132PD, 
	VFNMSUB213PD, 
	VFNMSUB231PD, 
	VFNMSUB132SS, 
	VFNMSUB213SS, 
	VFNMSUB231SS, 
	VFNMSUB132SD, 
	VFNMSUB213SD, 
	VFNMSUB231SD, 
	VFMADDSUB132PS, 
	VFMADDSUB213PS, 
	VFMADDSUB231PS, 
	VFMADDSUB132PD, 
	VFMADDSUB213PD, 
	VFMADDSUB231PD, 
	VFMSUBADD132PS, 
	VFMSUBADD213PS, 
	VFMSUBADD231PS, 
	VFMSUBADD132PD, 
	VFMSUBADD213PD, 
	VFMSUBADD231PD, 
	VCVTPH2PS, 
	VCVTPS2PH, 
	// -------------------------------------------------------------------------
	// SECTION: 4.23 AVX-512 Instructions
	// -------------------------------------------------------------------------
	VMOVDQA32, 
	VMOVDQA64, 
	VMOVDQU8, 
	VMOVDQU16, 
	VMOVDQU32, 
	VMOVDQU64, 
	VPBLENDMB, 
	VPBLENDMW, 
	VPBLENDMD, 
	VPBLENDMQ, 
	VBLENDMPS, 
	VBLENDMPD, 
	VPCMPB, 
	VPCMPUB, 
	VPCMPW, 
	VPCMPUW, 
	VPCMPD, 
	VPCMPUD, 
	VPCMPQ, 
	VPCMPUQ, 
	VPTESTMB, 
	VPTESTMW, 
	VPTESTMD, 
	VPTESTMQ, 
	VPTESTNMB, 
	VPTESTNMW, 
	VPTESTNMD, 
	VPTESTNMQ, 
	VPCOMPRESSD, 
	VPCOMPRESSQ, 
	VCOMPRESSPS, 
	VCOMPRESSPD, 
	VPEXPANDD, 
	VPEXPANDQ, 
	VEXPANDPS, 
	VEXPANDPD, 
	VPCONFLICTD, 
	VPCONFLICTQ, 
	VPLZCNTD, 
	VPLZCNTQ, 
	VPERMI2B, 
	VPERMI2W, 
	VPERMI2D, 
	VPERMI2Q, 
	VPERMI2PS, 
	VPERMI2PD, 
	VPERMT2B, 
	VPERMT2W, 
	VPERMT2D, 
	VPERMT2Q, 
	VPERMT2PS, 
	VPERMT2PD, 
	VPERMB, 
	VPERMW, 
	VPMOVB2M, 
	VPMOVW2M, 
	VPMOVD2M, 
	VPMOVQ2M, 
	VPMOVM2B, 
	VPMOVM2W, 
	VPMOVM2D, 
	VPMOVM2Q, 
	VPMOVQB, 
	VPMOVSQB, 
	VPMOVUSQB, 
	VPMOVQW, 
	VPMOVSQW, 
	VPMOVUSQW, 
	VPMOVQD, 
	VPMOVSQD, 
	VPMOVUSQD, 
	VPMOVDB, 
	VPMOVSDB, 
	VPMOVUSDB, 
	VPMOVDW, 
	VPMOVSDW, 
	VPMOVUSDW, 
	VPMOVWB, 
	VPMOVSWB, 
	VPMOVUSWB, 
	VPROLD, 
	VPROLQ, 
	VPROLVD, 
	VPROLVQ, 
	VPRORD, 
	VPRORQ, 
	VPRORVD, 
	VPRORVQ, 
	VPSCATTERDD, 
	VPSCATTERDQ, 
	VPSCATTERQD, 
	VPSCATTERQQ, 
	VSCATTERDPS, 
	VSCATTERDPD, 
	VSCATTERQPS, 
	VSCATTERQPD, 
	VPSRAVQ, 
	VPSRAVW, 
	VPSLLVW, 
	VPSRLVW, 
	VRANGEPS, 
	VRANGEPD, 
	VRANGESS, 
	VRANGESD, 
	VREDUCEPS, 
	VREDUCEPD, 
	VREDUCESS, 
	VREDUCESD, 
	VRNDSCALEPS, 
	VRNDSCALEPD, 
	VRNDSCALESS, 
	VRNDSCALESD, 
	VRSQRT14PS, 
	VRSQRT14PD, 
	VRSQRT14SS, 
	VRSQRT14SD, 
	VRCP14PS, 
	VRCP14PD, 
	VRCP14SS, 
	VRCP14SD, 
	VSCALEFPS, 
	VSCALEFPD, 
	VSCALEFSS, 
	VSCALEFSD, 
	VGETEXPPS, 
	VGETEXPPD, 
	VGETEXPSS, 
	VGETEXPSD, 
	VGETMANTPS, 
	VGETMANTPD, 
	VGETMANTSS, 
	VGETMANTSD, 
	VFIXUPIMMPS, 
	VFIXUPIMMPD, 
	VFIXUPIMMSS, 
	VFIXUPIMMSD, 
	VFPCLASSPS, 
	VFPCLASSPD, 
	VFPCLASSSS, 
	VFPCLASSSD, 
	VALIGNQ, 
	VALIGND, 
	VDBPSADBW, 
	VPTERNLOGD, 
	VPTERNLOGQ, 
	VPDPWSSD, 
	VPMULTISHIFTQB, 
	KADDW, 
	KADDB, 
	KADDQ, 
	KADDD, 
	KANDW, 
	KANDB, 
	KANDQ, 
	KANDD, 
	KANDNW, 
	KANDNB, 
	KANDNQ, 
	KANDND, 
	KMOVW, 
	KMOVB, 
	KMOVQ, 
	KMOVD, 
	KNOTW, 
	KNOTB, 
	KNOTQ, 
	KNOTD, 
	KORW, 
	KORB, 
	KORQ, 
	KORD, 
	KORTESTW, 
	KORTESTB, 
	KORTESTQ, 
	KORTESTD, 
	KSHIFTLW, 
	KSHIFTLB, 
	KSHIFTLQ, 
	KSHIFTLD, 
	KSHIFTRW, 
	KSHIFTRB, 
	KSHIFTRQ, 
	KSHIFTRD, 
	KTESTW, 
	KTESTB, 
	KTESTQ, 
	KTESTD, 
	KUNPCKBW, 
	KUNPCKWD, 
	KUNPCKDQ, 
	KXNORW, 
	KXNORB, 
	KXNORQ, 
	KXNORD, 
	KXORW, 
	KXORB, 
	KXORQ, 
	KXORD, 
	// -------------------------------------------------------------------------
	// SECTION: 4.24 x87 FPU Instructions
	// -------------------------------------------------------------------------
	FADD, 
	FADDP, 
	FIADD, 
	FSUB, 
	FSUBP, 
	FISUB, 
	FSUBR, 
	FSUBRP, 
	FISUBR, 
	FMUL, 
	FMULP, 
	FIMUL, 
	FDIV, 
	FDIVP, 
	FIDIV, 
	FDIVR, 
	FDIVRP, 
	FIDIVR, 
	FSQRT, 
	FABS, 
	FCHS, 
	FPREM, 
	FPREM1, 
	FRNDINT, 
	FSCALE, 
	FXTRACT, 
	FXAM, 
	FLD, 
	FILD, 
	FBLD, 
	FST, 
	FSTP, 
	FIST, 
	FISTP, 
	FISTTP, 
	FBSTP, 
	FXCH, 
	FCMOVB, 
	FCMOVE, 
	FCMOVBE, 
	FCMOVU, 
	FCMOVNB, 
	FCMOVNE, 
	FCMOVNBE, 
	FCMOVNU, 
	FCOM, 
	FCOMP, 
	FCOMPP, 
	FICOM, 
	FICOMP, 
	FCOMI, 
	FCOMIP, 
	FUCOMI, 
	FUCOMIP, 
	FUCOM, 
	FUCOMP, 
	FUCOMPP, 
	FTST, 
	FLDZ, 
	FLD1, 
	FLDPI, 
	FLDL2T, 
	FLDL2E, 
	FLDLG2, 
	FLDLN2, 
	FSIN, 
	FCOS, 
	FSINCOS, 
	FPTAN, 
	FPATAN, 
	F2XM1, 
	FYL2X, 
	FYL2XP1, 
	FINIT, 
	FNINIT, 
	FINCSTP, 
	FDECSTP, 
	FFREE, 
	FFREEP, 
	FNOP, 
	FWAIT, 
	FCLEX, 
	FNCLEX, 
	FSTCW, 
	FNSTCW, 
	FLDCW, 
	FSTENV, 
	FNSTENV, 
	FLDENV, 
	FSAVE, 
	FNSAVE, 
	FRSTOR, 
	FSTSW, 
	FNSTSW, 
	FXSAVE, 
	FXSAVE64, 
	FXRSTOR, 
	FXRSTOR64, 
	// -------------------------------------------------------------------------
	// SECTION: 4.25 System Instructions
	// -------------------------------------------------------------------------
	LGDT, 
	SGDT, 
	LIDT, 
	SIDT, 
	LLDT, 
	SLDT, 
	LTR, 
	STR, 
	LMSW, 
	SMSW, 
	CLTS, 
	ARPL, 
	LAR, 
	LSL, 
	VERR, 
	VERW, 
	INVD, 
	WBINVD, 
	INVLPG, 
	INVPCID, 
	RSM, 
	RDMSR, 
	WRMSR, 
	// -------------------------------------------------------------------------
	// SECTION: 4.26 VMX Instructions
	// -------------------------------------------------------------------------
	VMCALL, 
	VMLAUNCH, 
	VMRESUME, 
	VMXOFF, 
	VMXON, 
	VMCLEAR, 
	VMPTRLD, 
	VMPTRST, 
	VMREAD, 
	VMWRITE, 
	VMFUNC, 
	INVEPT, 
	INVVPID, 
	// -------------------------------------------------------------------------
	// SECTION: 4.27 Miscellaneous Extensions
	// -------------------------------------------------------------------------
	ENCLS, 
	ENCLU, 
	ENCLV, 
	RDPKRU, 
	WRPKRU, 
	INCSSPD, 
	INCSSPQ, 
	RDSSPD, 
	RDSSPQ, 
	SAVEPREVSSP, 
	RSTORSSP, 
	WRSSD, 
	WRSSQ, 
	WRUSSD, 
	WRUSSQ, 
	SETSSBSY, 
	CLRSSBSY, 
	ENDBR64, 
	ENDBR32, 
	XSAVE, 
	XSAVE64, 
	XRSTOR, 
	XRSTOR64, 
	XSAVEOPT, 
	XSAVEOPT64, 
	XSAVEC, 
	XSAVEC64, 
	XSAVES, 
	XSAVES64, 
	XRSTORS, 
	XRSTORS64, 
	PREFETCHT0, 
	PREFETCHT1, 
	PREFETCHT2, 
	PREFETCHNTA, 
	PREFETCHW, 
	CLFLUSHOPT, 
	CLWB, 
	CLDEMOTE, 
	BSWAP, 
	CMPXCHG, 
	CMPXCHG8B, 
	CMPXCHG16B, 
	XADD, 
	BOUND, 
	ENTER, 
	LEAVE, 
	XLAT, 
	XLATB, 
	MOVBE, 
	RDRAND, 
	RDSEED, 
	// -------------------------------------------------------------------------
	// SECTION: 4.28 Additional System / GPR Instructions
	// -------------------------------------------------------------------------
	SWAPGS, 
	MONITOR, 
	MWAIT, 
	CLAC, 
	STAC, 
	RDFSBASE, 
	RDGSBASE, 
	WRFSBASE, 
	WRGSBASE, 
	PTWRITE, 
	RDPID, 
	WBNOINVD, 
	SERIALIZE, 
	PREFETCH, 
	IN, 
	OUT, 
	// -------------------------------------------------------------------------
	// SECTION: 4.29 WAITPKG Instructions
	// -------------------------------------------------------------------------
	TPAUSE, 
	UMONITOR, 
	UMWAIT, 
	// -------------------------------------------------------------------------
	// SECTION: 4.30 Direct Store / Enqueue Store Instructions
	// -------------------------------------------------------------------------
	MOVDIRI, 
	MOVDIR64B, 
	ENQCMD, 
	ENQCMDS, 
	// -------------------------------------------------------------------------
	// SECTION: 4.31 Remote Atomic Operations (RAO-INT)
	// -------------------------------------------------------------------------
	AADD, 
	AAND, 
	AOR, 
	AXOR, 
	// -------------------------------------------------------------------------
	// SECTION: 4.32 Restricted Transactional Memory (RTM)
	// -------------------------------------------------------------------------
	XEND, 
	XTEST, 
	// -------------------------------------------------------------------------
	// SECTION: 4.33 AMD SVM (Secure Virtual Machine) Instructions
	// -------------------------------------------------------------------------
	VMRUN, 
	VMMCALL, 
	VMLOAD, 
	VMSAVE, 
	STGI, 
	CLGI, 
	SKINIT, 
	INVLPGA, 
	INVLPGB, 
	TLBSYNC, 
	// -------------------------------------------------------------------------
	// SECTION: 4.34 AMD SEV-SNP Instructions
	// -------------------------------------------------------------------------
	PVALIDATE, 
	RMPADJUST, 
	RMPUPDATE, 
	PSMASH, 
	// -------------------------------------------------------------------------
	// SECTION: 4.35 AMD Miscellaneous Instructions
	// -------------------------------------------------------------------------
	CLZERO, 
	MONITORX, 
	MWAITX, 
	RDPRU, 
	MCOMMIT, 
}

Mnemonic_Alias :: struct {
	alias:     Mnemonic,
	// never produced by the decoder
	canonical: Mnemonic,
}

ModRM_Info :: struct #packed {
	mod:       u8,
	reg:       u8,
	rm:        u8,
	has_sib:   bool,
	disp_size: u8,
}

Mode :: enum u8 {
	_64, // long mode (x86-64), default
	_32, // protected mode (i386 / IA-32)
	_16, // real mode -- declared but not yet implemented; see comment above
}

Operand :: struct #packed {
	using _: struct #raw_union {
		reg:       Register,
		// for Register kind
		mem:       Memory,
		// for Memory kind (packed)
		immediate: i64,
		// for Immediate kind
		relative:  i64,
	},
	kind:  Operand_Kind,
	size:  u8,
	// operand size in bytes (1, 2, 4, 8, 16, 32, 64)
	flags: Operand_Flags,
}

Operand_Encoding :: enum u8 {
	NONE, 
	// ModR/M based
	MR,   // operand in ModR/M r/m field (register or memory)
	REG,  // operand in ModR/M reg field
	// VEX/EVEX specific
	VVVV, // operand in VEX.vvvv
	// Opcode-embedded
	OP_R, // register encoded in low 3 bits of opcode (+rb, +rw, +rd, +ro)
	// Immediate
	IB,   // immediate byte following instruction
	IW,   // immediate word following instruction
	ID,   // immediate dword following instruction
	IQ,   // immediate qword following instruction
	// Implicit
	IMPL, // implicit operand (not encoded)
	// Special
	IS4,  // high 4 bits of 8-bit immediate (for some AVX)
	// EVEX
	AAA,  // opmask in EVEX.aaa
}

Operand_Flags :: distinct bit_field u16 {
	mask:         u8 | 3,
	zeroing:      bool | 1,
	broadcast:    Broadcast | 3,
	er_sae:       u8 | 2,
	imm_is_label: bool | 1,
}

Operand_Kind :: enum u8 {
	NONE, 
	REGISTER, 
	MEMORY, 
	IMMEDIATE, 
	RELATIVE,  // PC-relative target (label or raw offset)
}

Operand_Set :: distinct bit_set[int; u8]

Operand_Type :: enum u8 {
	NONE, 
	// GPR by size
	R8,        // 8-bit register
	R16,       // 16-bit register
	R32,       // 32-bit register
	R64,       // 64-bit register
	// GPR or memory
	RM8,       // r/m8
	RM16,      // r/m16
	RM32,      // r/m32
	RM64,      // r/m64
	// Memory only (for LEA, etc.)
	M,         // any memory
	M8,        // memory 8-bit
	M16,       // memory 16-bit
	M32,       // memory 32-bit
	M64,       // memory 64-bit
	M80,       // memory 80-bit (x87)
	M128,      // memory 128-bit
	M256,      // memory 256-bit
	M512,      // memory 512-bit
	// Immediates
	IMM8,      // 8-bit immediate
	IMM16,     // 16-bit immediate
	IMM32,     // 32-bit immediate
	IMM64,     // 64-bit immediate (only for MOV r64, imm64)
	// Sign-extended immediates
	IMM8SX,    // 8-bit sign-extended to operand size
	// Relative offsets
	REL8,      // 8-bit relative
	REL32,     // 32-bit relative
	// Fixed registers (implicit)
	AL_IMPL,   // implicit AL
	AX_IMPL,   // implicit AX
	EAX_IMPL,  // implicit EAX
	RAX_IMPL,  // implicit RAX
	CL_IMPL,   // implicit CL (for shifts)
	DX_IMPL,   // implicit DX (for IN/OUT)
	ONE_IMPL,  // implicit 1 (for shifts)
	// Segment registers
	SREG,      // segment register
	// Control/debug registers
	CR,        // control register
	DR,        // debug register
	// Vector registers
	XMM,       // XMM register
	YMM,       // YMM register
	ZMM,       // ZMM register
	// Vector register or memory
	XMM_M32,   // xmm or m32
	XMM_M64,   // xmm or m64
	XMM_M128,  // xmm or m128
	YMM_M256,  // ymm or m256
	ZMM_M512,  // zmm or m512
	// MMX
	MM,        // MMX register
	MM_M64,    // MMX or m64
	// x87 FPU
	ST0_IMPL,  // implicit ST(0)
	STI,       // ST(i) register
	// Implicit XMM0 (for BLENDV, SHA256RNDS2)
	XMM0_IMPL, // implicit XMM0
	// Opmask
	K,         // opmask register
	K_M8,      // opmask or m8
	K_M16,     // opmask or m16
	K_M32,     // opmask or m32
	K_M64,     // opmask or m64
	// Special
	MOFFS8,    // memory offset 8-bit (MOV AL, moffs)
	MOFFS16,   // memory offset 16-bit
	MOFFS32,   // memory offset 32-bit
	MOFFS64,   // memory offset 64-bit
	// Far pointers
	PTR16_16,  // 16:16 far pointer
	PTR16_32,  // 16:32 far pointer
	PTR16_64,  // 16:64 far pointer
	M16_16,    // memory 16:16
	M16_32,    // memory 16:32
	M16_64,    // memory 16:64
}

Print_Options :: rexcode_isa.Print_Options

Print_Result :: rexcode_isa.Print_Result

Recipe_Flags :: distinct bit_field u8 {
	eligible:     bool | 1,
	reg_from_ext: bool | 1,
	has_modrm:    bool | 1,
	force_rex_w:  bool | 1,
	could_spl:    bool | 1,
	default_64:   bool | 1,
}

Register :: distinct u16

Relocation :: struct #packed {
	offset:   u32,
	// byte offset in output where fixup needed
	label_id: u32,
	// label ID this references
	addend:   i32,
	// addend for relocation calculation
	type:     Relocation_Type,
	size:     u8,
	// bytes to patch (1, 4, or 8)
	inst_idx: u16,
}

Relocation_Type :: enum u8 {
	NONE  = 0, 
	REL8,      // 8-bit PC-relative (short jump)
	REL32,     // 32-bit PC-relative (call, jmp, RIP-relative)
	ABS32,     // 32-bit absolute address
	ABS64,     // 64-bit absolute address (movabs)
}

Rep :: enum u8 {
	NONE, 
	REP,   // REP/REPE/REPZ
	REPNE, // REPNE/REPNZ
}

SIB_Info :: struct #packed {
	scale: u8,
	index: u8,
	base:  u8,
}

SREG :: enum u8 {
	ES, 
	CS, 
	SS, 
	DS, 
	FS, 
	GS, 
}

ST :: enum u8 {
	ST0, 
	ST1, 
	ST2, 
	ST3, 
	ST4, 
	ST5, 
	ST6, 
	ST7, 
}

Side_Effect :: enum u8 {
	FENCE,            // memory-ordering barrier (LFENCE/SFENCE/MFENCE, LOCK)
	SERIALIZING,      // architecturally serializing (drains pipeline)
	HINT,             // microarchitectural hint, architecturally inert (PAUSE/PREFETCH*/ENDBR)
	CACHE,            // cache-line maintenance with coherence effects (CLFLUSH/CLWB)
	TRAP,             // may deliberately raise a fault (#UD/#BR): UD0-2, BOUND
	INTERRUPT,        // software interrupt / syscall gate
	HALT,             // stops execution until an external event
	PRIVILEGED,       // requires CPL0 / reads-writes supervisor machine state
	CONTROL,          // alters control flow (writes RIP): branches, calls, returns
	CET,              // control-flow-enforcement: landing pads, shadow-stack ops
	NONDETERMINISTIC, 
}

Side_Effects :: distinct bit_set[Side_Effect; u16]

Token :: rexcode_isa.Token

Token_Kind :: rexcode_isa.Token_Kind

VEX_Decode_Entry :: struct {
	esc:      Escape,
	prefix:   u8,
	opcode:   u8,
	ext:      u8,
	vex_w:    VEX_W,
	vex_l:    VEX_L,
	mnemonic: Mnemonic,
	ops:      [4]Operand_Type,
	enc:      [4]Operand_Encoding,
	flags:    Encoding_Flags,
}

VEX_L :: enum u8 {
	LIG, // L ignored
	L0,  // L = 0 (128-bit / scalar)
	L1,  // L = 1 (256-bit)
	L2,  // L = 2 (512-bit, EVEX only)
}

VEX_Type :: enum u8 {
	NONE, // legacy encoding
	VEX,  // VEX prefix (AVX)
	EVEX, // EVEX prefix (AVX-512)
	XOP,  // XOP prefix (AMD)
}

VEX_W :: enum u8 {
	WIG, // W ignored
	W0,  // W = 0
	W1,  // W = 1
}

XMM :: enum u8 {
	XMM0, 
	XMM1, 
	XMM2, 
	XMM3, 
	XMM4, 
	XMM5, 
	XMM6, 
	XMM7, 
	XMM8, 
	XMM9, 
	XMM10, 
	XMM11, 
	XMM12, 
	XMM13, 
	XMM14, 
	XMM15, 
	XMM16, 
	XMM17, 
	XMM18, 
	XMM19, 
	XMM20, 
	XMM21, 
	XMM22, 
	XMM23, 
	XMM24, 
	XMM25, 
	XMM26, 
	XMM27, 
	XMM28, 
	XMM29, 
	XMM30, 
	XMM31, 
}

YMM :: enum u8 {
	YMM0, 
	YMM1, 
	YMM2, 
	YMM3, 
	YMM4, 
	YMM5, 
	YMM6, 
	YMM7, 
	YMM8, 
	YMM9, 
	YMM10, 
	YMM11, 
	YMM12, 
	YMM13, 
	YMM14, 
	YMM15, 
	YMM16, 
	YMM17, 
	YMM18, 
	YMM19, 
	YMM20, 
	YMM21, 
	YMM22, 
	YMM23, 
	YMM24, 
	YMM25, 
	YMM26, 
	YMM27, 
	YMM28, 
	YMM29, 
	YMM30, 
	YMM31, 
}

ZMM :: enum u8 {
	ZMM0, 
	ZMM1, 
	ZMM2, 
	ZMM3, 
	ZMM4, 
	ZMM5, 
	ZMM6, 
	ZMM7, 
	ZMM8, 
	ZMM9, 
	ZMM10, 
	ZMM11, 
	ZMM12, 
	ZMM13, 
	ZMM14, 
	ZMM15, 
	ZMM16, 
	ZMM17, 
	ZMM18, 
	ZMM19, 
	ZMM20, 
	ZMM21, 
	ZMM22, 
	ZMM23, 
	ZMM24, 
	ZMM25, 
	ZMM26, 
	ZMM27, 
	ZMM28, 
	ZMM29, 
	ZMM30, 
	ZMM31, 
}

@(rodata)
CLOBBER_FORMS: []Clobber = …

@(rodata)
DECODE_INDEX_ESC_0F: []Decode_Index = …

@(rodata)
DECODE_INDEX_ESC_0F38: []Decode_Index = …

@(rodata)
DECODE_INDEX_ESC_0F3A: []Decode_Index = …

@(rodata)
DECODE_INDEX_LEGACY: []Decode_Index = …

@(rodata)
ENCODE_FORMS: []Encoding = …

@(rodata)
ENCODE_RECIPES: []Form_Recipe = …

@(rodata)
ENCODE_RUNS: []Encode_Run = …

@(rodata)
EVEX_DECODE_ENTRIES: []VEX_Decode_Entry = …

@(rodata)
EVEX_INDEX_0F: []Decode_Index = …

@(rodata)
EVEX_INDEX_0F38: []Decode_Index = …

@(rodata)
EVEX_INDEX_0F3A: []Decode_Index = …

@(rodata)
LEGACY_DECODE_ENTRIES: []Decode_Entry = …

@(rodata)
MNEMONIC_ALIASES: [57]Mnemonic_Alias = …

@(rodata)
MODRM_TABLE: []ModRM_Info = …

@(rodata)
PREFIX_SEGMENT_TABLE: [6]Register = …

@(rodata)
SIB_TABLE: []SIB_Info = …

@(rodata)
VEX_DECODE_ENTRIES: []VEX_Decode_Entry = …

@(rodata)
VEX_INDEX_0F: []Decode_Index = …

@(rodata)
VEX_INDEX_0F38: []Decode_Index = …

@(rodata)
VEX_INDEX_0F3A: []Decode_Index = …