package core:rexcode/isa/ppc_vle

Source

Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	mode:     Mode,
	// 1
	flags:    Encoding_Flags,
}

Decode_Index :: struct #packed {
	start: u32,
	count: u16,
	_:     u16,
}

Encode_Run :: struct {
	start: u32,
	count: u32,
}

Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	mode:     Mode,
	// 1
	flags:    Encoding_Flags,
}

Encoding_Flags :: distinct bit_field u8 {
	short:       bool | 1,
	cond_branch: bool | 1,
	writes_lr:   bool | 1,
	sets_cr0:    bool | 1,
	_:           u8 | 4,
}

Error :: rexcode_isa.Error

Error_Code :: rexcode_isa.Error_Code

Feature :: enum u8 {
	BASE, 
	LSP, 
	SPE, 
}

Instruction :: struct #packed {
	ops:           [4]Operand `fmt:"v,operand_count"`,
	mnemonic:      Mnemonic,
	operand_count: u8,
	flags:         Instruction_Flags,
	mode:          Mode,
	length:        u8,
	// 2 or 4
	form_id:       u16,
}

Instruction_Flags :: distinct bit_field u8 {
	sets_cr0: bool | 1,
	has_oe:   bool | 1,
	lk:       bool | 1,
	aa:       bool | 1,
	_:        u8 | 4,
}

Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}

Label_Definition :: rexcode_isa.Label_Definition

Label_Map :: rexcode_isa.Label_Map

Label_Names :: map[rexcode_isa.Label_Offset]string

Label_Offset :: rexcode_isa.Label_Offset

Memory :: struct #packed {
	base:  Register,
	index: Register,
	disp:  i64,
}

Mnemonic :: enum u16 {
	INVALID      = 0, 
	// ---- 16-bit short (se_*) ----
	SE_ILLEGAL, 
	SE_ISYNC, 
	SE_SC, 
	SE_BLR, 
	SE_BLRL, 
	SE_BCTR, 
	SE_BCTRL, 
	SE_RFI, 
	SE_RFCI, 
	SE_RFDI, 
	SE_RFMCI, 
	SE_RFGI, 
	SE_NOT, 
	SE_NEG, 
	SE_MFLR, 
	SE_MTLR, 
	SE_MFCTR, 
	SE_MTCTR, 
	SE_EXTZB, 
	SE_EXTSB, 
	SE_EXTZH, 
	SE_EXTSH, 
	SE_MR, 
	SE_MTAR, 
	SE_MFAR, 
	SE_ADD, 
	SE_MULLW, 
	SE_SUB, 
	SE_SUBF, 
	SE_CMP, 
	SE_CMPL, 
	SE_CMPH, 
	SE_CMPHL, 
	SE_SRW, 
	SE_SRAW, 
	SE_SLW, 
	SE_OR, 
	SE_ANDC, 
	SE_AND, 
	SE_AND_DOT, 
	SE_ADDI, 
	SE_CMPLI, 
	SE_SUBI, 
	SE_SUBI_DOT, 
	SE_CMPI, 
	SE_BMASKI, 
	SE_ANDI, 
	SE_NOP, 
	SE_LI, 
	SE_BCLRI, 
	SE_BGENI, 
	SE_BSETI, 
	SE_BTSTI, 
	SE_SRWI, 
	SE_SRAWI, 
	SE_SLWI, 
	SE_LBZ, 
	SE_STB, 
	SE_LHZ, 
	SE_STH, 
	SE_LWZ, 
	SE_STW, 
	SE_BGE, 
	SE_BNL, 
	SE_BLE, 
	SE_BNG, 
	SE_BNE, 
	SE_BNS, 
	SE_BNU, 
	SE_BF, 
	SE_BLT, 
	SE_BGT, 
	SE_BEQ, 
	SE_BSO, 
	SE_BUN, 
	SE_BT, 
	SE_BC, 
	SE_B, 
	SE_BL, 
	// ---- 32-bit (e_*) ----
	E_LBZU, 
	E_LHAU, 
	E_LHZU, 
	E_LMW, 
	E_LWZU, 
	E_STBU, 
	E_STHU, 
	E_STWU, 
	E_STMW, 
	E_LMVGPRW, 
	E_LDMVGPRW, 
	E_STMVGPRW, 
	E_LMVSPRW, 
	E_LDMVSPRW, 
	E_STMVSPRW, 
	E_LMVSRRW, 
	E_LDMVSRRW, 
	E_STMVSRRW, 
	E_LMVCSRRW, 
	E_LDMVCSRRW, 
	E_STMVCSRRW, 
	E_LMVDSRRW, 
	E_LDMVDSRRW, 
	E_STMVDSRRW, 
	E_LMVMCSRRW, 
	E_STMVMCSRRW, 
	E_ADD16I, 
	E_LA, 
	E_SUB16I, 
	E_LBZ, 
	E_STB, 
	E_LHA, 
	E_LWZ, 
	E_STW, 
	E_LHZ, 
	E_STH, 
	E_RLWIMI, 
	E_INSLWI, 
	E_INSRWI, 
	E_ROTLWI, 
	E_ROTRWI, 
	E_CLRLWI, 
	E_CLRRWI, 
	E_RLWINM, 
	E_EXTLWI, 
	E_EXTRWI, 
	E_CLRLSLWI, 
	E_CMPH, 
	E_SC, 
	E_CMPHL, 
	E_CRANDC, 
	E_CRNAND, 
	E_CRNOT, 
	E_CRNOR, 
	E_CRCLR, 
	E_CRXOR, 
	E_MCRF, 
	E_SLWI, 
	E_SLWI_DOT, 
	E_CRAND, 
	E_RLW, 
	E_RLW_DOT, 
	E_CRSET, 
	E_CREQV, 
	E_RLWI, 
	E_RLWI_DOT, 
	E_CRORC, 
	E_CRMOVE, 
	E_CROR, 
	E_SRWI, 
	E_SRWI_DOT, 
	E_BDNZ, 
	E_BDNZL, 
	E_BDZ, 
	E_BDZL, 
	E_CMPI, 
	E_CMPWI, 
	E_CMPLI, 
	E_CMPLWI, 
	E_ADDI, 
	E_SUBI, 
	E_ADDI_DOT, 
	E_ADDIC, 
	E_SUBIC, 
	E_ADDIC_DOT, 
	E_SUBIC_DOT, 
	E_MULLI, 
	E_SUBFIC, 
	E_SUBFIC_DOT, 
	E_ANDI, 
	E_ANDI_DOT, 
	E_NOP, 
	E_ORI, 
	E_ORI_DOT, 
	E_XORI, 
	E_XORI_DOT, 
	E_LIS, 
	E_AND2IS_DOT, 
	E_OR2IS, 
	E_AND2I_DOT, 
	E_OR2I, 
	E_CMPHL16I, 
	E_CMPH16I, 
	E_CMPL16I, 
	E_MULL2I, 
	E_CMP16I, 
	E_SUB2IS, 
	E_ADD2IS, 
	E_SUB2I_DOT, 
	E_ADD2I_DOT, 
	E_LI, 
	E_B, 
	E_BL, 
	E_BGE, 
	E_BGEL, 
	E_BNL, 
	E_BNLL, 
	E_BLT, 
	E_BLTL, 
	E_BGT, 
	E_BGTL, 
	E_BLE, 
	E_BLEL, 
	E_BNG, 
	E_BNGL, 
	E_BNE, 
	E_BNEL, 
	E_BEQ, 
	E_BEQL, 
	E_BSO, 
	E_BSOL, 
	E_BUN, 
	E_BUNL, 
	E_BNS, 
	E_BNSL, 
	E_BNU, 
	E_BNUL, 
	E_BC, 
	E_BCL, 
	E_BF, 
	E_BFL, 
	E_BT, 
	E_BTL, 
}

Mode :: enum u8 {
	PPC32_VLE = 0, 
}

Operand :: struct #packed {
	using _: struct #packed #raw_union {
		reg:       Register,
		mem:       Memory,
		immediate: i64,
		relative:  i64,
	},
	kind: Operand_Kind,
	size: u8,
}

Operand_Encoding :: enum u8 {
	NONE              = 0, 
	IMPL,                  // implicit / baked into bits
	// ---- 32-bit instructions (standard PPC slot positions) ----
	RT,                    // bits 21..25 (5-bit GPR destination)
	RA,                    // bits 16..20
	RB,                    // bits 11..15
	RS,                    // bits 21..25 (alias of RT used in store/X-form)
	UI16,                  // bits 0..15, unsigned 16-bit
	SI16,                  // bits 0..15, signed 16-bit
	LI20,                  // 20-bit immediate split: imm[19:16] at bits 17..20,
	//                          imm[15:11] at bits 11..15,
	//                          imm[10:0]  at bits  0..10
	SCI8,                  // 8-bit signed immediate with split scale + sign
	// ---- 32-bit branches ----
	B15,                   // bits 1..15, signed << 1 (15-bit displacement)
	B24,                   // bits 1..24, signed << 1 (24-bit displacement)
	BO32,                  // bits 20..21 (2-bit BO)
	BI32,                  // bits 16..19 (4-bit BI selecting CR bit)
	// ---- 16-bit register fields ----
	RX,                    // bits 0..3, 4-bit GPR_VLE16
	RY,                    // bits 4..7, 4-bit GPR_VLE16
	RZ,                    // alias of RY at bits 4..7
	// ---- 16-bit immediates ----
	UI5,                   // bits 4..8 (5-bit, SE_IM5 form)
	UI7,                   // bits 4..10 (7-bit, IM7 form — actually IM7 puts UI7 at bits 8..14 and RX at bits 4..7 — see encoder)
	// ---- 16-bit memory (SD4 form) ----
	SE_SD,                 // bits 8..11 unscaled (byte)
	SE_SDH,                // bits 8..11 scaled by 2 (halfword)
	SE_SDW,                // bits 8..11 scaled by 4 (word)
	// ---- 16-bit branches ----
	B8,                    // bits 0..7, signed << 1 (8-bit displacement)
	BO16,                  // bit 10 (1-bit BO in BD8IO form)
	BI16,                  // bits 8..9 (2-bit BI)
	// ---- Memory operand composites ----
	OFFSET_BASE_D,         // 32-bit D-form: RA + signed 16-bit D
	OFFSET_BASE_SD4,       // 16-bit SD4 byte memory: RX + SE_SD
	OFFSET_BASE_SD4_H,     // 16-bit SD4 halfword memory: RX + SE_SDH
	OFFSET_BASE_SD4_W,     // 16-bit SD4 word memory: RX + SE_SDW
}

Operand_Kind :: enum u8 {
	NONE, 
	REGISTER,  // mostly used for `A` in `ROL A` (implicit; rarely needed)
	IMMEDIATE, 
	MEMORY, 
	RELATIVE,  // PC-relative target (label or raw byte offset)
}

Operand_Type :: enum u8 {
	NONE        = 0, 
	GPR,             // standard 32-register GPR (5-bit field, used in 32-bit ops)
	GPR_VLE16,       // 16-register VLE subset (4-bit field) — r0..r7 + r24..r31
	GPR_OR_ZERO, 
	IMM, 
	SIMM, 
	UIMM, 
	REL, 
	MEM, 
	CR_FIELD, 
	CR_BIT, 
	SPR, 
	BO,              // branch-op selector immediate (BO16 = 1-bit, BO32 = 2-bit)
}

Print_Options :: rexcode_isa.Print_Options

Print_Result :: rexcode_isa.Print_Result

Register :: distinct u16

Relocation :: struct #packed {
	offset:   u32,
	label_id: u32,
	addend:   i32,
	type:     Relocation_Type,
	size:     u8,
	inst_idx: u16,
}

Relocation_Type :: enum u8 {
	NONE                   = 0, 
	// Internal (encoder-resolved) branch relocations
	BRANCH_BD8,                 // 8-bit signed << 1 at bits 7..0 of halfword
	BRANCH_BD15,                // 15-bit signed << 1 at bits 1..15 of low halfword
	BRANCH_BD24,                // 24-bit signed << 1 at bits 1..24 of word
	// ELF-spec relocations (linker-bound — encoder emits them but doesn't
	// resolve them locally)
	R_PPC_VLE_REL8,             // 216 — like BRANCH_BD8 but ELF-emitted
	R_PPC_VLE_REL15,            // 217
	R_PPC_VLE_REL24,            // 218
	R_PPC_VLE_LO16A,            // 219 — low 16 bits, A-form imm (I16A bit positions)
	R_PPC_VLE_LO16D,            // 220 — low 16 bits, D-form imm
	R_PPC_VLE_HI16A,            // 221 — high 16 bits, A-form
	R_PPC_VLE_HI16D,            // 222 — high 16 bits, D-form
	R_PPC_VLE_HA16A,            // 223 — high-adjusted 16 bits, A-form
	R_PPC_VLE_HA16D,            // 224 — high-adjusted 16 bits, D-form
	R_PPC_VLE_SDA21,            // 225 — 21-bit small-data-area
	R_PPC_VLE_SDA21_LO,         // 226 — like SDA21 but no overflow check
	R_PPC_VLE_SDAREL_LO16A,     // 227
	R_PPC_VLE_SDAREL_LO16D,     // 228
	R_PPC_VLE_SDAREL_HI16A,     // 229
	R_PPC_VLE_SDAREL_HI16D,     // 230
	R_PPC_VLE_SDAREL_HA16A,     // 231
	R_PPC_VLE_SDAREL_HA16D,     // 232
	R_PPC_VLE_ADDR20,           // 233 — 20-bit absolute (LI20)
}

Token :: rexcode_isa.Token

Token_Kind :: rexcode_isa.Token_Kind

@(rodata)
DECODE_BUCKET_LIST: []u16 = …

@(rodata)
DECODE_ENTRIES: []Decode_Entry = …

@(rodata)
DECODE_FORM_IDX: []u16 = …

@(rodata)
DECODE_INDEX_LONG: []Decode_Index = …

@(rodata)
DECODE_INDEX_SHORT: []Decode_Index = …

@(rodata)
ENCODE_FORMS: []Encoding = …

@(rodata)
ENCODE_RUNS: []Encode_Run = …