Address_Mode :: enum u8 {
	OFFSET,         // [Xn, #imm]   (imm may be 0)
	PRE_INDEXED,    // [Xn, #imm]!
	POST_INDEXED,   // [Xn], #imm
	REG_OFFSET,     // [Xn, Xm{, LSL #s}]
	EXT_REG_OFFSET, // [Xn, Wm, SXTW|UXTW|SXTX #s]
	LITERAL,        // PC-rel target (LDR literal)
}

Cond ¶
Source

Cond :: enum u8 {
	EQ = 0, 
	NE = 1, 
	CS = 2,  // unsigned higher or same (alias HS)
	CC = 3,  // unsigned lower (alias LO)
	MI = 4, 
	PL = 5, 
	VS = 6, 
	VC = 7, 
	HI = 8, 
	LS = 9, 
	GE = 10, 
	LT = 11, 
	GT = 12, 
	LE = 13, 
	AL = 14, 
	NV = 15, 
}

Related Procedures With Parameters

Related Constants

Decode_Entry ¶
Source

Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4 -- static field pattern
	mask:     u32,
	// 4 -- which bits are static
	feature:  Feature,
	// 1
	flags:    Encoding_Flags,
}

Decode_Index ¶
Source

Decode_Index :: struct #packed {
	start: u16,
	count: u16,
}

Encode_Run ¶
Source

Encode_Run :: struct {
	start: u32,
	count: u32,
}

Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS.

Encoding_Flags ¶
Source

Encoding_Flags :: distinct bit_field u8 {
	branch:      bool | 1,
	cond_branch: bool | 1,
	writes_pc:   bool | 1,
	sets_flags:  bool | 1,
	is_64:       bool | 1,
	_:           u8 | 3,
}

Endianness ¶
Source

Endianness :: enum u8 {
	LITTLE = 0, 
	BIG    = 1, 
}

Endianness for storing 32-bit instructions to []u8. ARM defaults to little-endian instruction storage on every modern platform; BE-8 mode stores data BE but instructions LE; BE-32 (legacy) is rare on AArch64 and unsupported in mainstream toolchains.

Related Procedures With Parameters

Error ¶
Source

Error :: rexcode_isa.Error

Error_Code ¶
Source

Error_Code :: rexcode_isa.Error_Code

Extend ¶
Source

Extend :: enum u8 {
	UXTB = 0, 
	UXTH = 1, 
	UXTW = 2, 
	UXTX = 3, 
	SXTB = 4, 
	SXTH = 5, 
	SXTW = 6, 
	SXTX = 7, 
}

Related Procedures With Parameters

Extended_Reg ¶
Source

Extended_Reg :: struct #packed {
	reg:    Register,
	// 2
	extend: Extend,
	// 1
	amount: u8,
}

Feature ¶
Source

Feature :: enum u8 {
	BASE,   // AArch64 base integer ISA
	FP,     // scalar FP (FPSCR-using; FADD/FCMP/FCVT/etc.)
	NEON,   // Advanced SIMD vector ops
	CRYPTO, // AES, SHA1, SHA2, SHA3, SM3, SM4
	CRC32,  // CRC32B/H/W/X + CRC32CB/H/W/X
	LSE,    // Large System Extensions (atomic LDADD/LDCLR/...)
	LSE2,   // single-copy-atomicity load/store
	FP16,   // half-precision FP arithmetic
	BF16,   // BFloat16
	DOT,    // SDOT/UDOT integer dot product
	PAC,    // Pointer Authentication
	BTI,    // Branch Target Indicator
	MTE,    // Memory Tagging
	SVE,    // Scalable Vector Extension
	SVE2, 
	SME,    // Scalable Matrix Extension
	AMX,    // Apple Matrix Extension (undocumented A13+/M1+ coprocessor)
}

Architectural feature this entry requires (for filtering and tagging at decode/print time).

Instruction ¶
Source

Instruction :: struct #packed {
	ops:           [4]Operand `fmt:"v,operand_count"`,
	// 4 * size_of(Operand)
	mnemonic:      Mnemonic,
	// 2
	operand_count: u8,
	// 1
	flags:         Instruction_Flags,
	// 1
	length:        u8,
	// 1 -- always 4
	_:             [3]u8,
}

Related Procedures With Returns

Instruction_Flags ¶
Source

Instruction_Flags :: distinct bit_field u8 {
	_: u8 | 8,
}

Instruction_Info ¶
Source

Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}

Label_Definition ¶
Source

Label_Definition :: rexcode_isa.Label_Definition

Related Constants

LABEL_UNDEFINED

Label_Map ¶
Source

Label_Map :: rexcode_isa.Label_Map

Memory ¶
Source

Memory :: struct #packed {
	base:   Register,
	// 2
	index:  Register,
	// 2  (NONE for OFFSET/PRE/POST/LITERAL)
	disp:   i32,
	//     OFFSET supports 0..32760 scaled via imm12*size)
	extend: Extend,
	// 1  (for EXT_REG_OFFSET; UXTX otherwise)
	shift:  u8,
	//     shift amount for shifted-register operands
	//     when reused there)
	mode:   Address_Mode,
	// 1
	_:      u8,
}

16-byte memory operand: base + optional index + signed disp + addressing metadata. Index is NONE for non-register-offset modes.

Related Procedures With Parameters

Related Procedures With Returns

Mnemonic ¶
Source

Mnemonic :: enum u16 {
	INVALID              = 0, 
	ADD_IMM, 
	ADDS_IMM, 
	SUB_IMM, 
	SUBS_IMM,                 // optional LSL #12 carried in shift field
	MOVZ, 
	MOVN, 
	MOVK,                     // 16-bit imm + 2-bit hw
	ADR, 
	ADRP,                     // PC-relative address
	ADD_SR, 
	ADDS_SR, 
	SUB_SR, 
	SUBS_SR, 
	AND_SR, 
	ANDS_SR, 
	ORR_SR, 
	EOR_SR, 
	BIC_SR, 
	BICS_SR, 
	ORN_SR, 
	EON_SR, 
	ADD_ER, 
	ADDS_ER, 
	SUB_ER, 
	SUBS_ER, 
	LSLV, 
	LSRV, 
	ASRV, 
	RORV,                     // also printed as LSL/LSR/ASR/ROR
	UDIV, 
	SDIV, 
	MADD, 
	MSUB,                     // 64x64+64 -> 64 (or 32 variant)
	SMADDL, 
	SMSUBL, 
	UMADDL, 
	UMSUBL,                   // 32x32+64 -> 64
	SMULH, 
	UMULH,                    // 64x64 -> high 64
	CLZ, 
	CLS, 
	RBIT, 
	REV, 
	REV16, 
	REV32, 
	CSEL, 
	CSINC, 
	CSINV, 
	CSNEG, 
	CCMP_REG, 
	CCMP_IMM, 
	CCMN_REG, 
	CCMN_IMM, 
	EXTR, 
	B, 
	BL,                       // 26-bit PC-rel
	BR, 
	BLR, 
	RET,                      // register indirect
	B_COND,                   // B.cond -- 19-bit PC-rel
	CBZ, 
	CBNZ,                     // 19-bit PC-rel + Rt
	TBZ, 
	TBNZ,                     // 14-bit PC-rel + bit position
	// Plain (unsigned offset / signed unscaled / pre / post)
	LDR, 
	STR,                      // X/W variants (matched by reg width)
	LDRB, 
	STRB, 
	LDRSB, 
	LDRH, 
	STRH, 
	LDRSH, 
	LDRSW, 
	// Pair
	LDP, 
	STP, 
	LDPSW, 
	// PC-relative literal
	LDR_LIT, 
	// Acquire / release
	LDAR, 
	STLR, 
	LDARB, 
	STLRB, 
	LDARH, 
	STLRH, 
	// Exclusive (load-linked / store-conditional)
	LDXR, 
	STXR, 
	LDAXR, 
	STLXR, 
	NOP, 
	YIELD, 
	WFE, 
	WFI, 
	SEV, 
	SEVL, 
	HINT, 
	MRS, 
	MSR_IMM, 
	MSR_REG, 
	ISB, 
	DSB, 
	DMB, 
	SVC, 
	HVC, 
	SMC, 
	BRK, 
	HLT, 
	ERET, 
	FMOV_REG, 
	FMOV_IMM, 
	FMOV_GEN,                 // reg-reg / imm / between int/FP
	FABS, 
	FNEG, 
	FSQRT, 
	FADD, 
	FSUB, 
	FMUL, 
	FDIV, 
	FNMUL, 
	FMADD, 
	FMSUB, 
	FNMADD, 
	FNMSUB, 
	FCMP, 
	FCMPE, 
	FCSEL, 
	FMAX, 
	FMIN, 
	FMAXNM, 
	FMINNM, 
	FCVT,                     // between single/double/half
	SCVTF, 
	UCVTF, 
	FCVTZS, 
	FCVTZU, 
	FCVTAS, 
	FCVTAU, 
	FCVTNS, 
	FCVTNU, 
	FCVTPS, 
	FCVTPU, 
	FCVTMS, 
	FCVTMU, 
	FRINTA, 
	FRINTI, 
	FRINTM, 
	FRINTN, 
	FRINTP, 
	FRINTX, 
	FRINTZ, 
	// -------------------------------------------------------------------------
	// Logical immediate (bitmask-encoded; N:imms:immr)
	// -------------------------------------------------------------------------
	AND_IMM, 
	ANDS_IMM, 
	ORR_IMM, 
	EOR_IMM, 
	TST_IMM,                  // alias of ANDS_IMM with Rd=ZR; printed separately
	// -------------------------------------------------------------------------
	// Additional load/store addressing modes
	// -------------------------------------------------------------------------
	LDUR, 
	STUR, 
	LDURB, 
	STURB, 
	LDURSB, 
	LDURH, 
	STURH, 
	LDURSH, 
	LDURSW, 
	LDR_PRE, 
	STR_PRE, 
	LDR_POST, 
	STR_POST, 
	LDRB_PRE, 
	STRB_PRE, 
	LDRB_POST, 
	STRB_POST, 
	LDRH_PRE, 
	STRH_PRE, 
	LDRH_POST, 
	STRH_POST, 
	LDR_REG, 
	STR_REG, 
	LDRB_REG, 
	STRB_REG, 
	LDRH_REG, 
	STRH_REG, 
	LDRSB_REG, 
	LDRSH_REG, 
	LDRSW_REG, 
	LDP_PRE, 
	STP_PRE, 
	LDP_POST, 
	STP_POST, 
	LDPSW_PRE, 
	LDPSW_POST, 
	LDNP, 
	STNP,                     // non-temporal pair
	LDXP, 
	STXP, 
	LDAXP, 
	STLXP,                    // exclusive pair
	LDXRB, 
	STXRB, 
	LDAXRB, 
	STLXRB,                   // exclusive byte
	LDXRH, 
	STXRH, 
	LDAXRH, 
	STLXRH,                   // exclusive halfword
	LDAPR, 
	LDAPRB, 
	LDAPRH,                   // load-acquire RCpc
	// -------------------------------------------------------------------------
	// LSE atomics (8 ops x 4 acq/rel x 2 width = 64 forms, named by op only;
	// size and acq/rel encoded in the bits + flags)
	// -------------------------------------------------------------------------
	LDADD, 
	LDADDA, 
	LDADDL, 
	LDADDAL, 
	LDCLR, 
	LDCLRA, 
	LDCLRL, 
	LDCLRAL, 
	LDEOR, 
	LDEORA, 
	LDEORL, 
	LDEORAL, 
	LDSET, 
	LDSETA, 
	LDSETL, 
	LDSETAL, 
	LDSMAX, 
	LDSMAXA, 
	LDSMAXL, 
	LDSMAXAL, 
	LDSMIN, 
	LDSMINA, 
	LDSMINL, 
	LDSMINAL, 
	LDUMAX, 
	LDUMAXA, 
	LDUMAXL, 
	LDUMAXAL, 
	LDUMIN, 
	LDUMINA, 
	LDUMINL, 
	LDUMINAL, 
	SWP, 
	SWPA, 
	SWPL, 
	SWPAL, 
	CAS, 
	CASA, 
	CASL, 
	CASAL,                    // 32/64
	CASB, 
	CASAB, 
	CASLB, 
	CASALB,                   // byte
	CASH, 
	CASAH, 
	CASLH, 
	CASALH,                   // half
	CASP, 
	CASPA, 
	CASPL, 
	CASPAL,                   // pair (W,W)/(X,X)
	// -------------------------------------------------------------------------
	// Pointer Authentication (PAC v8.3-A)
	// -------------------------------------------------------------------------
	PACIA, 
	PACIB, 
	PACDA, 
	PACDB, 
	PACIZA, 
	PACIZB, 
	PACDZA, 
	PACDZB,                   // implicit-zero variants
	AUTIA, 
	AUTIB, 
	AUTDA, 
	AUTDB, 
	AUTIZA, 
	AUTIZB, 
	AUTDZA, 
	AUTDZB, 
	PACIASP, 
	PACIBSP, 
	AUTIASP, 
	AUTIBSP,                  // hint-encoded SP variants
	PACIA1716, 
	PACIB1716, 
	AUTIA1716, 
	AUTIB1716, 
	PACGA, 
	XPACI, 
	XPACD, 
	XPACLRI, 
	RETAA, 
	RETAB, 
	BRAA, 
	BRAB, 
	BRAAZ, 
	BRABZ, 
	BLRAA, 
	BLRAB, 
	BLRAAZ, 
	BLRABZ, 
	ERETAA, 
	ERETAB, 
	// -------------------------------------------------------------------------
	// Branch Target Identification (BTI v8.5-A)
	// -------------------------------------------------------------------------
	BTI,                      // single mnemonic; modifier (c/j/jc) in operand
	// -------------------------------------------------------------------------
	// Memory Tagging Extension (MTE v8.5-A)
	// -------------------------------------------------------------------------
	IRG, 
	ADDG, 
	SUBG, 
	GMI, 
	SUBP, 
	SUBPS, 
	LDG, 
	STG, 
	ST2G, 
	STZG, 
	STZ2G, 
	STGP, 
	LDGM, 
	STGM, 
	STZGM, 
	// -------------------------------------------------------------------------
	// CRC32 (v8.0-A optional, mandatory v8.1+)
	// -------------------------------------------------------------------------
	CRC32B, 
	CRC32H, 
	CRC32W, 
	CRC32X, 
	CRC32CB, 
	CRC32CH, 
	CRC32CW, 
	CRC32CX, 
	// -------------------------------------------------------------------------
	// Crypto: AES / SHA / SM3 / SM4 / polynomial multiply
	// -------------------------------------------------------------------------
	AESE, 
	AESD, 
	AESMC, 
	AESIMC, 
	SHA1H, 
	SHA1C, 
	SHA1P, 
	SHA1M, 
	SHA1SU0, 
	SHA1SU1, 
	SHA256H, 
	SHA256H2, 
	SHA256SU0, 
	SHA256SU1, 
	SHA512H, 
	SHA512H2, 
	SHA512SU0, 
	SHA512SU1,                // v8.2-A
	EOR3, 
	BCAX, 
	RAX1, 
	XAR,                      // SHA3 v8.2-A
	SM3PARTW1, 
	SM3PARTW2, 
	SM3SS1, 
	SM3TT1A, 
	SM3TT1B, 
	SM3TT2A, 
	SM3TT2B, 
	SM4E, 
	SM4EKEY, 
	PMULL, 
	PMULL2, 
	// -------------------------------------------------------------------------
	// FP scalar half-precision (FP16)
	// -------------------------------------------------------------------------
	FABS_H, 
	FNEG_H, 
	FSQRT_H, 
	FADD_H, 
	FSUB_H, 
	FMUL_H, 
	FDIV_H, 
	FNMUL_H, 
	FMADD_H, 
	FMSUB_H, 
	FNMADD_H, 
	FNMSUB_H, 
	FCMP_H, 
	FCMPE_H, 
	FCSEL_H, 
	FMAX_H, 
	FMIN_H, 
	FMAXNM_H, 
	FMINNM_H, 
	FCVT_H_S, 
	FCVT_H_D, 
	FCVT_S_H, 
	FCVT_D_H,                 // half<->single/double cross
	FMOV_H, 
	SCVTF_H, 
	UCVTF_H, 
	FCVTZS_H, 
	FCVTZU_H, 
	// -------------------------------------------------------------------------
	// BFloat16 (BF16; v8.6-A)
	// -------------------------------------------------------------------------
	BFCVT,                    // BFloat16 from single
	BFDOT, 
	BFMMLA, 
	BFMLALB, 
	BFMLALT, 
	BFCVTN, 
	BFCVTN2, 
	// 3-same arithmetic
	ADD_V, 
	SUB_V, 
	MUL_V, 
	MLA_V, 
	MLS_V, 
	NEG_V, 
	ABS_V, 
	SHADD, 
	UHADD, 
	SHSUB, 
	UHSUB, 
	SRHADD, 
	URHADD, 
	SQADD, 
	UQADD, 
	SQSUB, 
	UQSUB, 
	SMAX, 
	UMAX, 
	SMIN, 
	UMIN, 
	SABD, 
	UABD, 
	SABA, 
	UABA, 
	ADDP_V, 
	ADDV, 
	SADDLP, 
	UADDLP, 
	SADALP, 
	UADALP, 
	SADDLV, 
	UADDLV, 
	SMAXV, 
	UMAXV, 
	SMINV, 
	UMINV, 
	SMAXP, 
	UMAXP, 
	SMINP, 
	UMINP, 
	// long / wide / narrowing
	SADDL, 
	SADDL2, 
	UADDL, 
	UADDL2, 
	SSUBL, 
	SSUBL2, 
	USUBL, 
	USUBL2, 
	SADDW, 
	SADDW2, 
	UADDW, 
	UADDW2, 
	SSUBW, 
	SSUBW2, 
	USUBW, 
	USUBW2, 
	RADDHN, 
	RADDHN2, 
	RSUBHN, 
	RSUBHN2, 
	ADDHN, 
	ADDHN2, 
	SUBHN, 
	SUBHN2, 
	XTN, 
	XTN2, 
	SQXTN, 
	SQXTN2, 
	UQXTN, 
	UQXTN2, 
	SQXTUN, 
	SQXTUN2, 
	// multiply long / multiply-accumulate long
	SMULL_V, 
	SMULL2_V, 
	UMULL_V, 
	UMULL2_V, 
	SMLAL, 
	SMLAL2, 
	UMLAL, 
	UMLAL2, 
	SMLSL, 
	SMLSL2, 
	UMLSL, 
	UMLSL2, 
	SQDMULL, 
	SQDMULL2, 
	SQDMLAL, 
	SQDMLAL2, 
	SQDMLSL, 
	SQDMLSL2, 
	SQDMULH, 
	SQRDMULH, 
	// dot product
	SDOT, 
	UDOT, 
	USDOT, 
	// FP vector
	FADD_V, 
	FSUB_V, 
	FMUL_V, 
	FDIV_V, 
	FNEG_V, 
	FABS_V, 
	FSQRT_V, 
	FMLA_V, 
	FMLS_V, 
	FMULX, 
	FMAX_V, 
	FMIN_V, 
	FMAXNM_V, 
	FMINNM_V, 
	FMAXP_V, 
	FMINP_V, 
	FMAXNMP, 
	FMINNMP, 
	FMAXV_V, 
	FMINV_V, 
	FMAXNMV, 
	FMINNMV, 
	FRECPE, 
	FRSQRTE, 
	FRECPS, 
	FRSQRTS, 
	FRECPX, 
	FADDP_V, 
	FRINTA_V, 
	FRINTI_V, 
	FRINTM_V, 
	FRINTN_V, 
	FRINTP_V, 
	FRINTX_V, 
	FRINTZ_V, 
	SCVTF_V, 
	UCVTF_V, 
	FCVTAS_V, 
	FCVTAU_V, 
	FCVTMS_V, 
	FCVTMU_V, 
	FCVTNS_V, 
	FCVTNU_V, 
	FCVTPS_V, 
	FCVTPU_V, 
	FCVTZS_V, 
	FCVTZU_V, 
	FCVTL, 
	FCVTL2, 
	FCVTN, 
	FCVTN2, 
	FCVTXN, 
	FCVTXN2, 
	// FP compare (vector)
	FCMEQ, 
	FCMGE, 
	FCMGT, 
	FCMLE, 
	FCMLT, 
	FACGE, 
	FACGT, 
	// Integer compare (vector)
	CMEQ, 
	CMGE, 
	CMGT, 
	CMHI, 
	CMHS, 
	CMLE, 
	CMLT, 
	CMTST, 
	// Logical (vector)
	AND_V, 
	ORR_V, 
	EOR_V, 
	BIC_V, 
	ORN_V, 
	MVN_V, 
	BIT, 
	BIF, 
	BSL, 
	// Shifts
	SHL_V, 
	SQSHL_V, 
	SQSHLU, 
	SRSHL, 
	URSHL, 
	SSHR, 
	USHR, 
	SSRA, 
	USRA, 
	SRSHR, 
	URSHR, 
	SRSRA, 
	URSRA, 
	SSHL, 
	USHL, 
	SLI, 
	SRI, 
	SSHLL, 
	SSHLL2, 
	USHLL, 
	USHLL2, 
	SXTL, 
	SXTL2, 
	UXTL, 
	UXTL2,                    // aliases of SSHLL/USHLL with imm=0
	SHRN, 
	SHRN2, 
	RSHRN, 
	RSHRN2, 
	SQSHRN, 
	SQSHRN2, 
	UQSHRN, 
	UQSHRN2, 
	SQRSHRN, 
	SQRSHRN2, 
	UQRSHRN, 
	UQRSHRN2, 
	SQSHRUN, 
	SQSHRUN2, 
	SQRSHRUN, 
	SQRSHRUN2, 
	// Misc / permute / bit
	DUP_V, 
	INS, 
	MOV_V, 
	EXT_V, 
	TBL, 
	TBX, 
	ZIP1, 
	ZIP2, 
	UZP1, 
	UZP2, 
	TRN1, 
	TRN2, 
	NOT_V, 
	RBIT_V, 
	REV16_V, 
	REV32_V, 
	REV64, 
	CLS_V, 
	CLZ_V, 
	CNT, 
	URECPE_V, 
	URSQRTE_V, 
	// Vector immediate
	MOVI, 
	MVNI, 
	FMOV_V_IMM, 
	// NEON load/store
	LD1, 
	LD2, 
	LD3, 
	LD4,                      // multiple structures
	ST1, 
	ST2, 
	ST3, 
	ST4, 
	LD1R, 
	LD2R, 
	LD3R, 
	LD4R,                     // load-and-replicate to all lanes
	LD1_LANE, 
	LD2_LANE, 
	LD3_LANE, 
	LD4_LANE,                 // load single structure to lane
	ST1_LANE, 
	ST2_LANE, 
	ST3_LANE, 
	ST4_LANE, 
	// FP/SIMD load/store using V/D/S/H/B/Q registers
	LDR_V, 
	STR_V,                    // imm/literal/pre/post/reg
	LDP_V, 
	STP_V, 
	LDUR_V, 
	STUR_V, 
	// Integer arithmetic (vectors, unpredicated)
	SVE_ADD_Z, 
	SVE_SUB_Z, 
	SVE_SQADD_Z, 
	SVE_UQADD_Z, 
	SVE_SQSUB_Z, 
	SVE_UQSUB_Z, 
	// Integer arithmetic (predicated, destructive merging)
	SVE_ADD_PRED, 
	SVE_SUB_PRED, 
	SVE_SUBR_PRED, 
	SVE_MUL_PRED, 
	SVE_SMULH_PRED, 
	SVE_UMULH_PRED, 
	SVE_SDIV_PRED, 
	SVE_UDIV_PRED, 
	SVE_SMAX_PRED, 
	SVE_UMAX_PRED, 
	SVE_SMIN_PRED, 
	SVE_UMIN_PRED, 
	SVE_SABD_PRED, 
	SVE_UABD_PRED, 
	SVE_AND_PRED, 
	SVE_ORR_PRED, 
	SVE_EOR_PRED, 
	SVE_BIC_PRED, 
	SVE_ASR_PRED, 
	SVE_LSL_PRED, 
	SVE_LSR_PRED, 
	SVE_ASRR_PRED, 
	SVE_LSLR_PRED, 
	SVE_LSRR_PRED, 
	SVE_ABS_PRED, 
	SVE_NEG_PRED, 
	SVE_CLS_PRED, 
	SVE_CLZ_PRED, 
	SVE_CNT_PRED, 
	SVE_MOV_PRED, 
	// FP arithmetic (unpredicated)
	SVE_FADD_Z, 
	SVE_FSUB_Z, 
	SVE_FMUL_Z, 
	SVE_FRECPS, 
	SVE_FRSQRTS, 
	SVE_FTSMUL, 
	// FP arithmetic (predicated, destructive merging)
	SVE_FADD_PRED, 
	SVE_FSUB_PRED, 
	SVE_FSUBR_PRED, 
	SVE_FMUL_PRED, 
	SVE_FDIV_PRED, 
	SVE_FDIVR_PRED, 
	SVE_FMAX_PRED, 
	SVE_FMIN_PRED, 
	SVE_FMAXNM_PRED, 
	SVE_FMINNM_PRED, 
	SVE_FABS_Z, 
	SVE_FNEG_Z, 
	SVE_FSQRT_Z, 
	SVE_FRECPX_Z, 
	SVE_FRINTN, 
	SVE_FRINTP, 
	SVE_FRINTM, 
	SVE_FRINTZ, 
	SVE_FRINTA, 
	SVE_FRINTX, 
	SVE_FRINTI, 
	SVE_FMLA, 
	SVE_FMLS, 
	SVE_FNMLA, 
	SVE_FNMLS, 
	// Predicate logical / move
	SVE_AND_P, 
	SVE_BIC_P, 
	SVE_ORR_P, 
	SVE_EOR_P, 
	SVE_NAND_P, 
	SVE_NOR_P, 
	SVE_ORN_P, 
	SVE_SEL_P, 
	SVE_ANDS_P, 
	SVE_BICS_P, 
	SVE_ORRS_P, 
	SVE_EORS_P, 
	SVE_NANDS_P, 
	SVE_NORS_P, 
	SVE_ORNS_P, 
	SVE_NOT_P, 
	SVE_MOV_P, 
	SVE_MOVS_P, 
	SVE_PTRUE, 
	SVE_PTRUES, 
	SVE_PFALSE, 
	SVE_PFIRST, 
	SVE_PNEXT, 
	SVE_BRKA, 
	SVE_BRKB, 
	SVE_BRKAS, 
	SVE_BRKBS, 
	SVE_BRKPA, 
	SVE_BRKPB, 
	SVE_BRKN, 
	SVE_RDFFR, 
	SVE_WRFFR, 
	SVE_SETFFR, 
	// Integer compare and set predicate
	SVE_CMPEQ, 
	SVE_CMPNE, 
	SVE_CMPGE, 
	SVE_CMPGT, 
	SVE_CMPLE, 
	SVE_CMPLT, 
	SVE_CMPHI, 
	SVE_CMPHS, 
	SVE_CMPLO, 
	SVE_CMPLS, 
	// FP compare and set predicate
	SVE_FCMEQ, 
	SVE_FCMNE, 
	SVE_FCMGE, 
	SVE_FCMGT, 
	SVE_FCMLE, 
	SVE_FCMLT, 
	SVE_FCMUO, 
	// Permute / move / replicate
	SVE_DUP_Z, 
	SVE_INSR, 
	SVE_REV_Z, 
	SVE_REV_P, 
	SVE_TBL, 
	SVE_ZIP1_Z, 
	SVE_ZIP2_Z, 
	SVE_UZP1_Z, 
	SVE_UZP2_Z, 
	SVE_TRN1_Z, 
	SVE_TRN2_Z, 
	SVE_ZIP1_P, 
	SVE_ZIP2_P, 
	SVE_UZP1_P, 
	SVE_UZP2_P, 
	SVE_TRN1_P, 
	SVE_TRN2_P, 
	SVE_CPY_Z, 
	SVE_COMPACT, 
	SVE_EXT_Z, 
	// Loads / stores (contiguous)
	SVE_LD1B, 
	SVE_LD1H, 
	SVE_LD1W, 
	SVE_LD1D, 
	SVE_LD1SB, 
	SVE_LD1SH, 
	SVE_LD1SW, 
	SVE_ST1B, 
	SVE_ST1H, 
	SVE_ST1W, 
	SVE_ST1D, 
	SVE_LDR_Z, 
	SVE_STR_Z, 
	SVE_LDR_P, 
	SVE_STR_P, 
	SVE_LDFF1B, 
	SVE_LDFF1H, 
	SVE_LDFF1W, 
	SVE_LDFF1D,               // first-faulting
	// SVE2 additions
	SVE_WHILEGE, 
	SVE_WHILEGT, 
	SVE_WHILELE, 
	SVE_WHILELT, 
	SVE_WHILEHI, 
	SVE_WHILEHS, 
	SVE_WHILELO, 
	SVE_WHILELS, 
	SVE_SQRDMLAH, 
	SVE_SQRDMLSH, 
	SVE_ADCLB, 
	SVE_ADCLT, 
	SVE_SBCLB, 
	SVE_SBCLT, 
	SVE_TBL2, 
	SVE_TBX, 
	SVE_AESE, 
	SVE_AESD, 
	SVE_AESMC, 
	SVE_AESIMC,               // SVE2 crypto
	SVE_BCAX_Z, 
	SVE_XAR_Z, 
	SVE_EOR3_Z, 
	SVE_MATCH, 
	SVE_NMATCH, 
	SVE_HISTCNT, 
	SVE_HISTSEG, 
	// -------------------------------------------------------------------------
	// SME (Scalable Matrix Extension)
	// -------------------------------------------------------------------------
	SME_SMSTART, 
	SME_SMSTOP, 
	SME_RDSVL, 
	SME_ADDHA, 
	SME_ADDVA, 
	SME_ZERO, 
	SME_FMOPA, 
	SME_FMOPS, 
	SME_BFMOPA, 
	SME_BFMOPS, 
	SME_SMOPA, 
	SME_SMOPS, 
	SME_UMOPA, 
	SME_UMOPS, 
	SME_USMOPA, 
	SME_SUMOPA, 
	SME_LDR_ZA, 
	SME_STR_ZA, 
	// -------------------------------------------------------------------------
	// SVE indexed FMLA / FMLS (lane-broadcast multiply-accumulate)
	// -------------------------------------------------------------------------
	SVE_FMLA_IDX_H, 
	SVE_FMLA_IDX_S, 
	SVE_FMLA_IDX_D, 
	SVE_FMLS_IDX_H, 
	SVE_FMLS_IDX_S, 
	SVE_FMLS_IDX_D, 
	// -------------------------------------------------------------------------
	// SVE gather/scatter (the practical 32-bit and 64-bit offset forms)
	// -------------------------------------------------------------------------
	SVE_LD1B_GATHER_S, 
	SVE_LD1B_GATHER_D, 
	SVE_LD1H_GATHER_S, 
	SVE_LD1H_GATHER_D, 
	SVE_LD1W_GATHER_S, 
	SVE_LD1W_GATHER_D, 
	SVE_LD1D_GATHER_D, 
	SVE_LD1SB_GATHER_S, 
	SVE_LD1SB_GATHER_D, 
	SVE_LD1SH_GATHER_S, 
	SVE_LD1SH_GATHER_D, 
	SVE_LD1SW_GATHER_D, 
	SVE_ST1B_SCATTER_S, 
	SVE_ST1B_SCATTER_D, 
	SVE_ST1H_SCATTER_S, 
	SVE_ST1H_SCATTER_D, 
	SVE_ST1W_SCATTER_S, 
	SVE_ST1W_SCATTER_D, 
	SVE_ST1D_SCATTER_D, 
	// -------------------------------------------------------------------------
	// SME tile slice load/store (LD1B/H/W/D/Q to ZA tile slice; ST1 reverse)
	// -------------------------------------------------------------------------
	SME_LD1B_TILE, 
	SME_LD1H_TILE, 
	SME_LD1W_TILE, 
	SME_LD1D_TILE, 
	SME_LD1Q_TILE, 
	SME_ST1B_TILE, 
	SME_ST1H_TILE, 
	SME_ST1W_TILE, 
	SME_ST1D_TILE, 
	SME_ST1Q_TILE, 
	// MOVA between Z register and tile slice (both directions)
	SME_MOVA_Z_FROM_TILE, 
	SME_MOVA_TILE_FROM_Z, 
	// -------------------------------------------------------------------------
	// NEON complex FP multiply-add (v8.3-A FCMA extension)
	// -------------------------------------------------------------------------
	FCMLA_4H, 
	FCMLA_8H, 
	FCMLA_4S, 
	FCMLA_2D, 
	FCADD_4H, 
	FCADD_8H, 
	FCADD_4S, 
	FCADD_2D, 
	// -------------------------------------------------------------------------
	// SVE prefetch, non-temporal load/store, EXT/SPLICE/INDEX
	// -------------------------------------------------------------------------
	SVE_PRFB, 
	SVE_PRFH, 
	SVE_PRFW, 
	SVE_PRFD, 
	SVE_LDNT1B, 
	SVE_LDNT1H, 
	SVE_LDNT1W, 
	SVE_LDNT1D, 
	SVE_STNT1B, 
	SVE_STNT1H, 
	SVE_STNT1W, 
	SVE_STNT1D, 
	SVE_EXT, 
	SVE_SPLICE, 
	SVE_INDEX_II, 
	SVE_INDEX_IR, 
	SVE_INDEX_RI, 
	SVE_INDEX_RR, 
	// -------------------------------------------------------------------------
	// SVE2 bitwise select family + polynomial multiply
	// -------------------------------------------------------------------------
	SVE_BSL, 
	SVE_BSL1N, 
	SVE_BSL2N, 
	SVE_NBSL, 
	SVE_PMUL_VEC, 
	SVE_PMULLB, 
	SVE_PMULLT, 
	// -------------------------------------------------------------------------
	// SVE BF16 conversions (BFCVT in SVE form)
	// -------------------------------------------------------------------------
	SVE_BFCVT, 
	SVE_BFCVTNT, 
	// -------------------------------------------------------------------------
	// PAC-authenticated loads (v8.3-A)
	// -------------------------------------------------------------------------
	LDRAA, 
	LDRAB, 
	LDRAA_PRE, 
	LDRAB_PRE, 
	// -------------------------------------------------------------------------
	// Transactional Memory Extension (TME, v9.0-A)
	// -------------------------------------------------------------------------
	TSTART, 
	TCOMMIT, 
	TCANCEL, 
	TTEST, 
	// -------------------------------------------------------------------------
	// Wait with timeout (v8.7-A)
	// -------------------------------------------------------------------------
	WFET, 
	WFIT, 
	// -------------------------------------------------------------------------
	// Branch consistency hint (v8.8-A BC.cond)
	// -------------------------------------------------------------------------
	BC_COND, 
	// -------------------------------------------------------------------------
	// Sign/zero extend aliases (canonical names for SBFM/UBFM specific cases)
	// -------------------------------------------------------------------------
	UXTB, 
	UXTH, 
	UXTW,                     // unsigned extends (UBFM aliases)
	SXTB, 
	SXTH, 
	SXTW,                     // signed extends (SBFM aliases)
	// -------------------------------------------------------------------------
	// Carry arithmetic (add/sub with carry)
	// -------------------------------------------------------------------------
	ADC, 
	ADCS, 
	SBC, 
	SBCS, 
	NGC, 
	NGCS,                     // NGC Rd, Rm = SBC Rd, ZR, Rm; NGCS similar
	// -------------------------------------------------------------------------
	// RCpc / LDAPUR / STLUR (v8.4-A unscaled release-consistency loads/stores)
	// -------------------------------------------------------------------------
	LDAPUR, 
	STLUR,                    // 32/64-bit word
	LDAPURB, 
	STLURB, 
	LDAPURH, 
	STLURH,                   // byte / half
	LDAPURSB, 
	LDAPURSH, 
	LDAPURSW,                 // signed extending
	// -------------------------------------------------------------------------
	// SVE BF16 predicated arithmetic (3-same)
	// -------------------------------------------------------------------------
	SVE_BFADD, 
	SVE_BFSUB, 
	SVE_BFMUL, 
	SVE_BFMLA, 
	SVE_BFMLS, 
	// -------------------------------------------------------------------------
	// Speculation / profiling barriers + speculation hints
	// -------------------------------------------------------------------------
	SB,                       // Speculation Barrier (v8.0)
	CSDB,                     // Consumption of Speculative Data Barrier
	DGH,                      // Data Gathering Hint (v8.5-A)
	PSB_CSYNC,                // Profile Synchronization Barrier
	TSB_CSYNC,                // Trace Synchronization Barrier
	BTI_J, 
	BTI_C, 
	BTI_JC,                   // explicit BTI variants
	// -------------------------------------------------------------------------
	// More NEON aliases
	// -------------------------------------------------------------------------
	MOV_V_ALIAS,              // MOV Vd.<T>, Vn.<T> = ORR Vd, Vn, Vn  (vector copy)
	NOT_V_ALIAS,              // NOT Vd.<T>, Vn.<T> = MVN with Rm=Rn
	// -------------------------------------------------------------------------
	// Shift-by-immediate aliases (UBFM/SBFM specific cases)
	// -------------------------------------------------------------------------
	LSL_IMM,                  // LSL Rd, Rn, #imm = UBFM Rd, Rn, #(-imm % regsize), #(regsize-1-imm)
	LSR_IMM,                  // LSR Rd, Rn, #imm = UBFM Rd, Rn, #imm, #(regsize-1)
	ASR_IMM,                  // ASR Rd, Rn, #imm = SBFM Rd, Rn, #imm, #(regsize-1)
	ROR_IMM,                  // ROR Rd, Rn, #imm = EXTR Rd, Rn, Rn, #imm
	// -------------------------------------------------------------------------
	// SVE2.1 / SME2 -- BF16 unpredicated + clamp/min/max + multi-vector
	// -------------------------------------------------------------------------
	SVE_BFADD_UNPRED, 
	SVE_BFSUB_UNPRED, 
	SVE_BFMUL_UNPRED, 
	SVE_BFCLAMP,              // BFCLAMP Zd.H, Zn.H, Zm.H
	SVE_BFMAXNM, 
	SVE_BFMINNM,              // BF16 min/max-num predicated
	// SME2 multi-vector: contiguous LD/ST and select-table lookup
	SME2_LUTI2_B, 
	SME2_LUTI4_B,             // LUTI2/4 table lookup (byte)
	SME2_LD1B_X2, 
	SME2_LD1H_X2,             // 2-vector contiguous loads
	SME2_LD1W_X2, 
	SME2_LD1D_X2, 
	SME2_LD1B_X4, 
	SME2_LD1H_X4,             // 4-vector contiguous loads
	SME2_LD1W_X4, 
	SME2_LD1D_X4, 
	SME2_ST1B_X2, 
	SME2_ST1H_X2, 
	SME2_ST1W_X2, 
	SME2_ST1D_X2, 
	SME2_ST1B_X4, 
	SME2_ST1H_X4, 
	SME2_ST1W_X4, 
	SME2_ST1D_X4, 
	// SME2 ZIP / UZP multi-way (3-vector and 4-vector forms)
	SME2_ZIP_3, 
	SME2_ZIP_4, 
	SME2_UZP_3, 
	SME2_UZP_4, 
	// -------------------------------------------------------------------------
	// RME (Realm Management Extension, ARMv9-A)
	// -------------------------------------------------------------------------
	TLBI_RPALOS, 
	TLBI_RPAOS,               // Realm physical address space
	AT_S1E1A,                 // stage-1 translate with implicit authority
	DC_CIPAPA, 
	DC_CIGDPAPA,              // physical-address cache mgmt
	TLBI_PAALL, 
	TLBI_PAALLOS, 
	// -------------------------------------------------------------------------
	// Apple AMX (undocumented vendor coprocessor; A13+/M1+)
	// -------------------------------------------------------------------------
	// 
	// All AMX instructions share the encoding 0x00201000 | (op << 5) | xn,
	// where xn is a 5-bit operand (typically a GPR holding pointer +
	// control word). The reserved bit pattern lives in the system-
	// instruction space (op0 = 0b0000) so it doesn't collide with any
	// standard A64 mnemonic. Reverse-engineered ops:
	// 
	//   00 LDX     load X register set (16 input rows)
	//   01 LDY     load Y register set (16 input rows)
	//   02 STX     store X
	//   03 STY     store Y
	//   04 LDZ     load Z accumulator (64 rows)
	//   05 STZ     store Z
	//   06 LDZI    load Z interleaved
	//   07 STZI    store Z interleaved
	//   08 EXTRX   extract from X
	//   09 EXTRY   extract from Y
	//   10 FMA64   FP64 fused multiply-add
	//   11 FMS64   FP64 fused multiply-subtract
	//   12 FMA32   FP32 fused multiply-add
	//   13 FMS32   FP32 fused multiply-subtract
	//   14 MAC16   int16 multiply-accumulate
	//   15 FMA16   FP16 fused multiply-add
	//   16 FMS16   FP16 fused multiply-subtract
	//   17 SET     enable AMX (operand=0)
	//   18 CLR     disable AMX
	//   19 VECINT  integer vector ops
	//   20 VECFP   FP vector ops
	//   21 MATINT  integer matrix ops
	//   22 MATFP   FP matrix ops
	//   23 GENLUT  general lookup table (A14+)
	AMX_LDX, 
	AMX_LDY, 
	AMX_STX, 
	AMX_STY, 
	AMX_LDZ, 
	AMX_STZ, 
	AMX_LDZI, 
	AMX_STZI, 
	AMX_EXTRX, 
	AMX_EXTRY, 
	AMX_FMA64, 
	AMX_FMS64, 
	AMX_FMA32, 
	AMX_FMS32, 
	AMX_MAC16, 
	AMX_FMA16, 
	AMX_FMS16, 
	AMX_SET, 
	AMX_CLR, 
	AMX_VECINT, 
	AMX_VECFP, 
	AMX_MATINT, 
	AMX_MATFP, 
	AMX_GENLUT, 
	// -------------------------------------------------------------------------
	// MOPS (Memory Operations, v8.8-A)
	// -------------------------------------------------------------------------
	// 
	// Each operation is split into a 3-instruction Prologue/Main/Epilogue
	// sequence that all share the same {Xd, Xs, Xn} destructive operands.
	//   CPY*  : general memcpy (may overlap)
	//   CPYF* : forward-only memcpy
	//   SET*  : memset (Xs holds the byte value)
	CPYP, 
	CPYM, 
	CPYE, 
	CPYFP, 
	CPYFM, 
	CPYFE, 
	SETP, 
	SETM, 
	SETE, 
	// -------------------------------------------------------------------------
	// Cache management (SYS-encoded under op0=3 or op0=0)
	// -------------------------------------------------------------------------
	// 
	// Data cache:
	DC_IVAC, 
	DC_ISW, 
	DC_CSW, 
	DC_CISW, 
	DC_ZVA, 
	DC_CVAC, 
	DC_CVAU, 
	DC_CIVAC, 
	// Instruction cache:
	IC_IALLUIS, 
	IC_IALLU, 
	IC_IVAU, 
	// Address translate (PE current EL):
	AT_S1E1R, 
	AT_S1E1W, 
	AT_S1E0R, 
	AT_S1E0W, 
	AT_S1E2R, 
	AT_S1E2W, 
	AT_S1E3R, 
	AT_S1E3W, 
	AT_S12E1R, 
	AT_S12E1W, 
	AT_S12E0R, 
	AT_S12E0W, 
	// TLB invalidate (the practical subset):
	TLBI_VMALLE1, 
	TLBI_VMALLE1IS, 
	TLBI_VAE1, 
	TLBI_VAE1IS, 
	TLBI_ASIDE1, 
	TLBI_ASIDE1IS, 
	TLBI_VAAE1, 
	TLBI_VAAE1IS, 
	TLBI_VALE1, 
	TLBI_VALE1IS, 
	TLBI_VAALE1, 
	TLBI_VAALE1IS, 
	TLBI_ALLE1, 
	TLBI_ALLE1IS, 
	TLBI_ALLE2, 
	TLBI_ALLE2IS, 
	TLBI_ALLE3, 
	TLBI_ALLE3IS, 
	// -------------------------------------------------------------------------
	// Prefetch
	// -------------------------------------------------------------------------
	PRFM, 
	PRFUM, 
	PRFM_LIT, 
	// -------------------------------------------------------------------------
	// Aliases (printed canonically; encode the underlying operation with
	// Rd=ZR or Rn=ZR fixed).
	// -------------------------------------------------------------------------
	MOV_REG,                  // MOV Rd, Rm  =  ORR Rd, ZR, Rm  (shifted-register form)
	MOV_BITMASK,              // MOV Rd, #imm =  ORR Rd, ZR, #bitmask_imm
	MVN,                      // MVN Rd, Rm  =  ORN Rd, ZR, Rm
	NEG_SR,                   // NEG Rd, Rm{,shift}  =  SUB  Rd, ZR, Rm{,shift}
	NEGS,                     // NEGS Rd, Rm{,shift} =  SUBS Rd, ZR, Rm{,shift}
	CMP_SR,                   // CMP Rn, Rm{,shift}  =  SUBS ZR, Rn, Rm{,shift}
	CMP_ER,                   // CMP Rn, Rm, ext     =  SUBS ZR, Rn, Rm, ext
	CMP_IMM,                  // CMP Rn, #imm        =  SUBS ZR, Rn, #imm
	CMN_SR,                   // CMN Rn, Rm{,shift}  =  ADDS ZR, Rn, Rm{,shift}
	CMN_ER,                   // CMN Rn, Rm, ext     =  ADDS ZR, Rn, Rm, ext
	CMN_IMM,                  // CMN Rn, #imm        =  ADDS ZR, Rn, #imm
	TST_SR,                   // TST Rn, Rm{,shift}  =  ANDS ZR, Rn, Rm{,shift}
}

Related Procedures With Parameters

Operand ¶
Source

Operand :: struct #packed {
	using _: struct #packed #raw_union {
		reg:       Register,
		// 2
		mem:       Memory,
		// 12
		immediate: i64,
		// 8
		relative:  i64,
		// 8
		shifted:   Shifted_Reg,
		// 8
		extended:  Extended_Reg,
		// 8
		cond:      u8,
	},
	// 12 total because of alignment
	kind: Operand_Kind,
	// 1
	size: u8,
}

16-byte tagged operand. The union holds whichever payload matches kind.

Related Procedures With Parameters

pack_operand_inline

Related Procedures With Returns

Operand_Encoding ¶
Source

Operand_Encoding :: enum u8 {
	NONE, 
	IMPL,                // implicit; no bits emitted
	// ---- Register slots (5-bit hw fields) ----
	RD,                  // bits 0-4
	RT,                  // bits 0-4 (alias of RD used in loads)
	RN,                  // bits 5-9
	RT2,                 // bits 10-14
	RA,                  // bits 10-14 (alias of RT2 used in MADD/MSUB)
	RM,                  // bits 16-20
	// ---- Immediates ----
	IMM12,               // bits 10-21
	IMM16,               // bits 5-20
	IMM6,                // bits 10-15  (shift amount; SHAMT)
	IMM9,                // bits 12-20  (signed 9-bit; LDUR/pre/post)
	IMM_HW,              // bits 21-22  (MOVZ/MOVN/MOVK hw field; value is shift/16)
	IMM_SH12,            // bit  22     (ADD/SUB imm: LSL #12 flag)
	SHIFT_TYPE,          // bits 22-23  (LSL/LSR/ASR/ROR for shifted-register)
	EXT_OPT,             // bits 13-15  (extend type for extended-register)
	EXT_IMM3,            // bits 10-12  (extend amount)
	COND_HI,             // bits 12-15  (CSEL/CSINC/CSINV/CSNEG, FCSEL, CCMP)
	COND_LO,             // bits  0-3   (B.cond)
	NZCV_FIELD,          // bits  0-3   (CCMP/CCMN immediate NZCV)
	SYS_FIELD,           // bits 5-19   (MRS/MSR: op0/op1/CRn/CRm/op2)
	HINT_FIELD,          // bits 5-11   (HINT type)
	BARRIER_FIELD,       // bits 8-11   (DMB/DSB/ISB barrier type)
	// ---- Memory operand composites ----
	OFFSET_BASE_U12,     // [Xn, #imm * size] with imm12 scaled by data size
	OFFSET_BASE_S9,      // [Xn, #imm] signed-9 unscaled (LDUR/STUR)
	OFFSET_BASE_PRE,     // [Xn, #imm]!   signed-9 pre-index
	OFFSET_BASE_POST,    // [Xn], #imm    signed-9 post-index
	OFFSET_BASE_A,       // [Xn]          no displacement (exclusives, acquire/release, LSE)
	OFFSET_REG,          // [Xn, Rm{, LSL #s}] register offset
	OFFSET_EXT,          // [Xn, Wm, SXTW|UXTW|SXTX #s]
	// ---- PC-relative ----
	BRANCH_26,           // B / BL  (operand-driven 26-bit field, scaled ×4)
	BRANCH_19,           // B.cond / CBZ / LDR literal
	BRANCH_14,           // TBZ / TBNZ
	BRANCH_PG21,         // ADR / ADRP: imm21 split as immlo[29-30] + immhi[5-23]
	// ---- TBZ/TBNZ bit position (split field b5 + b40) ----
	TBZ_BIT,             // b5 at bit 31, b40 at bits 19-23
	// ---- NEON / SIMD specific ---------------------------------------------
	VD, 
	VN, 
	VM,                  // 5-bit V regs at bits 0-4 / 5-9 / 16-20 (alias of RD/RN/RM)
	VA,                  // R4-type 3rd source (FMLA-ish) at bits 10-14
	NEON_IMM8_FMOV,      // 8-bit imm split (abc at 18-16, defgh at 9-5)
	NEON_INDEX_H,        // 2-bit H lane index
	NEON_INDEX_S,        // S lane index
	NEON_INDEX_D,        // D lane index
	// ---- NEON shift-by-immediate (immh:immb at bits 22:16) ----
	// The element-size marker bit is fixed in the entry's `bits`; the operand
	// drives only the low bits. Left: low = shift. Right: low = esize - shift.
	NEON_SHL_IMM, 
	NEON_SHR_IMM, 
	// ---- NEON copy/permute index fields ----
	// The element-size marker bit lives in the entry `bits`; the lane index
	// operand drives the bits above it (DUP/INS imm5, INS imm4) or the plain
	// imm4 (EXT). The decoder recovers the element size from imm5's marker.
	VN_VM_DUP,           // one V reg packed into BOTH Vn (9:5) and Vm (20:16) (MOV = ORR alias)
	NEON_IDX5,           // element lane index in imm5 (20:16); index << (markerbit+1)
	NEON_IDX4,           // INS source lane index in imm4 (14:11); index << markerbit
	NEON_EXT_IDX,        // EXT byte index in imm4 (14:11)
	// ---- MSR (immediate to PSTATE): pstate field selector op1:op2 ----
	// User passes the combined 6-bit selector (op1<<3 | op2); op1 lands at
	// bits 18:16, op2 at bits 7:5. The #imm goes to CRm (bits 11:8) via
	// BARRIER_FIELD, which it shares with the DMB/DSB barrier encoding.
	IMM5_HI,             // generic 5-bit immediate at bits 20:16 (CCMP/CCMN immediate)
	MSR_PSTATE,          // PSTATE field selector: op1 at 18:16, op2 at 7:5
	FMOV_SCALAR_IMM,     // scalar FMOV 8-bit float immediate at bits 20:13
	// ---- SVE alias duplicated predicate/Z fields + EXT byte index ----
	// MOV/NOT/MOVS predicate aliases are EOR/ORR/AND with a duplicated field;
	// MOV (predicated) is SEL with Zm = Zd. The source register is packed into
	// every slot it occupies so the alias round-trips to the canonical bytes.
	PG4_PM_DUP,          // Pg at 10:13 AND Pm at 16:19 (NOT = EOR Pd,Pg/z,Pn,Pg)
	PN_PM_DUP,           // Pn at 5:8 AND Pm at 16:19 (MOVS/MOV-pred: Pm = Pn)
	PN_PG_PM_DUP,        // Pn at 5:8, Pg at 10:13, Pm at 16:19 (MOV Pd,Pn)
	ZD_ZM_DUP,           // Zd at 0:4 AND Zm at 16:20 (MOV Zd,Pg/m,Zn = SEL ...,Zd)
	SVE_EXT_IMM,         // SVE EXT byte index: imm8h at 20:16, imm8l at 12:10
	ZA_TILE_LOW,         // SME ZA accumulator tile number at bits 2:0 (ADDHA/ADDVA)
	// ---- NEON single-structure lane index (LD1..4_LANE / ST1..4_LANE) ----
	// The lane index is split across Q (bit 30), S (bit 12) and size (bits
	// 11:10) in an element-size-dependent way; the structure-size/count opcode
	// bits stay fixed in the entry `bits`.
	NEON_LANE_B,         // .B[i]: Q<<3 | S<<2 | size  (i in 0..15)
	NEON_LANE_H,         // .H[i]: Q<<2 | S<<1 | bit11 (i in 0..7)
	NEON_LANE_S,         // .S[i]: Q<<1 | S            (i in 0..3)
	NEON_LANE_D,         // .D[i]: Q                   (i in 0..1)
	// ---- SVE2 XAR rotate amount (tszh:tszl:imm3 split) ----
	// V = 2*esize - amount placed as tszh(23:22):tszl(20:19):imm3(18:16);
	// esize comes from the form's Z register (highest set bit of tszh:tszl).
	SVE_XAR_SHIFT, 
	// ---- LSE atomics ------------------------------------------------------
	ATOMIC_RS,           // Rs (source / compare) at bits 16-20
	ATOMIC_RT,           // Rt (target) at bits 0-4
	ATOMIC_RN,           // Rn (address) at bits 5-9
	// ---- Bitmask logical immediate (N:imms:immr at bits 22 / 15:10 / 21:16) ----
	BITMASK_FIELD, 
	// ---- Predicate (SVE) --------------------------------------------------
	PD, 
	PN, 
	PM,                  // P-reg positions (bits 0-3 / 5-8 / 16-19 in many SVE forms)
	PG,                  // governing predicate (3-bit at bits 10-12)
	PG4,                 // governing predicate (4-bit at bits 10-13, e.g. predicate logical)
	PM3,                 // 3-bit Pm at bits 15:13 (SME outer products / a few SVE forms)
	// ---- SVE immediates ---------------------------------------------------
	SVE_IMM8,            // signed 8-bit at bits 12-5 (DUP/CPY/ADD imm)
	SVE_IMM5,            // 5-bit at bits 20-16 (INDEX imm, etc.)
	SVE_SHIFT_TSZ_IMM,   // tsz:imm3 at bits 22:16, encodes element-size + shift amount
	SVE_PATTERN,         // 5-bit pattern (POW2/VL1.../ALL) at bits 9-5 (PTRUE)
	// ---- SVE memory operands ---------------------------------------------
	SVE_OFFSET_BASE_SS,  // [Xn, Xm, LSL #s] -- scalar+scalar contiguous
	SVE_OFFSET_BASE_SI,  // [Xn, #imm, MUL VL] -- scalar+imm (signed 4-bit times VL)
	SVE_OFFSET_BASE_VEC, // [Xn, Zm.S/D, UXTW|SXTW|LSL #s] -- scalar base + vec offset
	SVE_OFFSET_VEC_BASE, // [Zn.S/D, #imm5] -- vector base + scalar imm
	// ---- SVE indexed lane field (FMLA Zda.T, Zn.T, Zm.T[i]) -----------
	SVE_FMLA_IDX_H,      // .H index: i3 split as (bit 22, bits 20:19), Zm@18:16
	SVE_FMLA_IDX_S,      // .S index: i2 at bits 20:19, Zm@18:16
	SVE_FMLA_IDX_D,      // .D index: i1 at bit 20, Zm@19:16
	// ---- SME ZA tile + slice fields --------------------------------------
	ZA_TILE_NUM_B,       // single-tile (ZA0.B): no field (implicit)
	ZA_TILE_NUM_H,       // tile number bit at bit 22 (ZA0.H..ZA1.H)
	ZA_TILE_NUM_S,       // tile number bits 23:22 (ZA0.S..ZA3.S)
	ZA_TILE_NUM_D,       // tile number bits 23:21 (ZA0.D..ZA7.D)
	SME_PATTERN_FIELD,   // 5-bit SME pattern (for ZERO list / SMSTART/SMSTOP)
	// ---- SME tile-slice descriptor field (LD1B/LD1H/LD1W/LD1D/LD1Q) ------
	// 
	// User passes a packed immediate carrying the full slice descriptor:
	//   bits  3:0  = imm offset within tile (0..15 for .B, 0..7 for .H, ...)
	//   bit  4     = direction (0=H, 1=V)
	//   bits  6:5  = Ws index (Ws is W12+this, range 0..3)
	//   bits 10:7  = tile number (only the low bits relevant per element size)
	// 
	// The encoder unpacks and places the bits per element-size layout.
	SME_SLICE_B,         // byte tile (single tile, imm 0..15)
	SME_SLICE_H,         // half tile (2 tiles, imm 0..7)
	SME_SLICE_W,         // word tile (4 tiles, imm 0..3)
	SME_SLICE_D,         // double tile (8 tiles, imm 0..1)
	SME_SLICE_Q,         // quad tile (16 tiles, imm 0)
	// ---- Misc new operand-encoding values (batch 3) ----
	ENC_FCMLA_ROT,       // 2-bit rotation at bits 13:12 (FCMLA)
	ENC_FCADD_ROT,       // 1-bit rotation at bit 12 (FCADD)
	ENC_SVE_PRFOP,       // 4-bit prefetch op at bits 3:0 (SVE PRFB/H/W/D)
	ENC_LDRAA_IMM10,     // signed 10-bit imm10 at bits 21:12, scaled by 8 (LDRAA/B)
	// ---- Batch 5 composite-packed encodings ----
	// 
	// LSL_IMM Wd, Wn, #imm = UBFM Wd, Wn, #(-imm % 32), #(31-imm).
	// The single user-passed shift amount drives BOTH immr (21:16) and
	// imms (15:10). Width 32 (W) vs 64 (X) selects the modulus and N bit.
	ENC_LSL_IMM_W,       // W-form: immr = (-imm) & 31, imms = 31 - imm
	ENC_LSL_IMM_X,       // X-form: immr = (-imm) & 63, imms = 63 - imm
	// ROR_IMM Rd, Rn, #imm = EXTR Rd, Rn, Rn, #imm. The Rn register is
	// packed at BOTH the Rn slot (9:5) AND the Rm slot (20:16). The shift
	// amount goes to imms (15:10).
	ENC_DUAL_RN_RM,      // packs op.reg at both bits 9:5 AND bits 20:16
	ENC_ROR_SHIFT,       // 6-bit shift amount at bits 15:10 (imms slot)
	// SME2 multi-vector lists at the Vd/Vn/Vm slots. The user passes the
	// first register of the list; the matcher validates alignment.
	// Encoding just packs the first register's hardware number into the
	// standard slot (the implicit pair/quad is encoded by mnemonic).
	ENC_Z_PAIR_VD, 
	ENC_Z_PAIR_VN, 
	ENC_Z_PAIR_VM, 
	ENC_Z_QUAD_VD, 
	ENC_Z_QUAD_VN, 
	ENC_Z_QUAD_VM, 
}

Where each operand's bits land in the 32-bit word.

Related Procedures With Parameters

pack_operand_inline

Operand_Kind ¶
Source

Operand_Kind :: enum u8 {
	NONE, 
	REGISTER, 
	IMMEDIATE, 
	MEMORY, 
	RELATIVE, 
	SHIFTED_REG,  // X reg + shift type + shift amount
	EXTENDED_REG, // X/W reg + extend + amount
	COND,         // 4-bit condition code (EQ/NE/.../AL/NV)
}

Operand_Type ¶
Source

Operand_Type :: enum u8 {
	NONE, 
	// ---- Integer registers ----
	W_REG,       // W0..W30 or WZR (hw=31 means ZR)
	X_REG,       // X0..X30 or XZR
	WSP_REG,     // W0..W30 or WSP (hw=31 means stack pointer)
	XSP_REG,     // X0..X30 or SP
	W_SHIFTED,   // W reg + shift type + 5-bit amount
	X_SHIFTED,   // X reg + shift type + 6-bit amount
	W_EXTENDED,  // W reg + extend + 3-bit amount
	X_EXTENDED,  // X reg + extend + 3-bit amount
	// ---- SIMD/FP scalar register views ----
	B_REG, 
	H_REG, 
	S_REG, 
	D_REG, 
	Q_REG, 
	// ---- Vector register (NEON full V) ----
	V_REG, 
	// NEON vector with explicit arrangement
	V_8B, 
	V_16B, 
	V_4H, 
	V_8H, 
	V_2S, 
	V_4S, 
	V_1D, 
	V_2D, 
	V_4H_FP16, 
	V_8H_FP16,   // FP16 vector forms
	// Element-indexed vector (V0.B[i] / .H[i] / .S[i] / .D[i])
	V_ELEM_B, 
	V_ELEM_H, 
	V_ELEM_S, 
	V_ELEM_D, 
	// ---- SVE register operands ----
	Z_REG_B, 
	Z_REG_H, 
	Z_REG_S, 
	Z_REG_D, 
	P_REG,       // P0..P15 (predicate)
	P_REG_MERGE, 
	P_REG_ZERO,  // predicated execution modes
	P_REG_GOV,   // governing predicate slot (3-bit P0..P7)
	// ---- SME register operands ----
	ZA_TILE_B, 
	ZA_TILE_H, 
	ZA_TILE_S, 
	ZA_TILE_D, 
	ZA_TILE_Q,   // ZA tile by element size
	SME_PATTERN, // SME pattern/tile-list mask selector
	SVE_PATTERN, // SVE predicate pattern (POW2, VL1.., ALL)
	// ---- SME tile-slice operand (packed immediate descriptor) ----
	//   bits  3:0 = imm offset within tile (range varies by element size)
	//   bit  4    = direction (0=H, 1=V)
	//   bits 6:5  = Ws index (Ws is W12 + this, range 0..3)
	//   bits 10:7 = tile number (relevant bits per element size)
	SME_SLICE_B, 
	SME_SLICE_H, 
	SME_SLICE_W, 
	SME_SLICE_D, 
	SME_SLICE_Q, 
	// ---- Misc new operand-type aliases ----
	FCMLA_ROT,   // 2-bit complex rotation index (0/90/180/270 deg) at bits 13:12
	FCADD_ROT,   // 1-bit complex rotation index (0=90, 1=270 deg) at bit 12
	SVE_PRFOP,   // 4-bit SVE prefetch op selector at bits 3:0
	LDRAA_IMM10, // signed 10-bit imm10 scaled by 8 (LDRAA / LDRAB)
	LSL_SHIFT_W, // shift amount 0..31 for LSL Wd, Wn, #imm (32-bit)
	LSL_SHIFT_X, // shift amount 0..63 for LSL Xd, Xn, #imm (64-bit)
	ROR_SHIFT,   // shift amount for ROR (alias of EXTR), goes to imms
	Z_PAIR,      // SME2 vector pair {Zn, Zn+1} — register number must be even
	Z_QUAD,      // SME2 vector quad {Zn, Zn+1, Zn+2, Zn+3} — number multiple of 4
	// ---- Immediates ----
	IMM_12,      // 12-bit unsigned (ADD/SUB imm; carries optional LSL #12 in size byte)
	IMM_16,      // 16-bit unsigned (MOVZ/MOVN/MOVK)
	IMM_8,       // 8-bit unsigned (NEON MOVI, BTI/CRC32 immediate-like)
	IMM_6,       // 6-bit unsigned (data-proc shift amount)
	IMM_5,       // 5-bit unsigned (TBZ/TBNZ bit position; FP rounding lane)
	IMM_3,       // 3-bit (shift amount for EXTEND, NZCV, system register field)
	IMM_4,       // 4-bit (HINT, DMB/DSB barrier types, NZCV flags)
	IMM_2,       // 2-bit (FP rounding mode / NEON cmode bits 14:13 etc.)
	NZCV_IMM,    // 4-bit NZCV for CCMP/CCMN immediate forms
	SYS_REG,     // 16-bit system register encoding (MSR/MRS)
	HW_SHIFT,    // 2-bit LSL hw (0/16/32/48) for MOV-immediate
	BITMASK_IMM, // Logical immediate (bitmask-encoded N:imms:immr)
	LSE_SIZE,    // 2-bit size selector for LSE atomics (00=B 01=H 10=W 11=X)
	// ---- PC-relative ----
	REL_26,      // B / BL (signed 26-bit << 2)
	REL_19,      // B.cond / CBZ / CBNZ / LDR literal (signed 19-bit << 2)
	REL_14,      // TBZ / TBNZ (signed 14-bit << 2)
	REL_PG21,    // ADR / ADRP (signed 21-bit; ADRP scales by 4096)
	// ---- Memory ----
	MEM,         // memory operand with addressing mode
	// ---- Condition code ----
	COND, 
	// ---- NEON shift-by-immediate amount (encoded into immh:immb together
	//      with the element size: left = esize+shift, right = 2*esize-shift) ----
	VEC_SHIFT, 
	// ---- NEON element lane index (DUP/INS/EXT). The element-size marker
	//      lives in the entry `bits`; the operand drives only the index bits. ----
	VEC_INDEX, 
}

What the user passes in. Most operand types describe a register class or a specific immediate width that the matcher cares about.

Print_Options ¶
Source

Print_Options :: rexcode_isa.Print_Options

Related Procedures With Parameters

Related Constants

DEFAULT_PRINT_OPTIONS

Print_Result ¶
Source

Print_Result :: rexcode_isa.Print_Result

Register ¶
Source

Register :: distinct u16

Related Procedures With Parameters

Related Procedures With Returns

Related Constants

FP_REG
LR
NONE
SP
V0
V1
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V2
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V3
V30
V31
V4
V5
V6
V7
V8
V9
W0
W1
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W2
W20
W21
W22
W23
W24
W25
W26
W27
W28
W29
W3
W30
W4
W5
W6
W7
W8
W9
WSP
WZR
X0
X1
X10
X11
X12
X13
X14
X15
X16
X17
X18
X19
X2
X20
X21
X22
X23
X24
X25
X26
X27
X28
X29
X3
X30
X4
X5
X6
X7
X8
X9
XZR

Relocation ¶
Source

Relocation :: struct #packed {
	offset:   u32,
	label_id: u32,
	addend:   i32,
	type:     Relocation_Type,
	size:     u8,
	inst_idx: u16,
}

Relocation_Type ¶
Source

Relocation_Type :: enum u8 {
	NONE          = 0, 
	// PC-relative branches
	B26,               // 26-bit signed offset (×4) -- B / BL
	B_COND19,          // 19-bit signed offset (×4) -- B.cond, CBZ/CBNZ
	TBZ14,             // 14-bit signed offset (×4) -- TBZ / TBNZ
	// PC-relative addressing
	ADR_PCREL21,       // ±1MB signed offset -- ADR
	ADRP_PCREL21,      // ±4GB signed offset on 4K page boundary -- ADRP
	PCREL_LO12_I,      // low 12 of (sym - page_of(ADRP)) -- ADD/LDR/STR after ADRP
	PCREL_LO12_S,      // S-form variant if needed for store-pair-style ops
	// Load-literal (PC-relative 19-bit signed, scaled by 4)
	LDR_LITERAL19, 
	// Absolute (filled by linker)
	ABS64, 
	ABS32, 
	ABS16, 
}

Shift_Type ¶
Source

Shift_Type :: enum u8 {
	LSL = 0, 
	LSR = 1, 
	ASR = 2, 
	ROR = 3, 
}

Related Procedures With Parameters

Shifted_Reg ¶
Source

Shifted_Reg :: struct #packed {
	reg:    Register,
	// 2
	type:   Shift_Type,
	// 1
	amount: u8,
}

Token ¶
Source

Token :: rexcode_isa.Token

Token_Kind ¶
Source

Token_Kind :: rexcode_isa.Token_Kind

Constants

ACTLR_EL1 ¶
Source

ACTLR_EL1 :: i64(0x4081)

3 0 1 0 1

AFSR0_EL1 ¶
Source

AFSR0_EL1 :: i64(0x4288)

3 0 5 1 0

AFSR1_EL1 ¶
Source

AFSR1_EL1 :: i64(0x4289)

3 0 5 1 1

AMAIR_EL1 ¶
Source

AMAIR_EL1 :: i64(0x4518)

3 0 10 3 0

APDAKEYHI_EL1 ¶
Source

APDAKEYHI_EL1 :: i64(0x4321)

3 0 2 2 1

APDAKEYLO_EL1 ¶
Source

APDAKEYLO_EL1 :: i64(0x4320)

3 0 2 2 0

APDBKEYHI_EL1 ¶
Source

APDBKEYHI_EL1 :: i64(0x4323)

3 0 2 2 3

APDBKEYLO_EL1 ¶
Source

APDBKEYLO_EL1 :: i64(0x4322)

3 0 2 2 2

APGAKEYHI_EL1 ¶
Source

APGAKEYHI_EL1 :: i64(0x4329)

3 0 2 3 1

APGAKEYLO_EL1 ¶
Source

APGAKEYLO_EL1 :: i64(0x4328)

3 0 2 3 0

APIAKEYHI_EL1 ¶
Source

APIAKEYHI_EL1 :: i64(0x4319)

3 0 2 1 1

APIAKEYLO_EL1 ¶
Source

APIAKEYLO_EL1 :: i64(0x4318)

3 0 2 1 0 (FEAT_PAuth)

APIBKEYHI_EL1 ¶
Source

APIBKEYHI_EL1 :: i64(0x431B)

3 0 2 1 3

APIBKEYLO_EL1 ¶
Source

APIBKEYLO_EL1 :: i64(0x431A)

3 0 2 1 2

CCSIDR_EL1 ¶
Source

CCSIDR_EL1 :: i64(0x4800)

----------------------------------------------------------------------------- Cache hierarchy + selection -----------------------------------------------------------------------------

CLIDR_EL1 ¶
Source

CLIDR_EL1 :: i64(0x4801)

3 1 0 0 1

CNTFRQ_EL0 ¶
Source

CNTFRQ_EL0 :: i64(0x5F00)

Counters / system identity

CNTHCTL_EL2 ¶
Source

CNTHCTL_EL2 :: i64(0x6708)

3 4 14 1 0

CNTHP_CTL_EL2 ¶
Source

CNTHP_CTL_EL2 :: i64(0x6711)

3 4 14 2 1

CNTHP_CVAL_EL2 ¶
Source

CNTHP_CVAL_EL2 :: i64(0x6712)

3 4 14 2 2

CNTHP_TVAL_EL2 ¶
Source

CNTHP_TVAL_EL2 :: i64(0x6710)

3 4 14 2 0

CNTHV_CTL_EL2 ¶
Source

CNTHV_CTL_EL2 :: i64(0x6719)

3 4 14 3 1

CNTHV_CVAL_EL2 ¶
Source

CNTHV_CVAL_EL2 :: i64(0x671A)

3 4 14 3 2

CNTHV_TVAL_EL2 ¶
Source

CNTHV_TVAL_EL2 :: i64(0x6718)

3 4 14 3 0

CNTKCTL_EL1 ¶
Source

CNTKCTL_EL1 :: i64(0x4708)

---- Counter / Timer (full set) ----

CNTPCT_EL0 ¶
Source

CNTPCT_EL0 :: i64(0x5F01)

3 3 14 0 1

CNTPS_CTL_EL1 ¶
Source

CNTPS_CTL_EL1 :: i64(0x7F11)

3 7 14 2 1

CNTPS_CVAL_EL1 ¶
Source

CNTPS_CVAL_EL1 :: i64(0x7F12)

3 7 14 2 2

CNTPS_TVAL_EL1 ¶
Source

CNTPS_TVAL_EL1 :: i64(0x7F10)

3 7 14 2 0

CNTP_CTL_EL0 ¶
Source

CNTP_CTL_EL0 :: i64(0x5F11)

3 3 14 2 1

CNTP_CVAL_EL0 ¶
Source

CNTP_CVAL_EL0 :: i64(0x5F12)

3 3 14 2 2

CNTP_TVAL_EL0 ¶
Source

CNTP_TVAL_EL0 :: i64(0x5F10)

3 3 14 2 0

CNTVCT_EL0 ¶
Source

CNTVCT_EL0 :: i64(0x5F02)

3 3 14 0 2

CNTVOFF_EL2 ¶
Source

CNTVOFF_EL2 :: i64(0x671B)

3 4 14 0 3

CNTV_CTL_EL0 ¶
Source

CNTV_CTL_EL0 :: i64(0x5F19)

3 3 14 3 1

CNTV_CVAL_EL0 ¶
Source

CNTV_CVAL_EL0 :: i64(0x5F1A)

3 3 14 3 2

CNTV_TVAL_EL0 ¶
Source

CNTV_TVAL_EL0 :: i64(0x5F18)

3 3 14 3 0

COND_HS ¶
Source

COND_HS :: Cond.CS

Architectural aliases for the two carry-style conditions.

COND_LO ¶
Source

COND_LO :: Cond.CC

CONTEXTIDR_EL1 ¶
Source

CONTEXTIDR_EL1 :: i64(0x4681)

----------------------------------------------------------------------------- Memory attribute / context / control registers -----------------------------------------------------------------------------

CPACR_EL1 ¶
Source

CPACR_EL1 :: i64(0x4082)

3 0 1 0 2

CSSELR_EL1 ¶
Source

CSSELR_EL1 :: i64(0x5000)

3 2 0 0 0

CTR_EL0 ¶
Source

CTR_EL0 :: i64(0x5801)

3 3 0 0 1

CURRENT_EL ¶
Source

CURRENT_EL :: i64(0x4212)

3 0 4 2 2

DACR32_EL2 ¶
Source

DACR32_EL2 :: i64(0x6180)

3 4 3 0 0

DAIF ¶
Source

DAIF :: i64(0x5A11)

3 3 4 2 1

DBGAUTHSTATUS_EL1 ¶
Source

DBGAUTHSTATUS_EL1 :: i64(0x1BF6)

2 0 7 14 6

DBGCLAIMCLR_EL1 ¶
Source

DBGCLAIMCLR_EL1 :: i64(0x1BCE)

2 0 7 9 6

DBGCLAIMSET_EL1 ¶
Source

DBGCLAIMSET_EL1 :: i64(0x1BC6)

2 0 7 8 6

DBGDTRRX_EL0 ¶
Source

DBGDTRRX_EL0 :: i64(0x1A28)

2 3 0 5 0

DBGDTRTX_EL0 ¶
Source

DBGDTRTX_EL0 :: i64(0x1A28)

DBGDTR_EL0 ¶
Source

DBGDTR_EL0 :: i64(0x1A20)

Other debug registers

DBGPRCR_EL1 ¶
Source

DBGPRCR_EL1 :: i64(0x0084)

(collision flag; treat as canonical from doc)

DCZID_EL0 ¶
Source

DCZID_EL0 :: i64(0x5807)

3 3 0 0 7 (used by __sve_max_vl-style probes too)

DEFAULT_PRINT_OPTIONS ¶
Source

DEFAULT_PRINT_OPTIONS: rexcode_isa.Print_Options : isa.DEFAULT_PRINT_OPTIONS

DISR_EL1 ¶
Source

DISR_EL1 :: i64(0x4609)

3 0 12 1 1

DLR_EL0 ¶
Source

DLR_EL0 :: i64(0x5A29)

3 3 4 5 1

DSPSR_EL0 ¶
Source

DSPSR_EL0 :: i64(0x5A28)

3 3 4 5 0

ELR_EL1 ¶
Source

ELR_EL1 :: i64(0x4201)

3 0 4 0 1

ELR_EL2 ¶
Source

ELR_EL2 :: i64(0x6201)

3 4 4 0 1

ELR_EL3 ¶
Source

ELR_EL3 :: i64(0x7201)

3 6 4 0 1

ERRIDR_EL1 ¶
Source

ERRIDR_EL1 :: i64(0x4298)

3 0 5 3 0

ERRSELR_EL1 ¶
Source

ERRSELR_EL1 :: i64(0x4299)

---- RAS (Reliability, Availability, Serviceability) ----

ERXADDR_EL1 ¶
Source

ERXADDR_EL1 :: i64(0x42A3)

3 0 5 4 3

ERXCTLR_EL1 ¶
Source

ERXCTLR_EL1 :: i64(0x42A1)

3 0 5 4 1

ERXFR_EL1 ¶
Source

ERXFR_EL1 :: i64(0x42A0)

3 0 5 4 0

ERXMISC0_EL1 ¶
Source

ERXMISC0_EL1 :: i64(0x42A8)

3 0 5 5 0

ERXMISC1_EL1 ¶
Source

ERXMISC1_EL1 :: i64(0x42A9)

3 0 5 5 1

ERXMISC2_EL1 ¶
Source

ERXMISC2_EL1 :: i64(0x42AA)

3 0 5 5 2

ERXMISC3_EL1 ¶
Source

ERXMISC3_EL1 :: i64(0x42AB)

3 0 5 5 3

ERXSTATUS_EL1 ¶
Source

ERXSTATUS_EL1 :: i64(0x42A2)

3 0 5 4 2

ESR_EL1 ¶
Source

ESR_EL1 :: i64(0x5290)

3 0 5 2 0

ESR_EL2 ¶
Source

ESR_EL2 :: i64(0x6290)

3 4 5 2 0

FAR_EL1 ¶
Source

FAR_EL1 :: i64(0x5300)

3 0 6 0 0

FAR_EL2 ¶
Source

FAR_EL2 :: i64(0x6300)

3 4 6 0 0

FPCR ¶
Source

FPCR :: i64(0x5A20)

3 3 4 4 0

FPEXC32_EL2 ¶
Source

FPEXC32_EL2 :: i64(0x6298)

3 4 5 3 0

FPSR ¶
Source

FPSR :: i64(0x5A21)

3 3 4 4 1

FP_REG ¶
Source

FP_REG: Register : X29

frame pointer (avoid collision with FP if added later)

GCR_EL1 ¶
Source

GCR_EL1 :: i64(0x4289)

3 0 5 1 2 (FEAT_MTE)

GMID_EL1 ¶
Source

GMID_EL1 :: i64(0x4804)

3 1 0 0 4 (FEAT_MTE)

GPCCR_EL3 ¶
Source

GPCCR_EL3 :: i64(0x70B6)

---- RME (Realm Management Extension) sysregs ----

GPTBR_EL3 ¶
Source

GPTBR_EL3 :: i64(0x70B4)

3 6 2 1 4 (Granule Protection Table Base)

HCR_EL2 ¶
Source

HCR_EL2 :: i64(0x6088)

3 4 1 1 0

HSTR_EL2 ¶
Source

HSTR_EL2 :: i64(0x608B)

3 4 1 1 3

ICC_ASGI1R_EL1 ¶
Source

ICC_ASGI1R_EL1 :: i64(0x5CDE)

3 3 12 11 6

ICC_BPR0_EL1 ¶
Source

ICC_BPR0_EL1 :: i64(0x4C43)

3 0 12 8 3

ICC_BPR1_EL1 ¶
Source

ICC_BPR1_EL1 :: i64(0x4C63)

3 0 12 12 3

ICC_CTLR_EL1 ¶
Source

ICC_CTLR_EL1 :: i64(0x4C64)

3 0 12 12 4

ICC_CTLR_EL3 ¶
Source

ICC_CTLR_EL3 :: i64(0x7C64)

3 6 12 12 4

ICC_DIR_EL1 ¶
Source

ICC_DIR_EL1 :: i64(0x4C59)

3 0 12 11 1

ICC_EOIR0_EL1 ¶
Source

ICC_EOIR0_EL1 :: i64(0x4C41)

3 0 12 8 1

ICC_EOIR1_EL1 ¶
Source

ICC_EOIR1_EL1 :: i64(0x4C61)

3 0 12 12 1

ICC_HPPIR0_EL1 ¶
Source

ICC_HPPIR0_EL1 :: i64(0x4C42)

3 0 12 8 2

ICC_HPPIR1_EL1 ¶
Source

ICC_HPPIR1_EL1 :: i64(0x4C62)

3 0 12 12 2

ICC_IAR0_EL1 ¶
Source

ICC_IAR0_EL1 :: i64(0x4C40)

---- GICv3 (ICC_*) -- CPU interface ----

ICC_IAR1_EL1 ¶
Source

ICC_IAR1_EL1 :: i64(0x4C60)

3 0 12 12 0

ICC_IGRPEN0_EL1 ¶
Source

ICC_IGRPEN0_EL1 :: i64(0x4C66)

3 0 12 12 6

ICC_IGRPEN1_EL1 ¶
Source

ICC_IGRPEN1_EL1 :: i64(0x4C67)

3 0 12 12 7

ICC_IGRPEN1_EL3 ¶
Source

ICC_IGRPEN1_EL3 :: i64(0x7C67)

3 6 12 12 7

ICC_PMR_EL1 ¶
Source

ICC_PMR_EL1 :: i64(0x4630)

3 0 4 6 0

ICC_RPR_EL1 ¶
Source

ICC_RPR_EL1 :: i64(0x4C5B)

3 0 12 11 3

ICC_SGI0R_EL1 ¶
Source

ICC_SGI0R_EL1 :: i64(0x5CDF)

3 3 12 11 7

ICC_SGI1R_EL1 ¶
Source

ICC_SGI1R_EL1 :: i64(0x5CDD)

3 3 12 11 5

ICC_SRE_EL1 ¶
Source

ICC_SRE_EL1 :: i64(0x4C65)

3 0 12 12 5

ICC_SRE_EL2 ¶
Source

ICC_SRE_EL2 :: i64(0x6C65)

3 4 12 9 5

ICC_SRE_EL3 ¶
Source

ICC_SRE_EL3 :: i64(0x7C65)

3 6 12 12 5

ICH_EISR_EL2 ¶
Source

ICH_EISR_EL2 :: i64(0x6CDB)

3 4 12 11 3

ICH_ELRSR_EL2 ¶
Source

ICH_ELRSR_EL2 :: i64(0x6CDD)

3 4 12 11 5

ICH_HCR_EL2 ¶
Source

ICH_HCR_EL2 :: i64(0x6CD8)

---- GICv3 hypervisor (ICH_*) ----

ICH_MISR_EL2 ¶
Source

ICH_MISR_EL2 :: i64(0x6CDA)

3 4 12 11 2

ICH_VMCR_EL2 ¶
Source

ICH_VMCR_EL2 :: i64(0x6CDF)

3 4 12 11 7

ICH_VTR_EL2 ¶
Source

ICH_VTR_EL2 :: i64(0x6CD9)

3 4 12 11 1

ID_AA64AFR0_EL1 ¶
Source

ID_AA64AFR0_EL1 :: i64(0x402C)

3 0 0 5 4 (auxiliary)

ID_AA64AFR1_EL1 ¶
Source

ID_AA64AFR1_EL1 :: i64(0x402D)

3 0 0 5 5

ID_AA64DFR0_EL1 ¶
Source

ID_AA64DFR0_EL1 :: i64(0x4028)

3 0 0 5 0

ID_AA64DFR1_EL1 ¶
Source

ID_AA64DFR1_EL1 :: i64(0x4029)

3 0 0 5 1

ID_AA64DFR2_EL1 ¶
Source

ID_AA64DFR2_EL1 :: i64(0x402A)

---- More ID registers (AArch32 + extras) ----

ID_AA64ISAR0_EL1 ¶
Source

ID_AA64ISAR0_EL1 :: i64(0x4030)

----------------------------------------------------------------------------- Identification registers (ID_AA64*_EL1) -- read-only feature bitmaps -----------------------------------------------------------------------------

ID_AA64ISAR1_EL1 ¶
Source

ID_AA64ISAR1_EL1 :: i64(0x4031)

3 0 0 6 1

ID_AA64ISAR2_EL1 ¶
Source

ID_AA64ISAR2_EL1 :: i64(0x4032)

3 0 0 6 2

ID_AA64ISAR3_EL1 ¶
Source

ID_AA64ISAR3_EL1 :: i64(0x4033)

3 0 0 6 3

ID_AA64MMFR0_EL1 ¶
Source

ID_AA64MMFR0_EL1 :: i64(0x4038)

3 0 0 7 0

ID_AA64MMFR1_EL1 ¶
Source

ID_AA64MMFR1_EL1 :: i64(0x4039)

3 0 0 7 1

ID_AA64MMFR2_EL1 ¶
Source

ID_AA64MMFR2_EL1 :: i64(0x403A)

3 0 0 7 2

ID_AA64PFR0_EL1 ¶
Source

ID_AA64PFR0_EL1 :: i64(0x4020)

3 0 0 4 0

ID_AA64PFR1_EL1 ¶
Source

ID_AA64PFR1_EL1 :: i64(0x4021)

3 0 0 4 1

ID_AA64SMFR0_EL1 ¶
Source

ID_AA64SMFR0_EL1 :: i64(0x4025)

3 0 0 4 5 (SME feature ID)

ID_AA64ZFR0_EL1 ¶
Source

ID_AA64ZFR0_EL1 :: i64(0x4024)

----------------------------------------------------------------------------- More ID registers -----------------------------------------------------------------------------

ID_AFR0_EL1 ¶
Source

ID_AFR0_EL1 :: i64(0x400B)

3 0 0 1 3

ID_DFR0_EL1 ¶
Source

ID_DFR0_EL1 :: i64(0x400A)

3 0 0 1 2

ID_ISAR0_EL1 ¶
Source

ID_ISAR0_EL1 :: i64(0x4010)

3 0 0 2 0

ID_ISAR1_EL1 ¶
Source

ID_ISAR1_EL1 :: i64(0x4011)

3 0 0 2 1

ID_ISAR2_EL1 ¶
Source

ID_ISAR2_EL1 :: i64(0x4012)

3 0 0 2 2

ID_ISAR3_EL1 ¶
Source

ID_ISAR3_EL1 :: i64(0x4013)

3 0 0 2 3

ID_ISAR4_EL1 ¶
Source

ID_ISAR4_EL1 :: i64(0x4014)

3 0 0 2 4

ID_ISAR5_EL1 ¶
Source

ID_ISAR5_EL1 :: i64(0x4015)

3 0 0 2 5

ID_ISAR6_EL1 ¶
Source

ID_ISAR6_EL1 :: i64(0x4017)

3 0 0 2 7

ID_MMFR0_EL1 ¶
Source

ID_MMFR0_EL1 :: i64(0x400C)

3 0 0 1 4

ID_MMFR1_EL1 ¶
Source

ID_MMFR1_EL1 :: i64(0x400D)

3 0 0 1 5

ID_MMFR2_EL1 ¶
Source

ID_MMFR2_EL1 :: i64(0x400E)

3 0 0 1 6

ID_MMFR3_EL1 ¶
Source

ID_MMFR3_EL1 :: i64(0x400F)

3 0 0 1 7

ID_MMFR4_EL1 ¶
Source

ID_MMFR4_EL1 :: i64(0x4036)

3 0 0 6 6

ID_MMFR5_EL1 ¶
Source

ID_MMFR5_EL1 :: i64(0x402E)

3 0 0 5 6

ID_PFR0_EL1 ¶
Source

ID_PFR0_EL1 :: i64(0x4008)

3 0 0 1 0

ID_PFR1_EL1 ¶
Source

ID_PFR1_EL1 :: i64(0x4009)

3 0 0 1 1

ID_PFR2_EL1 ¶
Source

ID_PFR2_EL1 :: i64(0x402C)

(overlap historic; check if collision)

ISR_EL1 ¶
Source

ISR_EL1 :: i64(0x4608)

3 0 12 1 0

LABEL_UNDEFINED ¶
Source

LABEL_UNDEFINED: rexcode_isa.Label_Definition : isa.LABEL_UNDEFINED

LORC_EL1 ¶
Source

LORC_EL1 :: i64(0x4523)

---- LOR (Limited Ordering Region) ----

LOREA_EL1 ¶
Source

LOREA_EL1 :: i64(0x4521)

3 0 10 4 1

LORID_EL1 ¶
Source

LORID_EL1 :: i64(0x4527)

3 0 10 4 7

LORN_EL1 ¶
Source

LORN_EL1 :: i64(0x4522)

3 0 10 4 2

LORSA_EL1 ¶
Source

LORSA_EL1 :: i64(0x4520)

3 0 10 4 0

LR ¶
Source

LR: Register : X30

procedure call link register

MAIR_EL1 ¶
Source

MAIR_EL1 :: i64(0x4510)

3 0 10 2 0

MAX_INST_SIZE ¶
Source

MAX_INST_SIZE :: 4

MDCCINT_EL1 ¶
Source

MDCCINT_EL1 :: i64(0x0010)

2 0 0 2 0

MDCR_EL2 ¶
Source

MDCR_EL2 :: i64(0x6089)

3 4 1 1 1

MDRAR_EL1 ¶
Source

MDRAR_EL1 :: i64(0x1080)

2 0 1 0 0

MDSCR_EL1 ¶
Source

MDSCR_EL1 :: i64(0x0012)

----------------------------------------------------------------------------- Debug registers (op0 = 2) -----------------------------------------------------------------------------

MFAR_EL3 ¶
Source

MFAR_EL3 :: i64(0x7305)

3 6 6 0 5 (Multiple FAR)

MIDR_EL1 ¶
Source

MIDR_EL1 :: i64(0x4000)

3 0 0 0 0

MPIDR_EL1 ¶
Source

MPIDR_EL1 :: i64(0x4005)

3 0 0 0 5

MVFR0_EL1 ¶
Source

MVFR0_EL1 :: i64(0x4018)

3 0 0 3 0

MVFR1_EL1 ¶
Source

MVFR1_EL1 :: i64(0x4019)

3 0 0 3 1

MVFR2_EL1 ¶
Source

MVFR2_EL1 :: i64(0x401A)

3 0 0 3 2

NONE ¶
Source

NONE :: Register(0xFFFF)

NZCV ¶
Source

NZCV :: i64(0x5A10)

op0 op1 CRn CRm op2

OSLAR_EL1 ¶
Source

OSLAR_EL1 :: i64(0x0084)

2 0 1 0 4 (op0=2 -> o0=0)

OSLSR_EL1 ¶
Source

OSLSR_EL1 :: i64(0x008C)

2 0 1 1 4

PAR_EL1 ¶
Source

PAR_EL1 :: i64(0x4380)

---- Translation result (returned by AT) ----

PMBIDR_EL1 ¶
Source

PMBIDR_EL1 :: i64(0x4957)

3 0 9 10 7

PMBLIMITR_EL1 ¶
Source

PMBLIMITR_EL1 :: i64(0x4950)

3 0 9 10 0

PMBPTR_EL1 ¶
Source

PMBPTR_EL1 :: i64(0x4951)

3 0 9 10 1

PMBSR_EL1 ¶
Source

PMBSR_EL1 :: i64(0x4953)

3 0 9 10 3

PMCCFILTR_EL0 ¶
Source

PMCCFILTR_EL0 :: i64(0x5F7F)

---- Performance Monitor extras ----

PMCCNTR_EL0 ¶
Source

PMCCNTR_EL0 :: i64(0x5CE8)

3 3 9 13 0

PMCEID0_EL0 ¶
Source

PMCEID0_EL0 :: i64(0x5CE6)

3 3 9 12 6

PMCEID1_EL0 ¶
Source

PMCEID1_EL0 :: i64(0x5CE7)

3 3 9 12 7

PMCNTENCLR_EL0 ¶
Source

PMCNTENCLR_EL0 :: i64(0x5CE2)

3 3 9 12 2

PMCNTENSET_EL0 ¶
Source

PMCNTENSET_EL0 :: i64(0x5CE1)

3 3 9 12 1

PMCR_EL0 ¶
Source

PMCR_EL0 :: i64(0x5CE0)

----------------------------------------------------------------------------- Performance Monitor Unit (PMU) -----------------------------------------------------------------------------

PMINTENCLR_EL1 ¶
Source

PMINTENCLR_EL1 :: i64(0x4CE2)

3 0 9 14 2

PMINTENSET_EL1 ¶
Source

PMINTENSET_EL1 :: i64(0x4CE1)

3 0 9 14 1

PMOVSCLR_EL0 ¶
Source

PMOVSCLR_EL0 :: i64(0x5CE3)

3 3 9 12 3

PMSCR_EL1 ¶
Source

PMSCR_EL1 :: i64(0x4948)

---- SPE (Statistical Profiling Extension, FEAT_SPE) ----

PMSELR_EL0 ¶
Source

PMSELR_EL0 :: i64(0x5CE5)

3 3 9 12 5

PMSEVFR_EL1 ¶
Source

PMSEVFR_EL1 :: i64(0x494D)

3 0 9 9 5

PMSFCR_EL1 ¶
Source

PMSFCR_EL1 :: i64(0x494C)

3 0 9 9 4

PMSICR_EL1 ¶
Source

PMSICR_EL1 :: i64(0x494A)

3 0 9 9 2

PMSIDR_EL1 ¶
Source

PMSIDR_EL1 :: i64(0x494F)

3 0 9 9 7

PMSIRR_EL1 ¶
Source

PMSIRR_EL1 :: i64(0x494B)

3 0 9 9 3

PMSLATFR_EL1 ¶
Source

PMSLATFR_EL1 :: i64(0x494E)

3 0 9 9 6

PMSWINC_EL0 ¶
Source

PMSWINC_EL0 :: i64(0x5CE4)

3 3 9 12 4

PMUSERENR_EL0 ¶
Source

PMUSERENR_EL0 :: i64(0x5CF0)

3 3 9 14 0

PMUSERENR_EL0_REPEAT ¶
Source

PMUSERENR_EL0_REPEAT: i64 : PMUSERENR_EL0

re-export alias placeholder

PRSELR_EL1 ¶
Source

PRSELR_EL1 :: i64(0x4288)

----------------------------------------------------------------------------- Cache / data prefetch hint controls -----------------------------------------------------------------------------

REG_B ¶
Source

REG_B :: 0x0600

B0..B31 (byte view)

REG_D ¶
Source

REG_D :: 0x0900

D0..D31 (double view)

REG_H ¶
Source

REG_H :: 0x0700

H0..H31 (half view)

REG_NONE ¶
Source

REG_NONE :: 0x0000

REG_P ¶
Source

REG_P :: 0x0C00

P0..P15 SVE predicate

REG_Q ¶
Source

REG_Q :: 0x0A00

Q0..Q31 (quad view)

REG_S ¶
Source

REG_S :: 0x0800

S0..S31 (single view)

REG_V ¶
Source

REG_V :: 0x0500

V0..V31 (full 128-bit; used in NEON vector form)

REG_W ¶
Source

REG_W :: 0x0200

W0..W30, WZR

REG_WSP ¶
Source

REG_WSP :: 0x0400

WSP

REG_X ¶
Source

REG_X :: 0x0100

X0..X30, XZR (X31 = ZR semantically)

REG_XSP ¶
Source

REG_XSP :: 0x0300

SP (only -- distinct class from X to opt-in)

REG_Z ¶
Source

REG_Z :: 0x0B00

Z0..Z31 SVE scalable vector (low 128 aliased with V)

RGSR_EL1 ¶
Source

RGSR_EL1 :: i64(0x4288)

----------------------------------------------------------------------------- Cache / Memory feature extras -----------------------------------------------------------------------------

RNDR ¶
Source

RNDR :: i64(0x5920)

----------------------------------------------------------------------------- Random number registers (v8.5-A FEAT_RNG) -----------------------------------------------------------------------------

RNDRRS ¶
Source

RNDRRS :: i64(0x5921)

3 3 2 4 1

SCTLR_EL1 ¶
Source

SCTLR_EL1 :: i64(0x4080)

3 0 1 0 0

SCTLR_EL2 ¶
Source

SCTLR_EL2 :: i64(0x6080)

----------------------------------------------------------------------------- EL2 / EL3 control + return registers -----------------------------------------------------------------------------

SCTLR_EL3 ¶
Source

SCTLR_EL3 :: i64(0x7080)

3 6 1 0 0

SMCR_EL1 ¶
Source

SMCR_EL1 :: i64(0x4296)

3 0 1 2 6 (FEAT_SME)

SMCR_EL2 ¶
Source

SMCR_EL2 :: i64(0x6296)

3 4 1 2 6

SP ¶
Source

SP :: Register(REG_XSP | 31)

SPSR_EL1 ¶
Source

SPSR_EL1 :: i64(0x4200)

3 0 4 0 0

SPSR_EL2 ¶
Source

SPSR_EL2 :: i64(0x6200)

3 4 4 0 0

SPSR_EL3 ¶
Source

SPSR_EL3 :: i64(0x7200)

3 6 4 0 0

SP_EL0 ¶
Source

SP_EL0 :: i64(0x4208)

3 0 4 1 0

SP_EL1 ¶
Source

SP_EL1 :: i64(0x6208)

3 4 4 1 0

SVCR ¶
Source

SVCR :: i64(0x5A22)

----------------------------------------------------------------------------- SME / SVE configuration -----------------------------------------------------------------------------

TCR_EL1 ¶
Source

TCR_EL1 :: i64(0x4282)

3 0 2 0 2

TFSRE0_EL1 ¶
Source

TFSRE0_EL1 :: i64(0x4301)

3 0 6 0 1 (FEAT_MTE)

TFSR_EL1 ¶
Source

TFSR_EL1 :: i64(0x4300)

3 0 6 0 0 (FEAT_MTE)

TPIDR2_EL0 ¶
Source

TPIDR2_EL0 :: i64(0x5E85)

3 3 13 0 5 (SME thread pointer 2)

TPIDRRO_EL0 ¶
Source

TPIDRRO_EL0 :: i64(0x5E83)

3 3 13 0 3

TPIDR_EL0 ¶
Source

TPIDR_EL0 :: i64(0x5E82)

3 3 13 0 2

TPIDR_EL1 ¶
Source

TPIDR_EL1 :: i64(0x4684)

3 0 13 0 4 (corrected: 3 0 13 0 4 -> 4684 hmm let me recompute)

TPIDR_EL2 ¶
Source

TPIDR_EL2 :: i64(0x6E82)

3 4 13 0 2

TPIDR_EL3 ¶
Source

TPIDR_EL3 :: i64(0x7682)

3 6 13 0 2 -- err, EL3 needs op1=6

TRBBASER_EL1 ¶
Source

TRBBASER_EL1 :: i64(0x4B92)

3 0 9 11 2

TRBIDR_EL1 ¶
Source

TRBIDR_EL1 :: i64(0x4B97)

3 0 9 11 7

TRBLIMITR_EL1 ¶
Source

TRBLIMITR_EL1 :: i64(0x4B90)

---- TRBE (Trace Buffer Extension, FEAT_TRBE) ----

TRBMAR_EL1 ¶
Source

TRBMAR_EL1 :: i64(0x4B94)

3 0 9 11 4

TRBPTR_EL1 ¶
Source

TRBPTR_EL1 :: i64(0x4B91)

3 0 9 11 1

TRBSR_EL1 ¶
Source

TRBSR_EL1 :: i64(0x4B93)

3 0 9 11 3

TRBTRG_EL1 ¶
Source

TRBTRG_EL1 :: i64(0x4B96)

3 0 9 11 6

TTBR0_EL1 ¶
Source

TTBR0_EL1 :: i64(0x4100)

3 0 2 0 0

TTBR1_EL1 ¶
Source

TTBR1_EL1 :: i64(0x4101)

3 0 2 0 1

V0 ¶
Source

V0 :: Register(REG_V | 0)

V1 ¶
Source

V1 :: Register(REG_V | 1)

V10 ¶
Source

V10 :: Register(REG_V | 10)

V11 ¶
Source

V11 :: Register(REG_V | 11)

V12 ¶
Source

V12 :: Register(REG_V | 12)

V13 ¶
Source

V13 :: Register(REG_V | 13)

V14 ¶
Source

V14 :: Register(REG_V | 14)

V15 ¶
Source

V15 :: Register(REG_V | 15)

V16 ¶
Source

V16 :: Register(REG_V | 16)

V17 ¶
Source

V17 :: Register(REG_V | 17)

V18 ¶
Source

V18 :: Register(REG_V | 18)

V19 ¶
Source

V19 :: Register(REG_V | 19)

V2 ¶
Source

V2 :: Register(REG_V | 2)

V20 ¶
Source

V20 :: Register(REG_V | 20)

V21 ¶
Source

V21 :: Register(REG_V | 21)

V22 ¶
Source

V22 :: Register(REG_V | 22)

V23 ¶
Source

V23 :: Register(REG_V | 23)

V24 ¶
Source

V24 :: Register(REG_V | 24)

V25 ¶
Source

V25 :: Register(REG_V | 25)

V26 ¶
Source

V26 :: Register(REG_V | 26)

V27 ¶
Source

V27 :: Register(REG_V | 27)

V28 ¶
Source

V28 :: Register(REG_V | 28)

V29 ¶
Source

V29 :: Register(REG_V | 29)

V3 ¶
Source

V3 :: Register(REG_V | 3)

V30 ¶
Source

V30 :: Register(REG_V | 30)

V31 ¶
Source

V31 :: Register(REG_V | 31)

V4 ¶
Source

V4 :: Register(REG_V | 4)

V5 ¶
Source

V5 :: Register(REG_V | 5)

V6 ¶
Source

V6 :: Register(REG_V | 6)

V7 ¶
Source

V7 :: Register(REG_V | 7)

V8 ¶
Source

V8 :: Register(REG_V | 8)

V9 ¶
Source

V9 :: Register(REG_V | 9)

VBAR_EL1 ¶
Source

VBAR_EL1 :: i64(0x4600)

3 0 12 0 0

VBAR_EL2 ¶
Source

VBAR_EL2 :: i64(0x6600)

3 4 12 0 0

VBAR_EL3 ¶
Source

VBAR_EL3 :: i64(0x7600)

3 6 12 0 0

VDISR_EL2 ¶
Source

VDISR_EL2 :: i64(0x6609)

3 4 12 1 1

VSESR_EL2 ¶
Source

VSESR_EL2 :: i64(0x628B)

3 4 5 2 3

VTCR_EL2 ¶
Source

VTCR_EL2 :: i64(0x610A)

3 4 2 1 2

VTTBR_EL2 ¶
Source

VTTBR_EL2 :: i64(0x6108)

3 4 2 1 0

W0 ¶
Source

W0 :: Register(REG_W | 0)

W1 ¶
Source

W1 :: Register(REG_W | 1)

W10 ¶
Source

W10 :: Register(REG_W | 10)

W11 ¶
Source

W11 :: Register(REG_W | 11)

W12 ¶
Source

W12 :: Register(REG_W | 12)

W13 ¶
Source

W13 :: Register(REG_W | 13)

W14 ¶
Source

W14 :: Register(REG_W | 14)

W15 ¶
Source

W15 :: Register(REG_W | 15)

W16 ¶
Source

W16 :: Register(REG_W | 16)

W17 ¶
Source

W17 :: Register(REG_W | 17)

W18 ¶
Source

W18 :: Register(REG_W | 18)

W19 ¶
Source

W19 :: Register(REG_W | 19)

W2 ¶
Source

W2 :: Register(REG_W | 2)

W20 ¶
Source

W20 :: Register(REG_W | 20)

W21 ¶
Source

W21 :: Register(REG_W | 21)

W22 ¶
Source

W22 :: Register(REG_W | 22)

W23 ¶
Source

W23 :: Register(REG_W | 23)

W24 ¶
Source

W24 :: Register(REG_W | 24)

W25 ¶
Source

W25 :: Register(REG_W | 25)

W26 ¶
Source

W26 :: Register(REG_W | 26)

W27 ¶
Source

W27 :: Register(REG_W | 27)

W28 ¶
Source

W28 :: Register(REG_W | 28)

W29 ¶
Source

W29 :: Register(REG_W | 29)

W3 ¶
Source

W3 :: Register(REG_W | 3)

W30 ¶
Source

W30 :: Register(REG_W | 30)

W4 ¶
Source

W4 :: Register(REG_W | 4)

W5 ¶
Source

W5 :: Register(REG_W | 5)

W6 ¶
Source

W6 :: Register(REG_W | 6)

W7 ¶
Source

W7 :: Register(REG_W | 7)

W8 ¶
Source

W8 :: Register(REG_W | 8)

W9 ¶
Source

W9 :: Register(REG_W | 9)

WSP ¶
Source

WSP :: Register(REG_WSP | 31)

WZR ¶
Source

WZR :: Register(REG_W | 31)

X0 ¶
Source

X0 :: Register(REG_X | 0)

X1 ¶
Source

X1 :: Register(REG_X | 1)

X10 ¶
Source

X10 :: Register(REG_X | 10)

X11 ¶
Source

X11 :: Register(REG_X | 11)

X12 ¶
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X12 :: Register(REG_X | 12)

X13 ¶
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X13 :: Register(REG_X | 13)

X14 ¶
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X14 :: Register(REG_X | 14)

X15 ¶
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X15 :: Register(REG_X | 15)

X16 ¶
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X16 :: Register(REG_X | 16)

X17 ¶
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X17 :: Register(REG_X | 17)

X18 ¶
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X18 :: Register(REG_X | 18)

X19 ¶
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X19 :: Register(REG_X | 19)

X2 ¶
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X2 :: Register(REG_X | 2)

X20 ¶
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X20 :: Register(REG_X | 20)

X21 ¶
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X21 :: Register(REG_X | 21)

X22 ¶
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X22 :: Register(REG_X | 22)

X23 ¶
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X23 :: Register(REG_X | 23)

X24 ¶
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X24 :: Register(REG_X | 24)

X25 ¶
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X25 :: Register(REG_X | 25)

X26 ¶
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X26 :: Register(REG_X | 26)

X27 ¶
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X27 :: Register(REG_X | 27)

X28 ¶
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X28 :: Register(REG_X | 28)

X29 ¶
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X29 :: Register(REG_X | 29)

X3 ¶
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X3 :: Register(REG_X | 3)

X30 ¶
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X30 :: Register(REG_X | 30)

X4 ¶
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X4 :: Register(REG_X | 4)

X5 ¶
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X5 :: Register(REG_X | 5)

X6 ¶
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X6 :: Register(REG_X | 6)

X7 ¶
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X7 :: Register(REG_X | 7)

X8 ¶
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X8 :: Register(REG_X | 8)

X9 ¶
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X9 :: Register(REG_X | 9)

XZR ¶
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XZR :: Register(REG_X | 31)

ZCR_EL1 ¶
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ZCR_EL1 :: i64(0x4290)

3 0 1 2 0 (FEAT_SVE)

ZCR_EL2 ¶
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ZCR_EL2 :: i64(0x6290)

3 4 1 2 0

ZCR_EL3 ¶
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ZCR_EL3 :: i64(0x7290)

3 6 1 2 0

Variables

DECODE_ENTRIES ¶
Source

@(rodata)
DECODE_ENTRIES: []Decode_Entry = …

DECODE_INDEX_OP0 ¶
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@(rodata)
DECODE_INDEX_OP0: []Decode_Index = …

ENCODE_FORMS ¶
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@(rodata)
ENCODE_FORMS: []Encoding = …

ENCODE_RUNS ¶
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@(rodata)
ENCODE_RUNS: []Encode_Run = …

Procedures

aprint ¶
Source

aprint :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
	allocator := context.allocator, 
) -> string {…}

aprintln ¶
Source

aprintln :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
	allocator := context.allocator, 
) -> string {…}

b_reg ¶
Source

b_reg :: proc "contextless" (n: u8) -> Register {…}

Scalar view constructors -- the hw number is the same V register.

bprint ¶
Source

bprint :: proc(
	buf:          []u8, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

bprintln ¶
Source

bprintln :: proc(
	buf:          []u8, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

d_reg ¶
Source

d_reg :: proc "contextless" (n: u8) -> Register {…}

decode ¶
Source

decode :: proc(
	data:         []u8, 
	relocs:       []Relocation, 
	instructions: ^[dynamic]Instruction, 
	inst_info:    ^[dynamic]Instruction_Info, 
	label_defs:   ^[dynamic]rexcode_isa.Label_Definition, 
	errors:       ^[dynamic]rexcode_isa.Error, 
	endianness:   Endianness = .LITTLE, 
) -> (byte_count: u32, ok: bool) {…}

decode_bitmask_imm ¶
Source

decode_bitmask_imm :: proc "contextless" (n, immr, imms: u8, is_64: bool) -> (value: u64, ok: bool) {…}

decode_bitmask_imm reconstructs the logical bitmask value from N:immr:imms, at the given width (32 or 64). Returns ok=false if the encoding is invalid.

decode_estimate_instruction_count ¶
Source

decode_estimate_instruction_count :: proc "contextless" (data: []u8) -> int {…}

Typical-case estimate (AArch64 is fixed 4 bytes/instruction, so this is exact).

decode_max_instruction_count ¶
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decode_max_instruction_count :: proc "contextless" (data: []u8) -> int {…}

Exact instruction-count ceiling for data (AArch64 instructions are 4 bytes).

decode_reserve ¶
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decode_reserve :: proc(instructions: ^[dynamic]Instruction, inst_info: ^[dynamic]Instruction_Info, label_defs: ^[dynamic]rexcode_isa.Label_Definition, data: []u8, exact: bool = false) {…}

Pre-size the caller's decode output arrays for data (reserves on top of any existing elements; nil to skip; exact=true for the ceiling, else the estimate).

emit_abs_v ¶
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emit_abs_v :: emit_abs_v_r_r

emit_abs_v_r_r ¶
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emit_abs_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_adc ¶
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emit_adc :: emit_adc_r_r_r

emit_adc_r_r_r ¶
Source

emit_adc_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_adcs ¶
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emit_adcs :: emit_adcs_r_r_r

emit_adcs_r_r_r ¶
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emit_adcs_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_add_er ¶
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emit_add_er :: emit_add_er_r_r_ex

emit_add_er_r_r_ex ¶
Source

emit_add_er_r_r_ex :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_ext:     Extend, 
	src2_amount:  u8, 
) {…}

emit_add_imm ¶
Source

emit_add_imm :: emit_add_imm_r_r_i

emit_add_imm_r_r_i ¶
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emit_add_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_add_sr ¶
Source

emit_add_sr :: emit_add_sr_r_r_sh

emit_add_sr_r_r_sh ¶
Source

emit_add_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_add_v ¶
Source

emit_add_v :: emit_add_v_r_r_r

emit_add_v_r_r_r ¶
Source

emit_add_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_addg ¶
Source

emit_addg :: emit_addg_r_r_i_i

emit_addg_r_r_i_i ¶
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emit_addg_r_r_i_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) {…}

emit_addhn ¶
Source

emit_addhn :: emit_addhn_r_r_r

emit_addhn2 ¶
Source

emit_addhn2 :: emit_addhn2_r_r_r

emit_addhn2_r_r_r ¶
Source

emit_addhn2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_addhn_r_r_r ¶
Source

emit_addhn_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_addp_v ¶
Source

emit_addp_v :: emit_addp_v_r_r_r

emit_addp_v_r_r_r ¶
Source

emit_addp_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_adds_er ¶
Source

emit_adds_er :: emit_adds_er_r_r_ex

emit_adds_er_r_r_ex ¶
Source

emit_adds_er_r_r_ex :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_ext:     Extend, 
	src2_amount:  u8, 
) {…}

emit_adds_imm ¶
Source

emit_adds_imm :: emit_adds_imm_r_r_i

emit_adds_imm_r_r_i ¶
Source

emit_adds_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_adds_sr ¶
Source

emit_adds_sr :: emit_adds_sr_r_r_sh

emit_adds_sr_r_r_sh ¶
Source

emit_adds_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_addv ¶
Source

emit_addv :: emit_addv_r_r

emit_addv_r_r ¶
Source

emit_addv_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_adr ¶
Source

emit_adr :: emit_adr_r_l

emit_adr_r_l ¶
Source

emit_adr_r_l :: proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) {…}

emit_adrp ¶
Source

emit_adrp :: emit_adrp_r_l

emit_adrp_r_l ¶
Source

emit_adrp_r_l :: proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) {…}

emit_aesd ¶
Source

emit_aesd :: emit_aesd_r_r

emit_aesd_r_r ¶
Source

emit_aesd_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_aese ¶
Source

emit_aese :: emit_aese_r_r

emit_aese_r_r ¶
Source

emit_aese_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_aesimc ¶
Source

emit_aesimc :: emit_aesimc_r_r

emit_aesimc_r_r ¶
Source

emit_aesimc_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_aesmc ¶
Source

emit_aesmc :: emit_aesmc_r_r

emit_aesmc_r_r ¶
Source

emit_aesmc_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_amx_clr ¶
Source

emit_amx_clr :: emit_amx_clr_none

emit_amx_clr_none ¶
Source

emit_amx_clr_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_amx_extrx ¶
Source

emit_amx_extrx :: emit_amx_extrx_r

emit_amx_extrx_r ¶
Source

emit_amx_extrx_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_extry ¶
Source

emit_amx_extry :: emit_amx_extry_r

emit_amx_extry_r ¶
Source

emit_amx_extry_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_fma16 ¶
Source

emit_amx_fma16 :: emit_amx_fma16_r

emit_amx_fma16_r ¶
Source

emit_amx_fma16_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_fma32 ¶
Source

emit_amx_fma32 :: emit_amx_fma32_r

emit_amx_fma32_r ¶
Source

emit_amx_fma32_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_fma64 ¶
Source

emit_amx_fma64 :: emit_amx_fma64_r

emit_amx_fma64_r ¶
Source

emit_amx_fma64_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_fms16 ¶
Source

emit_amx_fms16 :: emit_amx_fms16_r

emit_amx_fms16_r ¶
Source

emit_amx_fms16_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_fms32 ¶
Source

emit_amx_fms32 :: emit_amx_fms32_r

emit_amx_fms32_r ¶
Source

emit_amx_fms32_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_fms64 ¶
Source

emit_amx_fms64 :: emit_amx_fms64_r

emit_amx_fms64_r ¶
Source

emit_amx_fms64_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_genlut ¶
Source

emit_amx_genlut :: emit_amx_genlut_r

emit_amx_genlut_r ¶
Source

emit_amx_genlut_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_ldx ¶
Source

emit_amx_ldx :: emit_amx_ldx_r

emit_amx_ldx_r ¶
Source

emit_amx_ldx_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_ldy ¶
Source

emit_amx_ldy :: emit_amx_ldy_r

emit_amx_ldy_r ¶
Source

emit_amx_ldy_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_ldz ¶
Source

emit_amx_ldz :: emit_amx_ldz_r

emit_amx_ldz_r ¶
Source

emit_amx_ldz_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_ldzi ¶
Source

emit_amx_ldzi :: emit_amx_ldzi_r

emit_amx_ldzi_r ¶
Source

emit_amx_ldzi_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_mac16 ¶
Source

emit_amx_mac16 :: emit_amx_mac16_r

emit_amx_mac16_r ¶
Source

emit_amx_mac16_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_matfp ¶
Source

emit_amx_matfp :: emit_amx_matfp_r

emit_amx_matfp_r ¶
Source

emit_amx_matfp_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_matint ¶
Source

emit_amx_matint :: emit_amx_matint_r

emit_amx_matint_r ¶
Source

emit_amx_matint_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_set ¶
Source

emit_amx_set :: emit_amx_set_none

emit_amx_set_none ¶
Source

emit_amx_set_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_amx_stx ¶
Source

emit_amx_stx :: emit_amx_stx_r

emit_amx_stx_r ¶
Source

emit_amx_stx_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_sty ¶
Source

emit_amx_sty :: emit_amx_sty_r

emit_amx_sty_r ¶
Source

emit_amx_sty_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_stz ¶
Source

emit_amx_stz :: emit_amx_stz_r

emit_amx_stz_r ¶
Source

emit_amx_stz_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_stzi ¶
Source

emit_amx_stzi :: emit_amx_stzi_r

emit_amx_stzi_r ¶
Source

emit_amx_stzi_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_vecfp ¶
Source

emit_amx_vecfp :: emit_amx_vecfp_r

emit_amx_vecfp_r ¶
Source

emit_amx_vecfp_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_amx_vecint ¶
Source

emit_amx_vecint :: emit_amx_vecint_r

emit_amx_vecint_r ¶
Source

emit_amx_vecint_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_and_imm ¶
Source

emit_and_imm :: emit_and_imm_r_r_i

emit_and_imm_r_r_i ¶
Source

emit_and_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_and_sr ¶
Source

emit_and_sr :: emit_and_sr_r_r_sh

emit_and_sr_r_r_sh ¶
Source

emit_and_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_and_v ¶
Source

emit_and_v :: emit_and_v_r_r_r

emit_and_v_r_r_r ¶
Source

emit_and_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_ands_imm ¶
Source

emit_ands_imm :: emit_ands_imm_r_r_i

emit_ands_imm_r_r_i ¶
Source

emit_ands_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_ands_sr ¶
Source

emit_ands_sr :: emit_ands_sr_r_r_sh

emit_ands_sr_r_r_sh ¶
Source

emit_ands_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_asr_imm ¶
Source

emit_asr_imm :: emit_asr_imm_r_r_i

emit_asr_imm_r_r_i ¶
Source

emit_asr_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_asrv ¶
Source

emit_asrv :: emit_asrv_r_r_r

emit_asrv_r_r_r ¶
Source

emit_asrv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_at_s12e0r ¶
Source

emit_at_s12e0r :: emit_at_s12e0r_r

emit_at_s12e0r_r ¶
Source

emit_at_s12e0r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s12e0w ¶
Source

emit_at_s12e0w :: emit_at_s12e0w_r

emit_at_s12e0w_r ¶
Source

emit_at_s12e0w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s12e1r ¶
Source

emit_at_s12e1r :: emit_at_s12e1r_r

emit_at_s12e1r_r ¶
Source

emit_at_s12e1r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s12e1w ¶
Source

emit_at_s12e1w :: emit_at_s12e1w_r

emit_at_s12e1w_r ¶
Source

emit_at_s12e1w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s1e0r ¶
Source

emit_at_s1e0r :: emit_at_s1e0r_r

emit_at_s1e0r_r ¶
Source

emit_at_s1e0r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s1e0w ¶
Source

emit_at_s1e0w :: emit_at_s1e0w_r

emit_at_s1e0w_r ¶
Source

emit_at_s1e0w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s1e1a ¶
Source

emit_at_s1e1a :: emit_at_s1e1a_r

emit_at_s1e1a_r ¶
Source

emit_at_s1e1a_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s1e1r ¶
Source

emit_at_s1e1r :: emit_at_s1e1r_r

emit_at_s1e1r_r ¶
Source

emit_at_s1e1r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s1e1w ¶
Source

emit_at_s1e1w :: emit_at_s1e1w_r

emit_at_s1e1w_r ¶
Source

emit_at_s1e1w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s1e2r ¶
Source

emit_at_s1e2r :: emit_at_s1e2r_r

emit_at_s1e2r_r ¶
Source

emit_at_s1e2r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s1e2w ¶
Source

emit_at_s1e2w :: emit_at_s1e2w_r

emit_at_s1e2w_r ¶
Source

emit_at_s1e2w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s1e3r ¶
Source

emit_at_s1e3r :: emit_at_s1e3r_r

emit_at_s1e3r_r ¶
Source

emit_at_s1e3r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_at_s1e3w ¶
Source

emit_at_s1e3w :: emit_at_s1e3w_r

emit_at_s1e3w_r ¶
Source

emit_at_s1e3w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_autda ¶
Source

emit_autda :: emit_autda_r_r

emit_autda_r_r ¶
Source

emit_autda_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_autdb ¶
Source

emit_autdb :: emit_autdb_r_r

emit_autdb_r_r ¶
Source

emit_autdb_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_autdza ¶
Source

emit_autdza :: emit_autdza_r

emit_autdza_r ¶
Source

emit_autdza_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_autdzb ¶
Source

emit_autdzb :: emit_autdzb_r

emit_autdzb_r ¶
Source

emit_autdzb_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_autia ¶
Source

emit_autia :: emit_autia_r_r

emit_autia1716 ¶
Source

emit_autia1716 :: emit_autia1716_none

emit_autia1716_none ¶
Source

emit_autia1716_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_autia_r_r ¶
Source

emit_autia_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_autiasp ¶
Source

emit_autiasp :: emit_autiasp_none

emit_autiasp_none ¶
Source

emit_autiasp_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_autib ¶
Source

emit_autib :: emit_autib_r_r

emit_autib1716 ¶
Source

emit_autib1716 :: emit_autib1716_none

emit_autib1716_none ¶
Source

emit_autib1716_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_autib_r_r ¶
Source

emit_autib_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_autibsp ¶
Source

emit_autibsp :: emit_autibsp_none

emit_autibsp_none ¶
Source

emit_autibsp_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_autiza ¶
Source

emit_autiza :: emit_autiza_r

emit_autiza_r ¶
Source

emit_autiza_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_autizb ¶
Source

emit_autizb :: emit_autizb_r

emit_autizb_r ¶
Source

emit_autizb_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_b ¶
Source

emit_b :: emit_b_l

emit_b_cond ¶
Source

emit_b_cond :: emit_b_cond_c_l

emit_b_cond_c_l ¶
Source

emit_b_cond_c_l :: proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) {…}

emit_b_l ¶
Source

emit_b_l :: proc(instructions: ^[dynamic]Instruction, label: u32) {…}

emit_bc_cond ¶
Source

emit_bc_cond :: emit_bc_cond_c_l

emit_bc_cond_c_l ¶
Source

emit_bc_cond_c_l :: proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) {…}

emit_bcax ¶
Source

emit_bcax :: emit_bcax_r_r_r_r

emit_bcax_r_r_r_r ¶
Source

emit_bcax_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_bfcvt ¶
Source

emit_bfcvt :: emit_bfcvt_r_r

emit_bfcvt_r_r ¶
Source

emit_bfcvt_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_bfcvtn ¶
Source

emit_bfcvtn :: emit_bfcvtn_r_r

emit_bfcvtn2 ¶
Source

emit_bfcvtn2 :: emit_bfcvtn2_r_r

emit_bfcvtn2_r_r ¶
Source

emit_bfcvtn2_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_bfcvtn_r_r ¶
Source

emit_bfcvtn_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_bfdot ¶
Source

emit_bfdot :: emit_bfdot_r_r_r

emit_bfdot_r_r_r ¶
Source

emit_bfdot_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_bfmlalb ¶
Source

emit_bfmlalb :: emit_bfmlalb_r_r_r

emit_bfmlalb_r_r_r ¶
Source

emit_bfmlalb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_bfmlalt ¶
Source

emit_bfmlalt :: emit_bfmlalt_r_r_r

emit_bfmlalt_r_r_r ¶
Source

emit_bfmlalt_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_bfmmla ¶
Source

emit_bfmmla :: emit_bfmmla_r_r_r

emit_bfmmla_r_r_r ¶
Source

emit_bfmmla_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_bic_sr ¶
Source

emit_bic_sr :: emit_bic_sr_r_r_sh

emit_bic_sr_r_r_sh ¶
Source

emit_bic_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_bic_v ¶
Source

emit_bic_v :: emit_bic_v_r_r_r

emit_bic_v_r_r_r ¶
Source

emit_bic_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_bics_sr ¶
Source

emit_bics_sr :: emit_bics_sr_r_r_sh

emit_bics_sr_r_r_sh ¶
Source

emit_bics_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_bif ¶
Source

emit_bif :: emit_bif_r_r_r

emit_bif_r_r_r ¶
Source

emit_bif_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_bit ¶
Source

emit_bit :: emit_bit_r_r_r

emit_bit_r_r_r ¶
Source

emit_bit_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_bl ¶
Source

emit_bl :: emit_bl_l

emit_bl_l ¶
Source

emit_bl_l :: proc(instructions: ^[dynamic]Instruction, label: u32) {…}

emit_blr ¶
Source

emit_blr :: emit_blr_r

emit_blr_r ¶
Source

emit_blr_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_blraa ¶
Source

emit_blraa :: emit_blraa_r_r

emit_blraa_r_r ¶
Source

emit_blraa_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_blraaz ¶
Source

emit_blraaz :: emit_blraaz_r

emit_blraaz_r ¶
Source

emit_blraaz_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_blrab ¶
Source

emit_blrab :: emit_blrab_r_r

emit_blrab_r_r ¶
Source

emit_blrab_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_blrabz ¶
Source

emit_blrabz :: emit_blrabz_r

emit_blrabz_r ¶
Source

emit_blrabz_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_br ¶
Source

emit_br :: emit_br_r

emit_br_r ¶
Source

emit_br_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_braa ¶
Source

emit_braa :: emit_braa_r_r

emit_braa_r_r ¶
Source

emit_braa_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_braaz ¶
Source

emit_braaz :: emit_braaz_r

emit_braaz_r ¶
Source

emit_braaz_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_brab ¶
Source

emit_brab :: emit_brab_r_r

emit_brab_r_r ¶
Source

emit_brab_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_brabz ¶
Source

emit_brabz :: emit_brabz_r

emit_brabz_r ¶
Source

emit_brabz_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_brk ¶
Source

emit_brk :: emit_brk_i

emit_brk_i ¶
Source

emit_brk_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_bsl ¶
Source

emit_bsl :: emit_bsl_r_r_r

emit_bsl_r_r_r ¶
Source

emit_bsl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_bti ¶
Source

emit_bti :: emit_bti_i

emit_bti_c ¶
Source

emit_bti_c :: emit_bti_c_none

emit_bti_c_none ¶
Source

emit_bti_c_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_bti_i ¶
Source

emit_bti_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_bti_j ¶
Source

emit_bti_j :: emit_bti_j_none

emit_bti_j_none ¶
Source

emit_bti_j_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_bti_jc ¶
Source

emit_bti_jc :: emit_bti_jc_none

emit_bti_jc_none ¶
Source

emit_bti_jc_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_cas ¶
Source

emit_cas :: emit_cas_r_r_m

emit_cas_r_r_m ¶
Source

emit_cas_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_casa ¶
Source

emit_casa :: emit_casa_r_r_m

emit_casa_r_r_m ¶
Source

emit_casa_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_casab ¶
Source

emit_casab :: emit_casab_r_r_m

emit_casab_r_r_m ¶
Source

emit_casab_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_casah ¶
Source

emit_casah :: emit_casah_r_r_m

emit_casah_r_r_m ¶
Source

emit_casah_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_casal ¶
Source

emit_casal :: emit_casal_r_r_m

emit_casal_r_r_m ¶
Source

emit_casal_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_casalb ¶
Source

emit_casalb :: emit_casalb_r_r_m

emit_casalb_r_r_m ¶
Source

emit_casalb_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_casalh ¶
Source

emit_casalh :: emit_casalh_r_r_m

emit_casalh_r_r_m ¶
Source

emit_casalh_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_casb ¶
Source

emit_casb :: emit_casb_r_r_m

emit_casb_r_r_m ¶
Source

emit_casb_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_cash ¶
Source

emit_cash :: emit_cash_r_r_m

emit_cash_r_r_m ¶
Source

emit_cash_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_casl ¶
Source

emit_casl :: emit_casl_r_r_m

emit_casl_r_r_m ¶
Source

emit_casl_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_caslb ¶
Source

emit_caslb :: emit_caslb_r_r_m

emit_caslb_r_r_m ¶
Source

emit_caslb_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_caslh ¶
Source

emit_caslh :: emit_caslh_r_r_m

emit_caslh_r_r_m ¶
Source

emit_caslh_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_casp ¶
Source

emit_casp :: emit_casp_r_r_m

emit_casp_r_r_m ¶
Source

emit_casp_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_caspa ¶
Source

emit_caspa :: emit_caspa_r_r_m

emit_caspa_r_r_m ¶
Source

emit_caspa_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_caspal ¶
Source

emit_caspal :: emit_caspal_r_r_m

emit_caspal_r_r_m ¶
Source

emit_caspal_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_caspl ¶
Source

emit_caspl :: emit_caspl_r_r_m

emit_caspl_r_r_m ¶
Source

emit_caspl_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_cbnz ¶
Source

emit_cbnz :: emit_cbnz_r_l

emit_cbnz_r_l ¶
Source

emit_cbnz_r_l :: proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) {…}

emit_cbz ¶
Source

emit_cbz :: emit_cbz_r_l

emit_cbz_r_l ¶
Source

emit_cbz_r_l :: proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) {…}

emit_ccmn_imm ¶
Source

emit_ccmn_imm :: emit_ccmn_imm_r_i_i_c

emit_ccmn_imm_r_i_i_c ¶
Source

emit_ccmn_imm_r_i_i_c :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) {…}

emit_ccmn_reg ¶
Source

emit_ccmn_reg :: emit_ccmn_reg_r_r_i_c

emit_ccmn_reg_r_r_i_c ¶
Source

emit_ccmn_reg_r_r_i_c :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) {…}

emit_ccmp_imm ¶
Source

emit_ccmp_imm :: emit_ccmp_imm_r_i_i_c

emit_ccmp_imm_r_i_i_c ¶
Source

emit_ccmp_imm_r_i_i_c :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) {…}

emit_ccmp_reg ¶
Source

emit_ccmp_reg :: emit_ccmp_reg_r_r_i_c

emit_ccmp_reg_r_r_i_c ¶
Source

emit_ccmp_reg_r_r_i_c :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) {…}

emit_cls ¶
Source

emit_cls :: emit_cls_r_r

emit_cls_r_r ¶
Source

emit_cls_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_cls_v ¶
Source

emit_cls_v :: emit_cls_v_r_r

emit_cls_v_r_r ¶
Source

emit_cls_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_clz ¶
Source

emit_clz :: emit_clz_r_r

emit_clz_r_r ¶
Source

emit_clz_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_clz_v ¶
Source

emit_clz_v :: emit_clz_v_r_r

emit_clz_v_r_r ¶
Source

emit_clz_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_cmeq ¶
Source

emit_cmeq :: emit_cmeq_r_r_r

emit_cmeq_r_r_r ¶
Source

emit_cmeq_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_cmge ¶
Source

emit_cmge :: emit_cmge_r_r_r

emit_cmge_r_r_r ¶
Source

emit_cmge_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_cmgt ¶
Source

emit_cmgt :: emit_cmgt_r_r_r

emit_cmgt_r_r_r ¶
Source

emit_cmgt_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_cmhi ¶
Source

emit_cmhi :: emit_cmhi_r_r_r

emit_cmhi_r_r_r ¶
Source

emit_cmhi_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_cmhs ¶
Source

emit_cmhs :: emit_cmhs_r_r_r

emit_cmhs_r_r_r ¶
Source

emit_cmhs_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_cmle ¶
Source

emit_cmle :: emit_cmle_r_r

emit_cmle_r_r ¶
Source

emit_cmle_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_cmlt ¶
Source

emit_cmlt :: emit_cmlt_r_r

emit_cmlt_r_r ¶
Source

emit_cmlt_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_cmn_er ¶
Source

emit_cmn_er :: emit_cmn_er_r_ex

emit_cmn_er_r_ex ¶
Source

emit_cmn_er_r_ex :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) {…}

emit_cmn_imm ¶
Source

emit_cmn_imm :: emit_cmn_imm_r_i

emit_cmn_imm_r_i ¶
Source

emit_cmn_imm_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

emit_cmn_sr ¶
Source

emit_cmn_sr :: emit_cmn_sr_r_sh

emit_cmn_sr_r_sh ¶
Source

emit_cmn_sr_r_sh :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) {…}

emit_cmp_er ¶
Source

emit_cmp_er :: emit_cmp_er_r_ex

emit_cmp_er_r_ex ¶
Source

emit_cmp_er_r_ex :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) {…}

emit_cmp_imm ¶
Source

emit_cmp_imm :: emit_cmp_imm_r_i

emit_cmp_imm_r_i ¶
Source

emit_cmp_imm_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

emit_cmp_sr ¶
Source

emit_cmp_sr :: emit_cmp_sr_r_sh

emit_cmp_sr_r_sh ¶
Source

emit_cmp_sr_r_sh :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) {…}

emit_cmtst ¶
Source

emit_cmtst :: emit_cmtst_r_r_r

emit_cmtst_r_r_r ¶
Source

emit_cmtst_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_cnt ¶
Source

emit_cnt :: emit_cnt_r_r

emit_cnt_r_r ¶
Source

emit_cnt_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_cpye ¶
Source

emit_cpye :: emit_cpye_r_r_r

emit_cpye_r_r_r ¶
Source

emit_cpye_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_cpyfe ¶
Source

emit_cpyfe :: emit_cpyfe_r_r_r

emit_cpyfe_r_r_r ¶
Source

emit_cpyfe_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_cpyfm ¶
Source

emit_cpyfm :: emit_cpyfm_r_r_r

emit_cpyfm_r_r_r ¶
Source

emit_cpyfm_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_cpyfp ¶
Source

emit_cpyfp :: emit_cpyfp_r_r_r

emit_cpyfp_r_r_r ¶
Source

emit_cpyfp_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_cpym ¶
Source

emit_cpym :: emit_cpym_r_r_r

emit_cpym_r_r_r ¶
Source

emit_cpym_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_cpyp ¶
Source

emit_cpyp :: emit_cpyp_r_r_r

emit_cpyp_r_r_r ¶
Source

emit_cpyp_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_crc32b ¶
Source

emit_crc32b :: emit_crc32b_r_r_r

emit_crc32b_r_r_r ¶
Source

emit_crc32b_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_crc32cb ¶
Source

emit_crc32cb :: emit_crc32cb_r_r_r

emit_crc32cb_r_r_r ¶
Source

emit_crc32cb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_crc32ch ¶
Source

emit_crc32ch :: emit_crc32ch_r_r_r

emit_crc32ch_r_r_r ¶
Source

emit_crc32ch_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_crc32cw ¶
Source

emit_crc32cw :: emit_crc32cw_r_r_r

emit_crc32cw_r_r_r ¶
Source

emit_crc32cw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_crc32cx ¶
Source

emit_crc32cx :: emit_crc32cx_r_r_r

emit_crc32cx_r_r_r ¶
Source

emit_crc32cx_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_crc32h ¶
Source

emit_crc32h :: emit_crc32h_r_r_r

emit_crc32h_r_r_r ¶
Source

emit_crc32h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_crc32w ¶
Source

emit_crc32w :: emit_crc32w_r_r_r

emit_crc32w_r_r_r ¶
Source

emit_crc32w_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_crc32x ¶
Source

emit_crc32x :: emit_crc32x_r_r_r

emit_crc32x_r_r_r ¶
Source

emit_crc32x_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_csdb ¶
Source

emit_csdb :: emit_csdb_none

emit_csdb_none ¶
Source

emit_csdb_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_csel ¶
Source

emit_csel :: emit_csel_r_r_r_c

emit_csel_r_r_r_c ¶
Source

emit_csel_r_r_r_c :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) {…}

emit_csinc ¶
Source

emit_csinc :: emit_csinc_r_r_r_c

emit_csinc_r_r_r_c ¶
Source

emit_csinc_r_r_r_c :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) {…}

emit_csinv ¶
Source

emit_csinv :: emit_csinv_r_r_r_c

emit_csinv_r_r_r_c ¶
Source

emit_csinv_r_r_r_c :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) {…}

emit_csneg ¶
Source

emit_csneg :: emit_csneg_r_r_r_c

emit_csneg_r_r_r_c ¶
Source

emit_csneg_r_r_r_c :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) {…}

emit_dc_cigdpapa ¶
Source

emit_dc_cigdpapa :: emit_dc_cigdpapa_r

emit_dc_cigdpapa_r ¶
Source

emit_dc_cigdpapa_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_dc_cipapa ¶
Source

emit_dc_cipapa :: emit_dc_cipapa_r

emit_dc_cipapa_r ¶
Source

emit_dc_cipapa_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_dc_cisw ¶
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emit_dc_cisw :: emit_dc_cisw_r

emit_dc_cisw_r ¶
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emit_dc_cisw_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_dc_civac ¶
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emit_dc_civac :: emit_dc_civac_r

emit_dc_civac_r ¶
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emit_dc_civac_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_dc_csw ¶
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emit_dc_csw :: emit_dc_csw_r

emit_dc_csw_r ¶
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emit_dc_csw_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_dc_cvac ¶
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emit_dc_cvac :: emit_dc_cvac_r

emit_dc_cvac_r ¶
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emit_dc_cvac_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_dc_cvau ¶
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emit_dc_cvau :: emit_dc_cvau_r

emit_dc_cvau_r ¶
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emit_dc_cvau_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_dc_isw ¶
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emit_dc_isw :: emit_dc_isw_r

emit_dc_isw_r ¶
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emit_dc_isw_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_dc_ivac ¶
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emit_dc_ivac :: emit_dc_ivac_r

emit_dc_ivac_r ¶
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emit_dc_ivac_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_dc_zva ¶
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emit_dc_zva :: emit_dc_zva_r

emit_dc_zva_r ¶
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emit_dc_zva_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_dgh ¶
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emit_dgh :: emit_dgh_none

emit_dgh_none ¶
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emit_dgh_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_dmb ¶
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emit_dmb :: emit_dmb_i

emit_dmb_i ¶
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emit_dmb_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_dsb ¶
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emit_dsb :: emit_dsb_i

emit_dsb_i ¶
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emit_dsb_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_dup_v_r_r ¶
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emit_dup_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

Related Procedure Groups

emit_dup_v

emit_dup_v_r_r_i ¶
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emit_dup_v_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

Related Procedure Groups

emit_dup_v

emit_eon_sr ¶
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emit_eon_sr :: emit_eon_sr_r_r_sh

emit_eon_sr_r_r_sh ¶
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emit_eon_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_eor3 ¶
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emit_eor3 :: emit_eor3_r_r_r_r

emit_eor3_r_r_r_r ¶
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emit_eor3_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_eor_imm ¶
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emit_eor_imm :: emit_eor_imm_r_r_i

emit_eor_imm_r_r_i ¶
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emit_eor_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_eor_sr ¶
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emit_eor_sr :: emit_eor_sr_r_r_sh

emit_eor_sr_r_r_sh ¶
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emit_eor_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_eor_v ¶
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emit_eor_v :: emit_eor_v_r_r_r

emit_eor_v_r_r_r ¶
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emit_eor_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_eret ¶
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emit_eret :: emit_eret_none

emit_eret_none ¶
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emit_eret_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_eretaa ¶
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emit_eretaa :: emit_eretaa_none

emit_eretaa_none ¶
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emit_eretaa_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_eretab ¶
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emit_eretab :: emit_eretab_none

emit_eretab_none ¶
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emit_eretab_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_ext_v ¶
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emit_ext_v :: emit_ext_v_r_r_r_i

emit_ext_v_r_r_r_i ¶
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emit_ext_v_r_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) {…}

emit_extr ¶
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emit_extr :: emit_extr_r_r_r_i

emit_extr_r_r_r_i ¶
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emit_extr_r_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) {…}

emit_fabs ¶
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emit_fabs :: emit_fabs_r_r

emit_fabs_h ¶
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emit_fabs_h :: emit_fabs_h_r_r

emit_fabs_h_r_r ¶
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emit_fabs_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fabs_r_r ¶
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emit_fabs_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fabs_v ¶
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emit_fabs_v :: emit_fabs_v_r_r

emit_fabs_v_r_r ¶
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emit_fabs_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_facge ¶
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emit_facge :: emit_facge_r_r_r

emit_facge_r_r_r ¶
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emit_facge_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_facgt ¶
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emit_facgt :: emit_facgt_r_r_r

emit_facgt_r_r_r ¶
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emit_facgt_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fadd ¶
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emit_fadd :: emit_fadd_r_r_r

emit_fadd_h ¶
Source

emit_fadd_h :: emit_fadd_h_r_r_r

emit_fadd_h_r_r_r ¶
Source

emit_fadd_h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fadd_r_r_r ¶
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emit_fadd_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fadd_v ¶
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emit_fadd_v :: emit_fadd_v_r_r_r

emit_fadd_v_r_r_r ¶
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emit_fadd_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_faddp_v ¶
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emit_faddp_v :: emit_faddp_v_r_r_r

emit_faddp_v_r_r_r ¶
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emit_faddp_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fcadd_2d ¶
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emit_fcadd_2d :: emit_fcadd_2d_r_r_r_i

emit_fcadd_2d_r_r_r_i ¶
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emit_fcadd_2d_r_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) {…}

emit_fcadd_4h ¶
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emit_fcadd_4h :: emit_fcadd_4h_r_r_r_i

emit_fcadd_4h_r_r_r_i ¶
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emit_fcadd_4h_r_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) {…}

emit_fcadd_4s ¶
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emit_fcadd_4s :: emit_fcadd_4s_r_r_r_i

emit_fcadd_4s_r_r_r_i ¶
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emit_fcadd_4s_r_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) {…}

emit_fcadd_8h ¶
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emit_fcadd_8h :: emit_fcadd_8h_r_r_r_i

emit_fcadd_8h_r_r_r_i ¶
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emit_fcadd_8h_r_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) {…}

emit_fcmeq ¶
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emit_fcmeq :: emit_fcmeq_r_r_r

emit_fcmeq_r_r_r ¶
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emit_fcmeq_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fcmge ¶
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emit_fcmge :: emit_fcmge_r_r_r

emit_fcmge_r_r_r ¶
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emit_fcmge_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fcmgt ¶
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emit_fcmgt :: emit_fcmgt_r_r_r

emit_fcmgt_r_r_r ¶
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emit_fcmgt_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fcmla_2d ¶
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emit_fcmla_2d :: emit_fcmla_2d_r_r_r_i

emit_fcmla_2d_r_r_r_i ¶
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emit_fcmla_2d_r_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) {…}

emit_fcmla_4h ¶
Source

emit_fcmla_4h :: emit_fcmla_4h_r_r_r_i

emit_fcmla_4h_r_r_r_i ¶
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emit_fcmla_4h_r_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) {…}

emit_fcmla_4s ¶
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emit_fcmla_4s :: emit_fcmla_4s_r_r_r_i

emit_fcmla_4s_r_r_r_i ¶
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emit_fcmla_4s_r_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) {…}

emit_fcmla_8h ¶
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emit_fcmla_8h :: emit_fcmla_8h_r_r_r_i

emit_fcmla_8h_r_r_r_i ¶
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emit_fcmla_8h_r_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) {…}

emit_fcmle ¶
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emit_fcmle :: emit_fcmle_r_r

emit_fcmle_r_r ¶
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emit_fcmle_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcmlt ¶
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emit_fcmlt :: emit_fcmlt_r_r

emit_fcmlt_r_r ¶
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emit_fcmlt_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcmp ¶
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emit_fcmp :: emit_fcmp_r_r

emit_fcmp_h ¶
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emit_fcmp_h :: emit_fcmp_h_r_r

emit_fcmp_h_r_r ¶
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emit_fcmp_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcmp_r_r ¶
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emit_fcmp_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcmpe ¶
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emit_fcmpe :: emit_fcmpe_r_r

emit_fcmpe_h ¶
Source

emit_fcmpe_h :: emit_fcmpe_h_r_r

emit_fcmpe_h_r_r ¶
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emit_fcmpe_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcmpe_r_r ¶
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emit_fcmpe_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcsel ¶
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emit_fcsel :: emit_fcsel_r_r_r_c

emit_fcsel_h ¶
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emit_fcsel_h :: emit_fcsel_h_r_r_r_c

emit_fcsel_h_r_r_r_c ¶
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emit_fcsel_h_r_r_r_c :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) {…}

emit_fcsel_r_r_r_c ¶
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emit_fcsel_r_r_r_c :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) {…}

emit_fcvt ¶
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emit_fcvt :: emit_fcvt_r_r

emit_fcvt_d_h ¶
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emit_fcvt_d_h :: emit_fcvt_d_h_r_r

emit_fcvt_d_h_r_r ¶
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emit_fcvt_d_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvt_h_d ¶
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emit_fcvt_h_d :: emit_fcvt_h_d_r_r

emit_fcvt_h_d_r_r ¶
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emit_fcvt_h_d_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvt_h_s ¶
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emit_fcvt_h_s :: emit_fcvt_h_s_r_r

emit_fcvt_h_s_r_r ¶
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emit_fcvt_h_s_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvt_r_r ¶
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emit_fcvt_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvt_s_h ¶
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emit_fcvt_s_h :: emit_fcvt_s_h_r_r

emit_fcvt_s_h_r_r ¶
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emit_fcvt_s_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtas ¶
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emit_fcvtas :: emit_fcvtas_r_r

emit_fcvtas_r_r ¶
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emit_fcvtas_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtas_v ¶
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emit_fcvtas_v :: emit_fcvtas_v_r_r

emit_fcvtas_v_r_r ¶
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emit_fcvtas_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtau ¶
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emit_fcvtau :: emit_fcvtau_r_r

emit_fcvtau_r_r ¶
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emit_fcvtau_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtau_v ¶
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emit_fcvtau_v :: emit_fcvtau_v_r_r

emit_fcvtau_v_r_r ¶
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emit_fcvtau_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtl ¶
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emit_fcvtl :: emit_fcvtl_r_r

emit_fcvtl2 ¶
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emit_fcvtl2 :: emit_fcvtl2_r_r

emit_fcvtl2_r_r ¶
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emit_fcvtl2_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtl_r_r ¶
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emit_fcvtl_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtms ¶
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emit_fcvtms :: emit_fcvtms_r_r

emit_fcvtms_r_r ¶
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emit_fcvtms_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtms_v ¶
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emit_fcvtms_v :: emit_fcvtms_v_r_r

emit_fcvtms_v_r_r ¶
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emit_fcvtms_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtmu ¶
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emit_fcvtmu :: emit_fcvtmu_r_r

emit_fcvtmu_r_r ¶
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emit_fcvtmu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtmu_v ¶
Source

emit_fcvtmu_v :: emit_fcvtmu_v_r_r

emit_fcvtmu_v_r_r ¶
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emit_fcvtmu_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtn ¶
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emit_fcvtn :: emit_fcvtn_r_r

emit_fcvtn2 ¶
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emit_fcvtn2 :: emit_fcvtn2_r_r

emit_fcvtn2_r_r ¶
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emit_fcvtn2_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtn_r_r ¶
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emit_fcvtn_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtns ¶
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emit_fcvtns :: emit_fcvtns_r_r

emit_fcvtns_r_r ¶
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emit_fcvtns_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtns_v ¶
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emit_fcvtns_v :: emit_fcvtns_v_r_r

emit_fcvtns_v_r_r ¶
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emit_fcvtns_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtnu ¶
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emit_fcvtnu :: emit_fcvtnu_r_r

emit_fcvtnu_r_r ¶
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emit_fcvtnu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtnu_v ¶
Source

emit_fcvtnu_v :: emit_fcvtnu_v_r_r

emit_fcvtnu_v_r_r ¶
Source

emit_fcvtnu_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtps ¶
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emit_fcvtps :: emit_fcvtps_r_r

emit_fcvtps_r_r ¶
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emit_fcvtps_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtps_v ¶
Source

emit_fcvtps_v :: emit_fcvtps_v_r_r

emit_fcvtps_v_r_r ¶
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emit_fcvtps_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtpu ¶
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emit_fcvtpu :: emit_fcvtpu_r_r

emit_fcvtpu_r_r ¶
Source

emit_fcvtpu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtpu_v ¶
Source

emit_fcvtpu_v :: emit_fcvtpu_v_r_r

emit_fcvtpu_v_r_r ¶
Source

emit_fcvtpu_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtxn ¶
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emit_fcvtxn :: emit_fcvtxn_r_r

emit_fcvtxn2 ¶
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emit_fcvtxn2 :: emit_fcvtxn2_r_r

emit_fcvtxn2_r_r ¶
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emit_fcvtxn2_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtxn_r_r ¶
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emit_fcvtxn_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtzs ¶
Source

emit_fcvtzs :: emit_fcvtzs_r_r

emit_fcvtzs_h ¶
Source

emit_fcvtzs_h :: emit_fcvtzs_h_r_r

emit_fcvtzs_h_r_r ¶
Source

emit_fcvtzs_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtzs_r_r ¶
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emit_fcvtzs_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtzs_v ¶
Source

emit_fcvtzs_v :: emit_fcvtzs_v_r_r

emit_fcvtzs_v_r_r ¶
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emit_fcvtzs_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtzu ¶
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emit_fcvtzu :: emit_fcvtzu_r_r

emit_fcvtzu_h ¶
Source

emit_fcvtzu_h :: emit_fcvtzu_h_r_r

emit_fcvtzu_h_r_r ¶
Source

emit_fcvtzu_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtzu_r_r ¶
Source

emit_fcvtzu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fcvtzu_v ¶
Source

emit_fcvtzu_v :: emit_fcvtzu_v_r_r

emit_fcvtzu_v_r_r ¶
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emit_fcvtzu_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fdiv ¶
Source

emit_fdiv :: emit_fdiv_r_r_r

emit_fdiv_h ¶
Source

emit_fdiv_h :: emit_fdiv_h_r_r_r

emit_fdiv_h_r_r_r ¶
Source

emit_fdiv_h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fdiv_r_r_r ¶
Source

emit_fdiv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fdiv_v ¶
Source

emit_fdiv_v :: emit_fdiv_v_r_r_r

emit_fdiv_v_r_r_r ¶
Source

emit_fdiv_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmadd ¶
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emit_fmadd :: emit_fmadd_r_r_r_r

emit_fmadd_h ¶
Source

emit_fmadd_h :: emit_fmadd_h_r_r_r_r

emit_fmadd_h_r_r_r_r ¶
Source

emit_fmadd_h_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_fmadd_r_r_r_r ¶
Source

emit_fmadd_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_fmax ¶
Source

emit_fmax :: emit_fmax_r_r_r

emit_fmax_h ¶
Source

emit_fmax_h :: emit_fmax_h_r_r_r

emit_fmax_h_r_r_r ¶
Source

emit_fmax_h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmax_r_r_r ¶
Source

emit_fmax_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmax_v ¶
Source

emit_fmax_v :: emit_fmax_v_r_r_r

emit_fmax_v_r_r_r ¶
Source

emit_fmax_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmaxnm ¶
Source

emit_fmaxnm :: emit_fmaxnm_r_r_r

emit_fmaxnm_h ¶
Source

emit_fmaxnm_h :: emit_fmaxnm_h_r_r_r

emit_fmaxnm_h_r_r_r ¶
Source

emit_fmaxnm_h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmaxnm_r_r_r ¶
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emit_fmaxnm_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmaxnm_v ¶
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emit_fmaxnm_v :: emit_fmaxnm_v_r_r_r

emit_fmaxnm_v_r_r_r ¶
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emit_fmaxnm_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmaxnmp ¶
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emit_fmaxnmp :: emit_fmaxnmp_r_r_r

emit_fmaxnmp_r_r_r ¶
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emit_fmaxnmp_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmaxnmv ¶
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emit_fmaxnmv :: emit_fmaxnmv_r_r

emit_fmaxnmv_r_r ¶
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emit_fmaxnmv_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fmaxp_v ¶
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emit_fmaxp_v :: emit_fmaxp_v_r_r_r

emit_fmaxp_v_r_r_r ¶
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emit_fmaxp_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmaxv_v ¶
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emit_fmaxv_v :: emit_fmaxv_v_r_r

emit_fmaxv_v_r_r ¶
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emit_fmaxv_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fmin ¶
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emit_fmin :: emit_fmin_r_r_r

emit_fmin_h ¶
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emit_fmin_h :: emit_fmin_h_r_r_r

emit_fmin_h_r_r_r ¶
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emit_fmin_h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmin_r_r_r ¶
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emit_fmin_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmin_v ¶
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emit_fmin_v :: emit_fmin_v_r_r_r

emit_fmin_v_r_r_r ¶
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emit_fmin_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fminnm ¶
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emit_fminnm :: emit_fminnm_r_r_r

emit_fminnm_h ¶
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emit_fminnm_h :: emit_fminnm_h_r_r_r

emit_fminnm_h_r_r_r ¶
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emit_fminnm_h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fminnm_r_r_r ¶
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emit_fminnm_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fminnm_v ¶
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emit_fminnm_v :: emit_fminnm_v_r_r_r

emit_fminnm_v_r_r_r ¶
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emit_fminnm_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fminnmp ¶
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emit_fminnmp :: emit_fminnmp_r_r_r

emit_fminnmp_r_r_r ¶
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emit_fminnmp_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fminnmv ¶
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emit_fminnmv :: emit_fminnmv_r_r

emit_fminnmv_r_r ¶
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emit_fminnmv_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fminp_v ¶
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emit_fminp_v :: emit_fminp_v_r_r_r

emit_fminp_v_r_r_r ¶
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emit_fminp_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fminv_v ¶
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emit_fminv_v :: emit_fminv_v_r_r

emit_fminv_v_r_r ¶
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emit_fminv_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fmla_v ¶
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emit_fmla_v :: emit_fmla_v_r_r_r

emit_fmla_v_r_r_r ¶
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emit_fmla_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmls_v ¶
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emit_fmls_v :: emit_fmls_v_r_r_r

emit_fmls_v_r_r_r ¶
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emit_fmls_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmov_gen ¶
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emit_fmov_gen :: emit_fmov_gen_r_r

emit_fmov_gen_r_r ¶
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emit_fmov_gen_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fmov_h ¶
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emit_fmov_h :: emit_fmov_h_r_r

emit_fmov_h_r_r ¶
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emit_fmov_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fmov_imm ¶
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emit_fmov_imm :: emit_fmov_imm_r_i

emit_fmov_imm_r_i ¶
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emit_fmov_imm_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

emit_fmov_reg ¶
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emit_fmov_reg :: emit_fmov_reg_r_r

emit_fmov_reg_r_r ¶
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emit_fmov_reg_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fmov_v_imm ¶
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emit_fmov_v_imm :: emit_fmov_v_imm_r_i

emit_fmov_v_imm_r_i ¶
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emit_fmov_v_imm_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

emit_fmsub ¶
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emit_fmsub :: emit_fmsub_r_r_r_r

emit_fmsub_h ¶
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emit_fmsub_h :: emit_fmsub_h_r_r_r_r

emit_fmsub_h_r_r_r_r ¶
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emit_fmsub_h_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_fmsub_r_r_r_r ¶
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emit_fmsub_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_fmul ¶
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emit_fmul :: emit_fmul_r_r_r

emit_fmul_h ¶
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emit_fmul_h :: emit_fmul_h_r_r_r

emit_fmul_h_r_r_r ¶
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emit_fmul_h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmul_r_r_r ¶
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emit_fmul_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmul_v ¶
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emit_fmul_v :: emit_fmul_v_r_r_r

emit_fmul_v_r_r_r ¶
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emit_fmul_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fmulx ¶
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emit_fmulx :: emit_fmulx_r_r_r

emit_fmulx_r_r_r ¶
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emit_fmulx_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fneg ¶
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emit_fneg :: emit_fneg_r_r

emit_fneg_h ¶
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emit_fneg_h :: emit_fneg_h_r_r

emit_fneg_h_r_r ¶
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emit_fneg_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fneg_r_r ¶
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emit_fneg_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fneg_v ¶
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emit_fneg_v :: emit_fneg_v_r_r

emit_fneg_v_r_r ¶
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emit_fneg_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fnmadd ¶
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emit_fnmadd :: emit_fnmadd_r_r_r_r

emit_fnmadd_h ¶
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emit_fnmadd_h :: emit_fnmadd_h_r_r_r_r

emit_fnmadd_h_r_r_r_r ¶
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emit_fnmadd_h_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_fnmadd_r_r_r_r ¶
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emit_fnmadd_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_fnmsub ¶
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emit_fnmsub :: emit_fnmsub_r_r_r_r

emit_fnmsub_h ¶
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emit_fnmsub_h :: emit_fnmsub_h_r_r_r_r

emit_fnmsub_h_r_r_r_r ¶
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emit_fnmsub_h_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_fnmsub_r_r_r_r ¶
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emit_fnmsub_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_fnmul ¶
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emit_fnmul :: emit_fnmul_r_r_r

emit_fnmul_h ¶
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emit_fnmul_h :: emit_fnmul_h_r_r_r

emit_fnmul_h_r_r_r ¶
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emit_fnmul_h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fnmul_r_r_r ¶
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emit_fnmul_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_frecpe ¶
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emit_frecpe :: emit_frecpe_r_r

emit_frecpe_r_r ¶
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emit_frecpe_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frecps ¶
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emit_frecps :: emit_frecps_r_r_r

emit_frecps_r_r_r ¶
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emit_frecps_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_frecpx ¶
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emit_frecpx :: emit_frecpx_r_r

emit_frecpx_r_r ¶
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emit_frecpx_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frinta ¶
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emit_frinta :: emit_frinta_r_r

emit_frinta_r_r ¶
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emit_frinta_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frinta_v ¶
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emit_frinta_v :: emit_frinta_v_r_r

emit_frinta_v_r_r ¶
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emit_frinta_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frinti ¶
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emit_frinti :: emit_frinti_r_r

emit_frinti_r_r ¶
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emit_frinti_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frinti_v ¶
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emit_frinti_v :: emit_frinti_v_r_r

emit_frinti_v_r_r ¶
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emit_frinti_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frintm ¶
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emit_frintm :: emit_frintm_r_r

emit_frintm_r_r ¶
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emit_frintm_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frintm_v ¶
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emit_frintm_v :: emit_frintm_v_r_r

emit_frintm_v_r_r ¶
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emit_frintm_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frintn ¶
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emit_frintn :: emit_frintn_r_r

emit_frintn_r_r ¶
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emit_frintn_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frintn_v ¶
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emit_frintn_v :: emit_frintn_v_r_r

emit_frintn_v_r_r ¶
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emit_frintn_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frintp ¶
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emit_frintp :: emit_frintp_r_r

emit_frintp_r_r ¶
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emit_frintp_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frintp_v ¶
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emit_frintp_v :: emit_frintp_v_r_r

emit_frintp_v_r_r ¶
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emit_frintp_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frintx ¶
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emit_frintx :: emit_frintx_r_r

emit_frintx_r_r ¶
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emit_frintx_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frintx_v ¶
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emit_frintx_v :: emit_frintx_v_r_r

emit_frintx_v_r_r ¶
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emit_frintx_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frintz ¶
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emit_frintz :: emit_frintz_r_r

emit_frintz_r_r ¶
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emit_frintz_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frintz_v ¶
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emit_frintz_v :: emit_frintz_v_r_r

emit_frintz_v_r_r ¶
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emit_frintz_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frsqrte ¶
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emit_frsqrte :: emit_frsqrte_r_r

emit_frsqrte_r_r ¶
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emit_frsqrte_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_frsqrts ¶
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emit_frsqrts :: emit_frsqrts_r_r_r

emit_frsqrts_r_r_r ¶
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emit_frsqrts_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fsqrt ¶
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emit_fsqrt :: emit_fsqrt_r_r

emit_fsqrt_h ¶
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emit_fsqrt_h :: emit_fsqrt_h_r_r

emit_fsqrt_h_r_r ¶
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emit_fsqrt_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fsqrt_r_r ¶
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emit_fsqrt_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fsqrt_v ¶
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emit_fsqrt_v :: emit_fsqrt_v_r_r

emit_fsqrt_v_r_r ¶
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emit_fsqrt_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_fsub ¶
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emit_fsub :: emit_fsub_r_r_r

emit_fsub_h ¶
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emit_fsub_h :: emit_fsub_h_r_r_r

emit_fsub_h_r_r_r ¶
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emit_fsub_h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fsub_r_r_r ¶
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emit_fsub_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_fsub_v ¶
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emit_fsub_v :: emit_fsub_v_r_r_r

emit_fsub_v_r_r_r ¶
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emit_fsub_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_gmi ¶
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emit_gmi :: emit_gmi_r_r_r

emit_gmi_r_r_r ¶
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emit_gmi_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_hint ¶
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emit_hint :: emit_hint_i

emit_hint_i ¶
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emit_hint_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_hlt ¶
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emit_hlt :: emit_hlt_i

emit_hlt_i ¶
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emit_hlt_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_hvc ¶
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emit_hvc :: emit_hvc_i

emit_hvc_i ¶
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emit_hvc_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_ic_iallu ¶
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emit_ic_iallu :: emit_ic_iallu_none

emit_ic_iallu_none ¶
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emit_ic_iallu_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_ic_ialluis ¶
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emit_ic_ialluis :: emit_ic_ialluis_none

emit_ic_ialluis_none ¶
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emit_ic_ialluis_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_ic_ivau ¶
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emit_ic_ivau :: emit_ic_ivau_r

emit_ic_ivau_r ¶
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emit_ic_ivau_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_ins_r_i_r ¶
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emit_ins_r_i_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) {…}

Related Procedure Groups

emit_ins

emit_ins_r_i_r_i ¶
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emit_ins_r_i_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) {…}

Related Procedure Groups

emit_ins

emit_irg ¶
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emit_irg :: emit_irg_r_r_r

emit_irg_r_r_r ¶
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emit_irg_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_isb ¶
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emit_isb :: emit_isb_i

emit_isb_i ¶
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emit_isb_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_ld1 ¶
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emit_ld1 :: emit_ld1_r_m

emit_ld1_lane ¶
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emit_ld1_lane :: emit_ld1_lane_r_i_m

emit_ld1_lane_r_i_m ¶
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emit_ld1_lane_r_i_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) {…}

emit_ld1_r_m ¶
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emit_ld1_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ld1r ¶
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emit_ld1r :: emit_ld1r_r_m

emit_ld1r_r_m ¶
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emit_ld1r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ld2 ¶
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emit_ld2 :: emit_ld2_r_m

emit_ld2_lane ¶
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emit_ld2_lane :: emit_ld2_lane_r_i_m

emit_ld2_lane_r_i_m ¶
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emit_ld2_lane_r_i_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) {…}

emit_ld2_r_m ¶
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emit_ld2_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ld2r ¶
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emit_ld2r :: emit_ld2r_r_m

emit_ld2r_r_m ¶
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emit_ld2r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ld3 ¶
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emit_ld3 :: emit_ld3_r_m

emit_ld3_lane ¶
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emit_ld3_lane :: emit_ld3_lane_r_i_m

emit_ld3_lane_r_i_m ¶
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emit_ld3_lane_r_i_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) {…}

emit_ld3_r_m ¶
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emit_ld3_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ld3r ¶
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emit_ld3r :: emit_ld3r_r_m

emit_ld3r_r_m ¶
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emit_ld3r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ld4 ¶
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emit_ld4 :: emit_ld4_r_m

emit_ld4_lane ¶
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emit_ld4_lane :: emit_ld4_lane_r_i_m

emit_ld4_lane_r_i_m ¶
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emit_ld4_lane_r_i_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) {…}

emit_ld4_r_m ¶
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emit_ld4_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ld4r ¶
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emit_ld4r :: emit_ld4r_r_m

emit_ld4r_r_m ¶
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emit_ld4r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldadd ¶
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emit_ldadd :: emit_ldadd_r_r_m

emit_ldadd_r_r_m ¶
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emit_ldadd_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldadda ¶
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emit_ldadda :: emit_ldadda_r_r_m

emit_ldadda_r_r_m ¶
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emit_ldadda_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldaddal ¶
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emit_ldaddal :: emit_ldaddal_r_r_m

emit_ldaddal_r_r_m ¶
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emit_ldaddal_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldaddl ¶
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emit_ldaddl :: emit_ldaddl_r_r_m

emit_ldaddl_r_r_m ¶
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emit_ldaddl_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldapr ¶
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emit_ldapr :: emit_ldapr_r_m

emit_ldapr_r_m ¶
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emit_ldapr_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldaprb ¶
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emit_ldaprb :: emit_ldaprb_r_m

emit_ldaprb_r_m ¶
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emit_ldaprb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldaprh ¶
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emit_ldaprh :: emit_ldaprh_r_m

emit_ldaprh_r_m ¶
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emit_ldaprh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldapur ¶
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emit_ldapur :: emit_ldapur_r_m

emit_ldapur_r_m ¶
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emit_ldapur_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldapurb ¶
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emit_ldapurb :: emit_ldapurb_r_m

emit_ldapurb_r_m ¶
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emit_ldapurb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldapurh ¶
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emit_ldapurh :: emit_ldapurh_r_m

emit_ldapurh_r_m ¶
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emit_ldapurh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldapursb ¶
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emit_ldapursb :: emit_ldapursb_r_m

emit_ldapursb_r_m ¶
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emit_ldapursb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldapursh ¶
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emit_ldapursh :: emit_ldapursh_r_m

emit_ldapursh_r_m ¶
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emit_ldapursh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldapursw ¶
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emit_ldapursw :: emit_ldapursw_r_m

emit_ldapursw_r_m ¶
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emit_ldapursw_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldar ¶
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emit_ldar :: emit_ldar_r_m

emit_ldar_r_m ¶
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emit_ldar_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldarb ¶
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emit_ldarb :: emit_ldarb_r_m

emit_ldarb_r_m ¶
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emit_ldarb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldarh ¶
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emit_ldarh :: emit_ldarh_r_m

emit_ldarh_r_m ¶
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emit_ldarh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldaxp ¶
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emit_ldaxp :: emit_ldaxp_r_r_m

emit_ldaxp_r_r_m ¶
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emit_ldaxp_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldaxr ¶
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emit_ldaxr :: emit_ldaxr_r_m

emit_ldaxr_r_m ¶
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emit_ldaxr_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldaxrb ¶
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emit_ldaxrb :: emit_ldaxrb_r_m

emit_ldaxrb_r_m ¶
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emit_ldaxrb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldaxrh ¶
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emit_ldaxrh :: emit_ldaxrh_r_m

emit_ldaxrh_r_m ¶
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emit_ldaxrh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldclr ¶
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emit_ldclr :: emit_ldclr_r_r_m

emit_ldclr_r_r_m ¶
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emit_ldclr_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldclra ¶
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emit_ldclra :: emit_ldclra_r_r_m

emit_ldclra_r_r_m ¶
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emit_ldclra_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldclral ¶
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emit_ldclral :: emit_ldclral_r_r_m

emit_ldclral_r_r_m ¶
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emit_ldclral_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldclrl ¶
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emit_ldclrl :: emit_ldclrl_r_r_m

emit_ldclrl_r_r_m ¶
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emit_ldclrl_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldeor ¶
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emit_ldeor :: emit_ldeor_r_r_m

emit_ldeor_r_r_m ¶
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emit_ldeor_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldeora ¶
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emit_ldeora :: emit_ldeora_r_r_m

emit_ldeora_r_r_m ¶
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emit_ldeora_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldeoral ¶
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emit_ldeoral :: emit_ldeoral_r_r_m

emit_ldeoral_r_r_m ¶
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emit_ldeoral_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldeorl ¶
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emit_ldeorl :: emit_ldeorl_r_r_m

emit_ldeorl_r_r_m ¶
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emit_ldeorl_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldg ¶
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emit_ldg :: emit_ldg_r_m

emit_ldg_r_m ¶
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emit_ldg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldgm ¶
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emit_ldgm :: emit_ldgm_r_m

emit_ldgm_r_m ¶
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emit_ldgm_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldnp ¶
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emit_ldnp :: emit_ldnp_r_r_m

emit_ldnp_r_r_m ¶
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emit_ldnp_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldp ¶
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emit_ldp :: emit_ldp_r_r_m

emit_ldp_post ¶
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emit_ldp_post :: emit_ldp_post_r_r_m

emit_ldp_post_r_r_m ¶
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emit_ldp_post_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldp_pre ¶
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emit_ldp_pre :: emit_ldp_pre_r_r_m

emit_ldp_pre_r_r_m ¶
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emit_ldp_pre_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldp_r_r_m ¶
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emit_ldp_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldp_v ¶
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emit_ldp_v :: emit_ldp_v_r_r_m

emit_ldp_v_r_r_m ¶
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emit_ldp_v_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldpsw ¶
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emit_ldpsw :: emit_ldpsw_r_r_m

emit_ldpsw_post ¶
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emit_ldpsw_post :: emit_ldpsw_post_r_r_m

emit_ldpsw_post_r_r_m ¶
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emit_ldpsw_post_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldpsw_pre ¶
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emit_ldpsw_pre :: emit_ldpsw_pre_r_r_m

emit_ldpsw_pre_r_r_m ¶
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emit_ldpsw_pre_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldpsw_r_r_m ¶
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emit_ldpsw_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldr ¶
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emit_ldr :: emit_ldr_r_m

emit_ldr_lit ¶
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emit_ldr_lit :: emit_ldr_lit_r_l

emit_ldr_lit_r_l ¶
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emit_ldr_lit_r_l :: proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) {…}

emit_ldr_post ¶
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emit_ldr_post :: emit_ldr_post_r_m

emit_ldr_post_r_m ¶
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emit_ldr_post_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldr_pre ¶
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emit_ldr_pre :: emit_ldr_pre_r_m

emit_ldr_pre_r_m ¶
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emit_ldr_pre_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldr_r_m ¶
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emit_ldr_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldr_reg ¶
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emit_ldr_reg :: emit_ldr_reg_r_m

emit_ldr_reg_r_m ¶
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emit_ldr_reg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldr_v ¶
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emit_ldr_v :: emit_ldr_v_r_m

emit_ldr_v_r_m ¶
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emit_ldr_v_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldraa ¶
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emit_ldraa :: emit_ldraa_r_m

emit_ldraa_pre ¶
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emit_ldraa_pre :: emit_ldraa_pre_r_m

emit_ldraa_pre_r_m ¶
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emit_ldraa_pre_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldraa_r_m ¶
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emit_ldraa_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrab ¶
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emit_ldrab :: emit_ldrab_r_m

emit_ldrab_pre ¶
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emit_ldrab_pre :: emit_ldrab_pre_r_m

emit_ldrab_pre_r_m ¶
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emit_ldrab_pre_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrab_r_m ¶
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emit_ldrab_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrb ¶
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emit_ldrb :: emit_ldrb_r_m

emit_ldrb_post ¶
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emit_ldrb_post :: emit_ldrb_post_r_m

emit_ldrb_post_r_m ¶
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emit_ldrb_post_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrb_pre ¶
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emit_ldrb_pre :: emit_ldrb_pre_r_m

emit_ldrb_pre_r_m ¶
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emit_ldrb_pre_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrb_r_m ¶
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emit_ldrb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrb_reg ¶
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emit_ldrb_reg :: emit_ldrb_reg_r_m

emit_ldrb_reg_r_m ¶
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emit_ldrb_reg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrh ¶
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emit_ldrh :: emit_ldrh_r_m

emit_ldrh_post ¶
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emit_ldrh_post :: emit_ldrh_post_r_m

emit_ldrh_post_r_m ¶
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emit_ldrh_post_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrh_pre ¶
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emit_ldrh_pre :: emit_ldrh_pre_r_m

emit_ldrh_pre_r_m ¶
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emit_ldrh_pre_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrh_r_m ¶
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emit_ldrh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrh_reg ¶
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emit_ldrh_reg :: emit_ldrh_reg_r_m

emit_ldrh_reg_r_m ¶
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emit_ldrh_reg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrsb ¶
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emit_ldrsb :: emit_ldrsb_r_m

emit_ldrsb_r_m ¶
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emit_ldrsb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrsb_reg ¶
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emit_ldrsb_reg :: emit_ldrsb_reg_r_m

emit_ldrsb_reg_r_m ¶
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emit_ldrsb_reg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrsh ¶
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emit_ldrsh :: emit_ldrsh_r_m

emit_ldrsh_r_m ¶
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emit_ldrsh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrsh_reg ¶
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emit_ldrsh_reg :: emit_ldrsh_reg_r_m

emit_ldrsh_reg_r_m ¶
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emit_ldrsh_reg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrsw ¶
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emit_ldrsw :: emit_ldrsw_r_m

emit_ldrsw_r_m ¶
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emit_ldrsw_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldrsw_reg ¶
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emit_ldrsw_reg :: emit_ldrsw_reg_r_m

emit_ldrsw_reg_r_m ¶
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emit_ldrsw_reg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldset ¶
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emit_ldset :: emit_ldset_r_r_m

emit_ldset_r_r_m ¶
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emit_ldset_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldseta ¶
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emit_ldseta :: emit_ldseta_r_r_m

emit_ldseta_r_r_m ¶
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emit_ldseta_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldsetal ¶
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emit_ldsetal :: emit_ldsetal_r_r_m

emit_ldsetal_r_r_m ¶
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emit_ldsetal_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldsetl ¶
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emit_ldsetl :: emit_ldsetl_r_r_m

emit_ldsetl_r_r_m ¶
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emit_ldsetl_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldsmax ¶
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emit_ldsmax :: emit_ldsmax_r_r_m

emit_ldsmax_r_r_m ¶
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emit_ldsmax_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldsmaxa ¶
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emit_ldsmaxa :: emit_ldsmaxa_r_r_m

emit_ldsmaxa_r_r_m ¶
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emit_ldsmaxa_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldsmaxal ¶
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emit_ldsmaxal :: emit_ldsmaxal_r_r_m

emit_ldsmaxal_r_r_m ¶
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emit_ldsmaxal_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldsmaxl ¶
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emit_ldsmaxl :: emit_ldsmaxl_r_r_m

emit_ldsmaxl_r_r_m ¶
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emit_ldsmaxl_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldsmin ¶
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emit_ldsmin :: emit_ldsmin_r_r_m

emit_ldsmin_r_r_m ¶
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emit_ldsmin_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldsmina ¶
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emit_ldsmina :: emit_ldsmina_r_r_m

emit_ldsmina_r_r_m ¶
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emit_ldsmina_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldsminal ¶
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emit_ldsminal :: emit_ldsminal_r_r_m

emit_ldsminal_r_r_m ¶
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emit_ldsminal_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldsminl ¶
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emit_ldsminl :: emit_ldsminl_r_r_m

emit_ldsminl_r_r_m ¶
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emit_ldsminl_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldumax ¶
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emit_ldumax :: emit_ldumax_r_r_m

emit_ldumax_r_r_m ¶
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emit_ldumax_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldumaxa ¶
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emit_ldumaxa :: emit_ldumaxa_r_r_m

emit_ldumaxa_r_r_m ¶
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emit_ldumaxa_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldumaxal ¶
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emit_ldumaxal :: emit_ldumaxal_r_r_m

emit_ldumaxal_r_r_m ¶
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emit_ldumaxal_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldumaxl ¶
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emit_ldumaxl :: emit_ldumaxl_r_r_m

emit_ldumaxl_r_r_m ¶
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emit_ldumaxl_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldumin ¶
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emit_ldumin :: emit_ldumin_r_r_m

emit_ldumin_r_r_m ¶
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emit_ldumin_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldumina ¶
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emit_ldumina :: emit_ldumina_r_r_m

emit_ldumina_r_r_m ¶
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emit_ldumina_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_lduminal ¶
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emit_lduminal :: emit_lduminal_r_r_m

emit_lduminal_r_r_m ¶
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emit_lduminal_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_lduminl ¶
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emit_lduminl :: emit_lduminl_r_r_m

emit_lduminl_r_r_m ¶
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emit_lduminl_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldur ¶
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emit_ldur :: emit_ldur_r_m

emit_ldur_r_m ¶
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emit_ldur_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldur_v ¶
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emit_ldur_v :: emit_ldur_v_r_m

emit_ldur_v_r_m ¶
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emit_ldur_v_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldurb ¶
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emit_ldurb :: emit_ldurb_r_m

emit_ldurb_r_m ¶
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emit_ldurb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldurh ¶
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emit_ldurh :: emit_ldurh_r_m

emit_ldurh_r_m ¶
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emit_ldurh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldursb ¶
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emit_ldursb :: emit_ldursb_r_m

emit_ldursb_r_m ¶
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emit_ldursb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldursh ¶
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emit_ldursh :: emit_ldursh_r_m

emit_ldursh_r_m ¶
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emit_ldursh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldursw ¶
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emit_ldursw :: emit_ldursw_r_m

emit_ldursw_r_m ¶
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emit_ldursw_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldxp ¶
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emit_ldxp :: emit_ldxp_r_r_m

emit_ldxp_r_r_m ¶
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emit_ldxp_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_ldxr ¶
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emit_ldxr :: emit_ldxr_r_m

emit_ldxr_r_m ¶
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emit_ldxr_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldxrb ¶
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emit_ldxrb :: emit_ldxrb_r_m

emit_ldxrb_r_m ¶
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emit_ldxrb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_ldxrh ¶
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emit_ldxrh :: emit_ldxrh_r_m

emit_ldxrh_r_m ¶
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emit_ldxrh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_lsl_imm ¶
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emit_lsl_imm :: emit_lsl_imm_r_r_i

emit_lsl_imm_r_r_i ¶
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emit_lsl_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_lslv ¶
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emit_lslv :: emit_lslv_r_r_r

emit_lslv_r_r_r ¶
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emit_lslv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_lsr_imm ¶
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emit_lsr_imm :: emit_lsr_imm_r_r_i

emit_lsr_imm_r_r_i ¶
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emit_lsr_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_lsrv ¶
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emit_lsrv :: emit_lsrv_r_r_r

emit_lsrv_r_r_r ¶
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emit_lsrv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_madd ¶
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emit_madd :: emit_madd_r_r_r_r

emit_madd_r_r_r_r ¶
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emit_madd_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_mla_v ¶
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emit_mla_v :: emit_mla_v_r_r_r

emit_mla_v_r_r_r ¶
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emit_mla_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_mls_v ¶
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emit_mls_v :: emit_mls_v_r_r_r

emit_mls_v_r_r_r ¶
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emit_mls_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_mov_bitmask ¶
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emit_mov_bitmask :: emit_mov_bitmask_r_i

emit_mov_bitmask_r_i ¶
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emit_mov_bitmask_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

emit_mov_reg ¶
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emit_mov_reg :: emit_mov_reg_r_r

emit_mov_reg_r_r ¶
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emit_mov_reg_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_mov_v ¶
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emit_mov_v :: emit_mov_v_r_r

emit_mov_v_alias ¶
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emit_mov_v_alias :: emit_mov_v_alias_r_r

emit_mov_v_alias_r_r ¶
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emit_mov_v_alias_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_mov_v_r_r ¶
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emit_mov_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_movi ¶
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emit_movi :: emit_movi_r_i

emit_movi_r_i ¶
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emit_movi_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

emit_movk ¶
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emit_movk :: emit_movk_r_i_i

emit_movk_r_i_i ¶
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emit_movk_r_i_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) {…}

emit_movn ¶
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emit_movn :: emit_movn_r_i_i

emit_movn_r_i_i ¶
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emit_movn_r_i_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) {…}

emit_movz ¶
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emit_movz :: emit_movz_r_i_i

emit_movz_r_i_i ¶
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emit_movz_r_i_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) {…}

emit_mrs ¶
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emit_mrs :: emit_mrs_r_i

emit_mrs_r_i ¶
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emit_mrs_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

emit_msr_imm ¶
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emit_msr_imm :: emit_msr_imm_i_i

emit_msr_imm_i_i ¶
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emit_msr_imm_i_i :: proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) {…}

emit_msr_reg ¶
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emit_msr_reg :: emit_msr_reg_i_r

emit_msr_reg_i_r ¶
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emit_msr_reg_i_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) {…}

emit_msub ¶
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emit_msub :: emit_msub_r_r_r_r

emit_msub_r_r_r_r ¶
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emit_msub_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_mul_v ¶
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emit_mul_v :: emit_mul_v_r_r_r

emit_mul_v_r_r_r ¶
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emit_mul_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_mvn ¶
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emit_mvn :: emit_mvn_r_r

emit_mvn_r_r ¶
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emit_mvn_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_mvn_v ¶
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emit_mvn_v :: emit_mvn_v_r_r

emit_mvn_v_r_r ¶
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emit_mvn_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_mvni ¶
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emit_mvni :: emit_mvni_r_i

emit_mvni_r_i ¶
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emit_mvni_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

emit_neg_sr ¶
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emit_neg_sr :: emit_neg_sr_r_sh

emit_neg_sr_r_sh ¶
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emit_neg_sr_r_sh :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) {…}

emit_neg_v ¶
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emit_neg_v :: emit_neg_v_r_r

emit_neg_v_r_r ¶
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emit_neg_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_negs ¶
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emit_negs :: emit_negs_r_sh

emit_negs_r_sh ¶
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emit_negs_r_sh :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) {…}

emit_ngc ¶
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emit_ngc :: emit_ngc_r_r

emit_ngc_r_r ¶
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emit_ngc_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_ngcs ¶
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emit_ngcs :: emit_ngcs_r_r

emit_ngcs_r_r ¶
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emit_ngcs_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_nop ¶
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emit_nop :: emit_nop_none

emit_nop_none ¶
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emit_nop_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_not_v ¶
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emit_not_v :: emit_not_v_r_r

emit_not_v_alias ¶
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emit_not_v_alias :: emit_not_v_alias_r_r

emit_not_v_alias_r_r ¶
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emit_not_v_alias_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_not_v_r_r ¶
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emit_not_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_orn_sr ¶
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emit_orn_sr :: emit_orn_sr_r_r_sh

emit_orn_sr_r_r_sh ¶
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emit_orn_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_orn_v ¶
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emit_orn_v :: emit_orn_v_r_r_r

emit_orn_v_r_r_r ¶
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emit_orn_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_orr_imm ¶
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emit_orr_imm :: emit_orr_imm_r_r_i

emit_orr_imm_r_r_i ¶
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emit_orr_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_orr_sr ¶
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emit_orr_sr :: emit_orr_sr_r_r_sh

emit_orr_sr_r_r_sh ¶
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emit_orr_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_orr_v ¶
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emit_orr_v :: emit_orr_v_r_r_r

emit_orr_v_r_r_r ¶
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emit_orr_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_pacda ¶
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emit_pacda :: emit_pacda_r_r

emit_pacda_r_r ¶
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emit_pacda_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_pacdb ¶
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emit_pacdb :: emit_pacdb_r_r

emit_pacdb_r_r ¶
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emit_pacdb_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_pacdza ¶
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emit_pacdza :: emit_pacdza_r

emit_pacdza_r ¶
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emit_pacdza_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_pacdzb ¶
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emit_pacdzb :: emit_pacdzb_r

emit_pacdzb_r ¶
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emit_pacdzb_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_pacga ¶
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emit_pacga :: emit_pacga_r_r_r

emit_pacga_r_r_r ¶
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emit_pacga_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_pacia ¶
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emit_pacia :: emit_pacia_r_r

emit_pacia1716 ¶
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emit_pacia1716 :: emit_pacia1716_none

emit_pacia1716_none ¶
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emit_pacia1716_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_pacia_r_r ¶
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emit_pacia_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_paciasp ¶
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emit_paciasp :: emit_paciasp_none

emit_paciasp_none ¶
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emit_paciasp_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_pacib ¶
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emit_pacib :: emit_pacib_r_r

emit_pacib1716 ¶
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emit_pacib1716 :: emit_pacib1716_none

emit_pacib1716_none ¶
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emit_pacib1716_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_pacib_r_r ¶
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emit_pacib_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_pacibsp ¶
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emit_pacibsp :: emit_pacibsp_none

emit_pacibsp_none ¶
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emit_pacibsp_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_paciza ¶
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emit_paciza :: emit_paciza_r

emit_paciza_r ¶
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emit_paciza_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_pacizb ¶
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emit_pacizb :: emit_pacizb_r

emit_pacizb_r ¶
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emit_pacizb_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_pmull ¶
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emit_pmull :: emit_pmull_r_r_r

emit_pmull2 ¶
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emit_pmull2 :: emit_pmull2_r_r_r

emit_pmull2_r_r_r ¶
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emit_pmull2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_pmull_r_r_r ¶
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emit_pmull_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_prfm ¶
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emit_prfm :: emit_prfm_i_m

emit_prfm_i_m ¶
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emit_prfm_i_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) {…}

emit_prfm_lit ¶
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emit_prfm_lit :: emit_prfm_lit_i_l

emit_prfm_lit_i_l ¶
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emit_prfm_lit_i_l :: proc(instructions: ^[dynamic]Instruction, imm: i64, label: u32) {…}

emit_prfum ¶
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emit_prfum :: emit_prfum_i_m

emit_prfum_i_m ¶
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emit_prfum_i_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) {…}

emit_psb_csync ¶
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emit_psb_csync :: emit_psb_csync_none

emit_psb_csync_none ¶
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emit_psb_csync_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_raddhn ¶
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emit_raddhn :: emit_raddhn_r_r_r

emit_raddhn2 ¶
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emit_raddhn2 :: emit_raddhn2_r_r_r

emit_raddhn2_r_r_r ¶
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emit_raddhn2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_raddhn_r_r_r ¶
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emit_raddhn_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_rax1 ¶
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emit_rax1 :: emit_rax1_r_r_r

emit_rax1_r_r_r ¶
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emit_rax1_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_rbit ¶
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emit_rbit :: emit_rbit_r_r

emit_rbit_r_r ¶
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emit_rbit_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_rbit_v ¶
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emit_rbit_v :: emit_rbit_v_r_r

emit_rbit_v_r_r ¶
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emit_rbit_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_ret_none ¶
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emit_ret_none :: proc(instructions: ^[dynamic]Instruction) {…}

Related Procedure Groups

emit_ret

emit_ret_r ¶
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emit_ret_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

Related Procedure Groups

emit_ret

emit_retaa ¶
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emit_retaa :: emit_retaa_none

emit_retaa_none ¶
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emit_retaa_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_retab ¶
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emit_retab :: emit_retab_none

emit_retab_none ¶
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emit_retab_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_rev ¶
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emit_rev :: emit_rev_r_r

emit_rev16 ¶
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emit_rev16 :: emit_rev16_r_r

emit_rev16_r_r ¶
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emit_rev16_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_rev16_v ¶
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emit_rev16_v :: emit_rev16_v_r_r

emit_rev16_v_r_r ¶
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emit_rev16_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_rev32 ¶
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emit_rev32 :: emit_rev32_r_r

emit_rev32_r_r ¶
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emit_rev32_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_rev32_v ¶
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emit_rev32_v :: emit_rev32_v_r_r

emit_rev32_v_r_r ¶
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emit_rev32_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_rev64 ¶
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emit_rev64 :: emit_rev64_r_r

emit_rev64_r_r ¶
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emit_rev64_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_rev_r_r ¶
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emit_rev_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_ror_imm ¶
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emit_ror_imm :: emit_ror_imm_r_r_i

emit_ror_imm_r_r_i ¶
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emit_ror_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_rorv ¶
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emit_rorv :: emit_rorv_r_r_r

emit_rorv_r_r_r ¶
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emit_rorv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_rshrn ¶
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emit_rshrn :: emit_rshrn_r_r_i

emit_rshrn2 ¶
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emit_rshrn2 :: emit_rshrn2_r_r_i

emit_rshrn2_r_r_i ¶
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emit_rshrn2_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_rshrn_r_r_i ¶
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emit_rshrn_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_rsubhn ¶
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emit_rsubhn :: emit_rsubhn_r_r_r

emit_rsubhn2 ¶
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emit_rsubhn2 :: emit_rsubhn2_r_r_r

emit_rsubhn2_r_r_r ¶
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emit_rsubhn2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_rsubhn_r_r_r ¶
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emit_rsubhn_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_saba ¶
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emit_saba :: emit_saba_r_r_r

emit_saba_r_r_r ¶
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emit_saba_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sabd ¶
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emit_sabd :: emit_sabd_r_r_r

emit_sabd_r_r_r ¶
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emit_sabd_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sadalp ¶
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emit_sadalp :: emit_sadalp_r_r

emit_sadalp_r_r ¶
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emit_sadalp_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_saddl ¶
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emit_saddl :: emit_saddl_r_r_r

emit_saddl2 ¶
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emit_saddl2 :: emit_saddl2_r_r_r

emit_saddl2_r_r_r ¶
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emit_saddl2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_saddl_r_r_r ¶
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emit_saddl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_saddlp ¶
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emit_saddlp :: emit_saddlp_r_r

emit_saddlp_r_r ¶
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emit_saddlp_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_saddlv ¶
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emit_saddlv :: emit_saddlv_r_r

emit_saddlv_r_r ¶
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emit_saddlv_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_saddw ¶
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emit_saddw :: emit_saddw_r_r_r

emit_saddw2 ¶
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emit_saddw2 :: emit_saddw2_r_r_r

emit_saddw2_r_r_r ¶
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emit_saddw2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_saddw_r_r_r ¶
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emit_saddw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sb ¶
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emit_sb :: emit_sb_none

emit_sb_none ¶
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emit_sb_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_sbc ¶
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emit_sbc :: emit_sbc_r_r_r

emit_sbc_r_r_r ¶
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emit_sbc_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sbcs ¶
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emit_sbcs :: emit_sbcs_r_r_r

emit_sbcs_r_r_r ¶
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emit_sbcs_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_scvtf ¶
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emit_scvtf :: emit_scvtf_r_r

emit_scvtf_h ¶
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emit_scvtf_h :: emit_scvtf_h_r_r

emit_scvtf_h_r_r ¶
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emit_scvtf_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_scvtf_r_r ¶
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emit_scvtf_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_scvtf_v ¶
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emit_scvtf_v :: emit_scvtf_v_r_r

emit_scvtf_v_r_r ¶
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emit_scvtf_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sdiv ¶
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emit_sdiv :: emit_sdiv_r_r_r

emit_sdiv_r_r_r ¶
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emit_sdiv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sdot ¶
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emit_sdot :: emit_sdot_r_r_r

emit_sdot_r_r_r ¶
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emit_sdot_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sete ¶
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emit_sete :: emit_sete_r_r_r

emit_sete_r_r_r ¶
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emit_sete_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_setm ¶
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emit_setm :: emit_setm_r_r_r

emit_setm_r_r_r ¶
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emit_setm_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_setp ¶
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emit_setp :: emit_setp_r_r_r

emit_setp_r_r_r ¶
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emit_setp_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sev ¶
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emit_sev :: emit_sev_none

emit_sev_none ¶
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emit_sev_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_sevl ¶
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emit_sevl :: emit_sevl_none

emit_sevl_none ¶
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emit_sevl_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_sha1c ¶
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emit_sha1c :: emit_sha1c_r_r_r

emit_sha1c_r_r_r ¶
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emit_sha1c_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sha1h ¶
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emit_sha1h :: emit_sha1h_r_r

emit_sha1h_r_r ¶
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emit_sha1h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sha1m ¶
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emit_sha1m :: emit_sha1m_r_r_r

emit_sha1m_r_r_r ¶
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emit_sha1m_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sha1p ¶
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emit_sha1p :: emit_sha1p_r_r_r

emit_sha1p_r_r_r ¶
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emit_sha1p_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sha1su0 ¶
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emit_sha1su0 :: emit_sha1su0_r_r_r

emit_sha1su0_r_r_r ¶
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emit_sha1su0_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sha1su1 ¶
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emit_sha1su1 :: emit_sha1su1_r_r

emit_sha1su1_r_r ¶
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emit_sha1su1_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sha256h ¶
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emit_sha256h :: emit_sha256h_r_r_r

emit_sha256h2 ¶
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emit_sha256h2 :: emit_sha256h2_r_r_r

emit_sha256h2_r_r_r ¶
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emit_sha256h2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sha256h_r_r_r ¶
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emit_sha256h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sha256su0 ¶
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emit_sha256su0 :: emit_sha256su0_r_r

emit_sha256su0_r_r ¶
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emit_sha256su0_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sha256su1 ¶
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emit_sha256su1 :: emit_sha256su1_r_r_r

emit_sha256su1_r_r_r ¶
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emit_sha256su1_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sha512h ¶
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emit_sha512h :: emit_sha512h_r_r_r

emit_sha512h2 ¶
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emit_sha512h2 :: emit_sha512h2_r_r_r

emit_sha512h2_r_r_r ¶
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emit_sha512h2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sha512h_r_r_r ¶
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emit_sha512h_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sha512su0 ¶
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emit_sha512su0 :: emit_sha512su0_r_r

emit_sha512su0_r_r ¶
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emit_sha512su0_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sha512su1 ¶
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emit_sha512su1 :: emit_sha512su1_r_r_r

emit_sha512su1_r_r_r ¶
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emit_sha512su1_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_shadd ¶
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emit_shadd :: emit_shadd_r_r_r

emit_shadd_r_r_r ¶
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emit_shadd_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_shl_v ¶
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emit_shl_v :: emit_shl_v_r_r_i

emit_shl_v_r_r_i ¶
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emit_shl_v_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_shrn ¶
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emit_shrn :: emit_shrn_r_r_i

emit_shrn2 ¶
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emit_shrn2 :: emit_shrn2_r_r_i

emit_shrn2_r_r_i ¶
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emit_shrn2_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_shrn_r_r_i ¶
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emit_shrn_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_shsub ¶
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emit_shsub :: emit_shsub_r_r_r

emit_shsub_r_r_r ¶
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emit_shsub_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sli ¶
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emit_sli :: emit_sli_r_r_i

emit_sli_r_r_i ¶
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emit_sli_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sm3partw1 ¶
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emit_sm3partw1 :: emit_sm3partw1_r_r_r

emit_sm3partw1_r_r_r ¶
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emit_sm3partw1_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sm3partw2 ¶
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emit_sm3partw2 :: emit_sm3partw2_r_r_r

emit_sm3partw2_r_r_r ¶
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emit_sm3partw2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sm3ss1 ¶
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emit_sm3ss1 :: emit_sm3ss1_r_r_r_r

emit_sm3ss1_r_r_r_r ¶
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emit_sm3ss1_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_sm3tt1a ¶
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emit_sm3tt1a :: emit_sm3tt1a_r_r_r

emit_sm3tt1a_r_r_r ¶
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emit_sm3tt1a_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sm3tt1b ¶
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emit_sm3tt1b :: emit_sm3tt1b_r_r_r

emit_sm3tt1b_r_r_r ¶
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emit_sm3tt1b_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sm3tt2a ¶
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emit_sm3tt2a :: emit_sm3tt2a_r_r_r

emit_sm3tt2a_r_r_r ¶
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emit_sm3tt2a_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sm3tt2b ¶
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emit_sm3tt2b :: emit_sm3tt2b_r_r_r

emit_sm3tt2b_r_r_r ¶
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emit_sm3tt2b_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sm4e ¶
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emit_sm4e :: emit_sm4e_r_r

emit_sm4e_r_r ¶
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emit_sm4e_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sm4ekey ¶
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emit_sm4ekey :: emit_sm4ekey_r_r_r

emit_sm4ekey_r_r_r ¶
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emit_sm4ekey_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_smaddl ¶
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emit_smaddl :: emit_smaddl_r_r_r_r

emit_smaddl_r_r_r_r ¶
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emit_smaddl_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_smax ¶
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emit_smax :: emit_smax_r_r_r

emit_smax_r_r_r ¶
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emit_smax_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_smaxp ¶
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emit_smaxp :: emit_smaxp_r_r_r

emit_smaxp_r_r_r ¶
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emit_smaxp_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_smaxv ¶
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emit_smaxv :: emit_smaxv_r_r

emit_smaxv_r_r ¶
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emit_smaxv_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_smc ¶
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emit_smc :: emit_smc_i

emit_smc_i ¶
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emit_smc_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_sme2_ld1b_x2 ¶
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emit_sme2_ld1b_x2 :: emit_sme2_ld1b_x2_z_p_m

emit_sme2_ld1b_x2_z_p_m ¶
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emit_sme2_ld1b_x2_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_ld1b_x4 ¶
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emit_sme2_ld1b_x4 :: emit_sme2_ld1b_x4_z_p_m

emit_sme2_ld1b_x4_z_p_m ¶
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emit_sme2_ld1b_x4_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_ld1d_x2 ¶
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emit_sme2_ld1d_x2 :: emit_sme2_ld1d_x2_z_p_m

emit_sme2_ld1d_x2_z_p_m ¶
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emit_sme2_ld1d_x2_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_ld1d_x4 ¶
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emit_sme2_ld1d_x4 :: emit_sme2_ld1d_x4_z_p_m

emit_sme2_ld1d_x4_z_p_m ¶
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emit_sme2_ld1d_x4_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_ld1h_x2 ¶
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emit_sme2_ld1h_x2 :: emit_sme2_ld1h_x2_z_p_m

emit_sme2_ld1h_x2_z_p_m ¶
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emit_sme2_ld1h_x2_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_ld1h_x4 ¶
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emit_sme2_ld1h_x4 :: emit_sme2_ld1h_x4_z_p_m

emit_sme2_ld1h_x4_z_p_m ¶
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emit_sme2_ld1h_x4_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_ld1w_x2 ¶
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emit_sme2_ld1w_x2 :: emit_sme2_ld1w_x2_z_p_m

emit_sme2_ld1w_x2_z_p_m ¶
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emit_sme2_ld1w_x2_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_ld1w_x4 ¶
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emit_sme2_ld1w_x4 :: emit_sme2_ld1w_x4_z_p_m

emit_sme2_ld1w_x4_z_p_m ¶
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emit_sme2_ld1w_x4_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_luti2_b ¶
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emit_sme2_luti2_b :: emit_sme2_luti2_b_z_z_z_i

emit_sme2_luti2_b_z_z_z_i ¶
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emit_sme2_luti2_b_z_z_z_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) {…}

emit_sme2_luti4_b ¶
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emit_sme2_luti4_b :: emit_sme2_luti4_b_z_z_z_i

emit_sme2_luti4_b_z_z_z_i ¶
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emit_sme2_luti4_b_z_z_z_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) {…}

emit_sme2_st1b_x2 ¶
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emit_sme2_st1b_x2 :: emit_sme2_st1b_x2_z_p_m

emit_sme2_st1b_x2_z_p_m ¶
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emit_sme2_st1b_x2_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_st1b_x4 ¶
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emit_sme2_st1b_x4 :: emit_sme2_st1b_x4_z_p_m

emit_sme2_st1b_x4_z_p_m ¶
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emit_sme2_st1b_x4_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_st1d_x2 ¶
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emit_sme2_st1d_x2 :: emit_sme2_st1d_x2_z_p_m

emit_sme2_st1d_x2_z_p_m ¶
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emit_sme2_st1d_x2_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_st1d_x4 ¶
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emit_sme2_st1d_x4 :: emit_sme2_st1d_x4_z_p_m

emit_sme2_st1d_x4_z_p_m ¶
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emit_sme2_st1d_x4_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_st1h_x2 ¶
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emit_sme2_st1h_x2 :: emit_sme2_st1h_x2_z_p_m

emit_sme2_st1h_x2_z_p_m ¶
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emit_sme2_st1h_x2_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_st1h_x4 ¶
Source

emit_sme2_st1h_x4 :: emit_sme2_st1h_x4_z_p_m

emit_sme2_st1h_x4_z_p_m ¶
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emit_sme2_st1h_x4_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_st1w_x2 ¶
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emit_sme2_st1w_x2 :: emit_sme2_st1w_x2_z_p_m

emit_sme2_st1w_x2_z_p_m ¶
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emit_sme2_st1w_x2_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_st1w_x4 ¶
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emit_sme2_st1w_x4 :: emit_sme2_st1w_x4_z_p_m

emit_sme2_st1w_x4_z_p_m ¶
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emit_sme2_st1w_x4_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sme2_uzp_3 ¶
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emit_sme2_uzp_3 :: emit_sme2_uzp_3_z_z_z

emit_sme2_uzp_3_z_z_z ¶
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emit_sme2_uzp_3_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sme2_uzp_4 ¶
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emit_sme2_uzp_4 :: emit_sme2_uzp_4_z_z

emit_sme2_uzp_4_z_z ¶
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emit_sme2_uzp_4_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) {…}

emit_sme2_zip_3 ¶
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emit_sme2_zip_3 :: emit_sme2_zip_3_z_z_z

emit_sme2_zip_3_z_z_z ¶
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emit_sme2_zip_3_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sme2_zip_4 ¶
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emit_sme2_zip_4 :: emit_sme2_zip_4_z_z

emit_sme2_zip_4_z_z ¶
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emit_sme2_zip_4_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) {…}

emit_sme_addha ¶
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emit_sme_addha :: emit_sme_addha_i_p_p_z

emit_sme_addha_i_p_p_z ¶
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emit_sme_addha_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_addva ¶
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emit_sme_addva :: emit_sme_addva_i_p_p_z

emit_sme_addva_i_p_p_z ¶
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emit_sme_addva_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_bfmopa ¶
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emit_sme_bfmopa :: emit_sme_bfmopa_i_p_p_z

emit_sme_bfmopa_i_p_p_z ¶
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emit_sme_bfmopa_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_bfmops ¶
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emit_sme_bfmops :: emit_sme_bfmops_i_p_p_z

emit_sme_bfmops_i_p_p_z ¶
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emit_sme_bfmops_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_fmopa ¶
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emit_sme_fmopa :: emit_sme_fmopa_i_p_p_z

emit_sme_fmopa_i_p_p_z ¶
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emit_sme_fmopa_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_fmops ¶
Source

emit_sme_fmops :: emit_sme_fmops_i_p_p_z

emit_sme_fmops_i_p_p_z ¶
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emit_sme_fmops_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_ld1b_tile ¶
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emit_sme_ld1b_tile :: emit_sme_ld1b_tile_i_p_m

emit_sme_ld1b_tile_i_p_m ¶
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emit_sme_ld1b_tile_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sme_ld1b_za ¶
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emit_sme_ld1b_za :: emit_sme_ld1b_tile_i_p_m

emit_sme_ld1d_tile ¶
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emit_sme_ld1d_tile :: emit_sme_ld1d_tile_i_p_m

emit_sme_ld1d_tile_i_p_m ¶
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emit_sme_ld1d_tile_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sme_ld1d_za ¶
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emit_sme_ld1d_za :: emit_sme_ld1d_tile_i_p_m

emit_sme_ld1h_tile ¶
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emit_sme_ld1h_tile :: emit_sme_ld1h_tile_i_p_m

emit_sme_ld1h_tile_i_p_m ¶
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emit_sme_ld1h_tile_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sme_ld1h_za ¶
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emit_sme_ld1h_za :: emit_sme_ld1h_tile_i_p_m

emit_sme_ld1q_tile ¶
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emit_sme_ld1q_tile :: emit_sme_ld1q_tile_i_p_m

emit_sme_ld1q_tile_i_p_m ¶
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emit_sme_ld1q_tile_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sme_ld1q_za ¶
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emit_sme_ld1q_za :: emit_sme_ld1q_tile_i_p_m

emit_sme_ld1w_tile ¶
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emit_sme_ld1w_tile :: emit_sme_ld1w_tile_i_p_m

emit_sme_ld1w_tile_i_p_m ¶
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emit_sme_ld1w_tile_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sme_ld1w_za ¶
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emit_sme_ld1w_za :: emit_sme_ld1w_tile_i_p_m

emit_sme_ldr_za ¶
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emit_sme_ldr_za :: emit_sme_ldr_za_i_m

emit_sme_ldr_za_i_m ¶
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emit_sme_ldr_za_i_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) {…}

emit_sme_mova_tile_from_z ¶
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emit_sme_mova_tile_from_z :: emit_sme_mova_tile_from_z_i_p_z

emit_sme_mova_tile_from_z_i_p_z ¶
Source

emit_sme_mova_tile_from_z_i_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8) {…}

emit_sme_mova_to_z ¶
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emit_sme_mova_to_z :: emit_sme_mova_z_from_tile_z_p_i

emit_sme_mova_to_za ¶
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emit_sme_mova_to_za :: emit_sme_mova_tile_from_z_i_p_z

emit_sme_mova_z_from_tile ¶
Source

emit_sme_mova_z_from_tile :: emit_sme_mova_z_from_tile_z_p_i

emit_sme_mova_z_from_tile_z_p_i ¶
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emit_sme_mova_z_from_tile_z_p_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) {…}

emit_sme_rdsvl ¶
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emit_sme_rdsvl :: emit_sme_rdsvl_r_i

emit_sme_rdsvl_r_i ¶
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emit_sme_rdsvl_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

emit_sme_smopa ¶
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emit_sme_smopa :: emit_sme_smopa_i_p_p_z

emit_sme_smopa_i_p_p_z ¶
Source

emit_sme_smopa_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_smops ¶
Source

emit_sme_smops :: emit_sme_smops_i_p_p_z

emit_sme_smops_i_p_p_z ¶
Source

emit_sme_smops_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_smstart ¶
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emit_sme_smstart :: emit_sme_smstart_none

emit_sme_smstart_none ¶
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emit_sme_smstart_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_sme_smstop ¶
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emit_sme_smstop :: emit_sme_smstop_none

emit_sme_smstop_none ¶
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emit_sme_smstop_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_sme_st1b_tile ¶
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emit_sme_st1b_tile :: emit_sme_st1b_tile_i_p_m

emit_sme_st1b_tile_i_p_m ¶
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emit_sme_st1b_tile_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sme_st1b_za ¶
Source

emit_sme_st1b_za :: emit_sme_st1b_tile_i_p_m

emit_sme_st1d_tile ¶
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emit_sme_st1d_tile :: emit_sme_st1d_tile_i_p_m

emit_sme_st1d_tile_i_p_m ¶
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emit_sme_st1d_tile_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sme_st1d_za ¶
Source

emit_sme_st1d_za :: emit_sme_st1d_tile_i_p_m

emit_sme_st1h_tile ¶
Source

emit_sme_st1h_tile :: emit_sme_st1h_tile_i_p_m

emit_sme_st1h_tile_i_p_m ¶
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emit_sme_st1h_tile_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sme_st1h_za ¶
Source

emit_sme_st1h_za :: emit_sme_st1h_tile_i_p_m

emit_sme_st1q_tile ¶
Source

emit_sme_st1q_tile :: emit_sme_st1q_tile_i_p_m

emit_sme_st1q_tile_i_p_m ¶
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emit_sme_st1q_tile_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sme_st1q_za ¶
Source

emit_sme_st1q_za :: emit_sme_st1q_tile_i_p_m

emit_sme_st1w_tile ¶
Source

emit_sme_st1w_tile :: emit_sme_st1w_tile_i_p_m

emit_sme_st1w_tile_i_p_m ¶
Source

emit_sme_st1w_tile_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sme_st1w_za ¶
Source

emit_sme_st1w_za :: emit_sme_st1w_tile_i_p_m

emit_sme_str_za ¶
Source

emit_sme_str_za :: emit_sme_str_za_i_m

emit_sme_str_za_i_m ¶
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emit_sme_str_za_i_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) {…}

emit_sme_sumopa ¶
Source

emit_sme_sumopa :: emit_sme_sumopa_i_p_p_z

emit_sme_sumopa_i_p_p_z ¶
Source

emit_sme_sumopa_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_umopa ¶
Source

emit_sme_umopa :: emit_sme_umopa_i_p_p_z

emit_sme_umopa_i_p_p_z ¶
Source

emit_sme_umopa_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_umops ¶
Source

emit_sme_umops :: emit_sme_umops_i_p_p_z

emit_sme_umops_i_p_p_z ¶
Source

emit_sme_umops_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_usmopa ¶
Source

emit_sme_usmopa :: emit_sme_usmopa_i_p_p_z

emit_sme_usmopa_i_p_p_z ¶
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emit_sme_usmopa_i_p_p_z :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) {…}

emit_sme_zero ¶
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emit_sme_zero :: emit_sme_zero_i

emit_sme_zero_i ¶
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emit_sme_zero_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_smin ¶
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emit_smin :: emit_smin_r_r_r

emit_smin_r_r_r ¶
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emit_smin_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sminp ¶
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emit_sminp :: emit_sminp_r_r_r

emit_sminp_r_r_r ¶
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emit_sminp_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sminv ¶
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emit_sminv :: emit_sminv_r_r

emit_sminv_r_r ¶
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emit_sminv_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_smlal ¶
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emit_smlal :: emit_smlal_r_r_r

emit_smlal2 ¶
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emit_smlal2 :: emit_smlal2_r_r_r

emit_smlal2_r_r_r ¶
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emit_smlal2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_smlal_r_r_r ¶
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emit_smlal_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_smlsl ¶
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emit_smlsl :: emit_smlsl_r_r_r

emit_smlsl2 ¶
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emit_smlsl2 :: emit_smlsl2_r_r_r

emit_smlsl2_r_r_r ¶
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emit_smlsl2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_smlsl_r_r_r ¶
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emit_smlsl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_smsubl ¶
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emit_smsubl :: emit_smsubl_r_r_r_r

emit_smsubl_r_r_r_r ¶
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emit_smsubl_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_smulh ¶
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emit_smulh :: emit_smulh_r_r_r

emit_smulh_r_r_r ¶
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emit_smulh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_smull2_v ¶
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emit_smull2_v :: emit_smull2_v_r_r_r

emit_smull2_v_r_r_r ¶
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emit_smull2_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_smull_v ¶
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emit_smull_v :: emit_smull_v_r_r_r

emit_smull_v_r_r_r ¶
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emit_smull_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sqadd ¶
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emit_sqadd :: emit_sqadd_r_r_r

emit_sqadd_r_r_r ¶
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emit_sqadd_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sqdmlal ¶
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emit_sqdmlal :: emit_sqdmlal_r_r_r

emit_sqdmlal2 ¶
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emit_sqdmlal2 :: emit_sqdmlal2_r_r_r

emit_sqdmlal2_r_r_r ¶
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emit_sqdmlal2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sqdmlal_r_r_r ¶
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emit_sqdmlal_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sqdmlsl ¶
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emit_sqdmlsl :: emit_sqdmlsl_r_r_r

emit_sqdmlsl2 ¶
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emit_sqdmlsl2 :: emit_sqdmlsl2_r_r_r

emit_sqdmlsl2_r_r_r ¶
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emit_sqdmlsl2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sqdmlsl_r_r_r ¶
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emit_sqdmlsl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sqdmulh ¶
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emit_sqdmulh :: emit_sqdmulh_r_r_r

emit_sqdmulh_r_r_r ¶
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emit_sqdmulh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sqdmull ¶
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emit_sqdmull :: emit_sqdmull_r_r_r

emit_sqdmull2 ¶
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emit_sqdmull2 :: emit_sqdmull2_r_r_r

emit_sqdmull2_r_r_r ¶
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emit_sqdmull2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sqdmull_r_r_r ¶
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emit_sqdmull_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sqrdmulh ¶
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emit_sqrdmulh :: emit_sqrdmulh_r_r_r

emit_sqrdmulh_r_r_r ¶
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emit_sqrdmulh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sqrshrn ¶
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emit_sqrshrn :: emit_sqrshrn_r_r_i

emit_sqrshrn2 ¶
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emit_sqrshrn2 :: emit_sqrshrn2_r_r_i

emit_sqrshrn2_r_r_i ¶
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emit_sqrshrn2_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sqrshrn_r_r_i ¶
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emit_sqrshrn_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sqrshrun ¶
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emit_sqrshrun :: emit_sqrshrun_r_r_i

emit_sqrshrun2 ¶
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emit_sqrshrun2 :: emit_sqrshrun2_r_r_i

emit_sqrshrun2_r_r_i ¶
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emit_sqrshrun2_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sqrshrun_r_r_i ¶
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emit_sqrshrun_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sqshl_v ¶
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emit_sqshl_v :: emit_sqshl_v_r_r_i

emit_sqshl_v_r_r_i ¶
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emit_sqshl_v_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sqshlu ¶
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emit_sqshlu :: emit_sqshlu_r_r_i

emit_sqshlu_r_r_i ¶
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emit_sqshlu_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sqshrn ¶
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emit_sqshrn :: emit_sqshrn_r_r_i

emit_sqshrn2 ¶
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emit_sqshrn2 :: emit_sqshrn2_r_r_i

emit_sqshrn2_r_r_i ¶
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emit_sqshrn2_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sqshrn_r_r_i ¶
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emit_sqshrn_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sqshrun ¶
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emit_sqshrun :: emit_sqshrun_r_r_i

emit_sqshrun2 ¶
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emit_sqshrun2 :: emit_sqshrun2_r_r_i

emit_sqshrun2_r_r_i ¶
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emit_sqshrun2_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sqshrun_r_r_i ¶
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emit_sqshrun_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sqsub ¶
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emit_sqsub :: emit_sqsub_r_r_r

emit_sqsub_r_r_r ¶
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emit_sqsub_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sqxtn ¶
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emit_sqxtn :: emit_sqxtn_r_r

emit_sqxtn2 ¶
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emit_sqxtn2 :: emit_sqxtn2_r_r

emit_sqxtn2_r_r ¶
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emit_sqxtn2_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sqxtn_r_r ¶
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emit_sqxtn_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sqxtun ¶
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emit_sqxtun :: emit_sqxtun_r_r

emit_sqxtun2 ¶
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emit_sqxtun2 :: emit_sqxtun2_r_r

emit_sqxtun2_r_r ¶
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emit_sqxtun2_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sqxtun_r_r ¶
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emit_sqxtun_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_srhadd ¶
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emit_srhadd :: emit_srhadd_r_r_r

emit_srhadd_r_r_r ¶
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emit_srhadd_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sri ¶
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emit_sri :: emit_sri_r_r_i

emit_sri_r_r_i ¶
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emit_sri_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_srshl ¶
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emit_srshl :: emit_srshl_r_r_r

emit_srshl_r_r_r ¶
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emit_srshl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_srshr ¶
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emit_srshr :: emit_srshr_r_r_i

emit_srshr_r_r_i ¶
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emit_srshr_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_srsra ¶
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emit_srsra :: emit_srsra_r_r_i

emit_srsra_r_r_i ¶
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emit_srsra_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sshl ¶
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emit_sshl :: emit_sshl_r_r_r

emit_sshl_r_r_r ¶
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emit_sshl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_sshll ¶
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emit_sshll :: emit_sshll_r_r_i

emit_sshll2 ¶
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emit_sshll2 :: emit_sshll2_r_r_i

emit_sshll2_r_r_i ¶
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emit_sshll2_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sshll_r_r_i ¶
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emit_sshll_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sshr ¶
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emit_sshr :: emit_sshr_r_r_i

emit_sshr_r_r_i ¶
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emit_sshr_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_ssra ¶
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emit_ssra :: emit_ssra_r_r_i

emit_ssra_r_r_i ¶
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emit_ssra_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_ssubl ¶
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emit_ssubl :: emit_ssubl_r_r_r

emit_ssubl2 ¶
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emit_ssubl2 :: emit_ssubl2_r_r_r

emit_ssubl2_r_r_r ¶
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emit_ssubl2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_ssubl_r_r_r ¶
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emit_ssubl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_ssubw ¶
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emit_ssubw :: emit_ssubw_r_r_r

emit_ssubw2 ¶
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emit_ssubw2 :: emit_ssubw2_r_r_r

emit_ssubw2_r_r_r ¶
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emit_ssubw2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_ssubw_r_r_r ¶
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emit_ssubw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_st1 ¶
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emit_st1 :: emit_st1_r_m

emit_st1_lane ¶
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emit_st1_lane :: emit_st1_lane_r_i_m

emit_st1_lane_r_i_m ¶
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emit_st1_lane_r_i_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) {…}

emit_st1_r_m ¶
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emit_st1_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_st2 ¶
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emit_st2 :: emit_st2_r_m

emit_st2_lane ¶
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emit_st2_lane :: emit_st2_lane_r_i_m

emit_st2_lane_r_i_m ¶
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emit_st2_lane_r_i_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) {…}

emit_st2_r_m ¶
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emit_st2_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_st2g ¶
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emit_st2g :: emit_st2g_r_m

emit_st2g_r_m ¶
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emit_st2g_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_st3 ¶
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emit_st3 :: emit_st3_r_m

emit_st3_lane ¶
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emit_st3_lane :: emit_st3_lane_r_i_m

emit_st3_lane_r_i_m ¶
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emit_st3_lane_r_i_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) {…}

emit_st3_r_m ¶
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emit_st3_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_st4 ¶
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emit_st4 :: emit_st4_r_m

emit_st4_lane ¶
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emit_st4_lane :: emit_st4_lane_r_i_m

emit_st4_lane_r_i_m ¶
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emit_st4_lane_r_i_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) {…}

emit_st4_r_m ¶
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emit_st4_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stg ¶
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emit_stg :: emit_stg_r_m

emit_stg_r_m ¶
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emit_stg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stgm ¶
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emit_stgm :: emit_stgm_r_m

emit_stgm_r_m ¶
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emit_stgm_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stgp ¶
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emit_stgp :: emit_stgp_r_r_m

emit_stgp_r_r_m ¶
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emit_stgp_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_stlr ¶
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emit_stlr :: emit_stlr_r_m

emit_stlr_r_m ¶
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emit_stlr_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stlrb ¶
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emit_stlrb :: emit_stlrb_r_m

emit_stlrb_r_m ¶
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emit_stlrb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stlrh ¶
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emit_stlrh :: emit_stlrh_r_m

emit_stlrh_r_m ¶
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emit_stlrh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stlur ¶
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emit_stlur :: emit_stlur_r_m

emit_stlur_r_m ¶
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emit_stlur_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stlurb ¶
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emit_stlurb :: emit_stlurb_r_m

emit_stlurb_r_m ¶
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emit_stlurb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stlurh ¶
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emit_stlurh :: emit_stlurh_r_m

emit_stlurh_r_m ¶
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emit_stlurh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stlxp ¶
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emit_stlxp :: emit_stlxp_r_r_r_m

emit_stlxp_r_r_r_m ¶
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emit_stlxp_r_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) {…}

emit_stlxr ¶
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emit_stlxr :: emit_stlxr_r_r_m

emit_stlxr_r_r_m ¶
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emit_stlxr_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_stlxrb ¶
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emit_stlxrb :: emit_stlxrb_r_r_m

emit_stlxrb_r_r_m ¶
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emit_stlxrb_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_stlxrh ¶
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emit_stlxrh :: emit_stlxrh_r_r_m

emit_stlxrh_r_r_m ¶
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emit_stlxrh_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_stnp ¶
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emit_stnp :: emit_stnp_r_r_m

emit_stnp_r_r_m ¶
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emit_stnp_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_stp ¶
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emit_stp :: emit_stp_r_r_m

emit_stp_post ¶
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emit_stp_post :: emit_stp_post_r_r_m

emit_stp_post_r_r_m ¶
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emit_stp_post_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_stp_pre ¶
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emit_stp_pre :: emit_stp_pre_r_r_m

emit_stp_pre_r_r_m ¶
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emit_stp_pre_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_stp_r_r_m ¶
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emit_stp_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_stp_v ¶
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emit_stp_v :: emit_stp_v_r_r_m

emit_stp_v_r_r_m ¶
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emit_stp_v_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_str ¶
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emit_str :: emit_str_r_m

emit_str_post ¶
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emit_str_post :: emit_str_post_r_m

emit_str_post_r_m ¶
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emit_str_post_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_str_pre ¶
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emit_str_pre :: emit_str_pre_r_m

emit_str_pre_r_m ¶
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emit_str_pre_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_str_r_m ¶
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emit_str_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_str_reg ¶
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emit_str_reg :: emit_str_reg_r_m

emit_str_reg_r_m ¶
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emit_str_reg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_str_v ¶
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emit_str_v :: emit_str_v_r_m

emit_str_v_r_m ¶
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emit_str_v_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_strb ¶
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emit_strb :: emit_strb_r_m

emit_strb_post ¶
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emit_strb_post :: emit_strb_post_r_m

emit_strb_post_r_m ¶
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emit_strb_post_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_strb_pre ¶
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emit_strb_pre :: emit_strb_pre_r_m

emit_strb_pre_r_m ¶
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emit_strb_pre_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_strb_r_m ¶
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emit_strb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_strb_reg ¶
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emit_strb_reg :: emit_strb_reg_r_m

emit_strb_reg_r_m ¶
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emit_strb_reg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_strh ¶
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emit_strh :: emit_strh_r_m

emit_strh_post ¶
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emit_strh_post :: emit_strh_post_r_m

emit_strh_post_r_m ¶
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emit_strh_post_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_strh_pre ¶
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emit_strh_pre :: emit_strh_pre_r_m

emit_strh_pre_r_m ¶
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emit_strh_pre_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_strh_r_m ¶
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emit_strh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_strh_reg ¶
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emit_strh_reg :: emit_strh_reg_r_m

emit_strh_reg_r_m ¶
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emit_strh_reg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stur ¶
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emit_stur :: emit_stur_r_m

emit_stur_r_m ¶
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emit_stur_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stur_v ¶
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emit_stur_v :: emit_stur_v_r_m

emit_stur_v_r_m ¶
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emit_stur_v_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_sturb ¶
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emit_sturb :: emit_sturb_r_m

emit_sturb_r_m ¶
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emit_sturb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_sturh ¶
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emit_sturh :: emit_sturh_r_m

emit_sturh_r_m ¶
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emit_sturh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stxp ¶
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emit_stxp :: emit_stxp_r_r_r_m

emit_stxp_r_r_r_m ¶
Source

emit_stxp_r_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) {…}

emit_stxr ¶
Source

emit_stxr :: emit_stxr_r_r_m

emit_stxr_r_r_m ¶
Source

emit_stxr_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_stxrb ¶
Source

emit_stxrb :: emit_stxrb_r_r_m

emit_stxrb_r_r_m ¶
Source

emit_stxrb_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_stxrh ¶
Source

emit_stxrh :: emit_stxrh_r_r_m

emit_stxrh_r_r_m ¶
Source

emit_stxrh_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_stz2g ¶
Source

emit_stz2g :: emit_stz2g_r_m

emit_stz2g_r_m ¶
Source

emit_stz2g_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stzg ¶
Source

emit_stzg :: emit_stzg_r_m

emit_stzg_r_m ¶
Source

emit_stzg_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_stzgm ¶
Source

emit_stzgm :: emit_stzgm_r_m

emit_stzgm_r_m ¶
Source

emit_stzgm_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

emit_sub_er ¶
Source

emit_sub_er :: emit_sub_er_r_r_ex

emit_sub_er_r_r_ex ¶
Source

emit_sub_er_r_r_ex :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_ext:     Extend, 
	src2_amount:  u8, 
) {…}

emit_sub_imm ¶
Source

emit_sub_imm :: emit_sub_imm_r_r_i

emit_sub_imm_r_r_i ¶
Source

emit_sub_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_sub_sr ¶
Source

emit_sub_sr :: emit_sub_sr_r_r_sh

emit_sub_sr_r_r_sh ¶
Source

emit_sub_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_sub_v ¶
Source

emit_sub_v :: emit_sub_v_r_r_r

emit_sub_v_r_r_r ¶
Source

emit_sub_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_subg ¶
Source

emit_subg :: emit_subg_r_r_i_i

emit_subg_r_r_i_i ¶
Source

emit_subg_r_r_i_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) {…}

emit_subhn ¶
Source

emit_subhn :: emit_subhn_r_r_r

emit_subhn2 ¶
Source

emit_subhn2 :: emit_subhn2_r_r_r

emit_subhn2_r_r_r ¶
Source

emit_subhn2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_subhn_r_r_r ¶
Source

emit_subhn_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_subp ¶
Source

emit_subp :: emit_subp_r_r_r

emit_subp_r_r_r ¶
Source

emit_subp_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_subps ¶
Source

emit_subps :: emit_subps_r_r_r

emit_subps_r_r_r ¶
Source

emit_subps_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_subs_er ¶
Source

emit_subs_er :: emit_subs_er_r_r_ex

emit_subs_er_r_r_ex ¶
Source

emit_subs_er_r_r_ex :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_ext:     Extend, 
	src2_amount:  u8, 
) {…}

emit_subs_imm ¶
Source

emit_subs_imm :: emit_subs_imm_r_r_i

emit_subs_imm_r_r_i ¶
Source

emit_subs_imm_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_subs_sr ¶
Source

emit_subs_sr :: emit_subs_sr_r_r_sh

emit_subs_sr_r_r_sh ¶
Source

emit_subs_sr_r_r_sh :: proc(
	instructions: ^[dynamic]Instruction, 
	dst:          Register, 
	src:          Register, 
	src2:         Register, 
	src2_shift:   Shift_Type, 
	src2_amount:  u8, 
) {…}

emit_svc ¶
Source

emit_svc :: emit_svc_i

emit_svc_i ¶
Source

emit_svc_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_sve_abs_pred ¶
Source

emit_sve_abs_pred :: emit_sve_abs_pred_z_p_z

emit_sve_abs_pred_z_p_z ¶
Source

emit_sve_abs_pred_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_adclb ¶
Source

emit_sve_adclb :: emit_sve_adclb_z_z_z

emit_sve_adclb_z_z_z ¶
Source

emit_sve_adclb_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_adclt ¶
Source

emit_sve_adclt :: emit_sve_adclt_z_z_z

emit_sve_adclt_z_z_z ¶
Source

emit_sve_adclt_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_add_pred ¶
Source

emit_sve_add_pred :: emit_sve_add_pred_z_p_z_z

emit_sve_add_pred_z_p_z_z ¶
Source

emit_sve_add_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_add_z ¶
Source

emit_sve_add_z :: emit_sve_add_z_z_z_z

emit_sve_add_z_z_z_z ¶
Source

emit_sve_add_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_aesd ¶
Source

emit_sve_aesd :: emit_sve_aesd_z_z

emit_sve_aesd_z_z ¶
Source

emit_sve_aesd_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) {…}

emit_sve_aese ¶
Source

emit_sve_aese :: emit_sve_aese_z_z

emit_sve_aese_z_z ¶
Source

emit_sve_aese_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) {…}

emit_sve_aesimc ¶
Source

emit_sve_aesimc :: emit_sve_aesimc_z

emit_sve_aesimc_z ¶
Source

emit_sve_aesimc_z :: proc(instructions: ^[dynamic]Instruction, rz: u8) {…}

emit_sve_aesmc ¶
Source

emit_sve_aesmc :: emit_sve_aesmc_z

emit_sve_aesmc_z ¶
Source

emit_sve_aesmc_z :: proc(instructions: ^[dynamic]Instruction, rz: u8) {…}

emit_sve_and_p ¶
Source

emit_sve_and_p :: emit_sve_and_p_p_p_p_p

emit_sve_and_p_p_p_p_p ¶
Source

emit_sve_and_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_and_pred ¶
Source

emit_sve_and_pred :: emit_sve_and_pred_z_p_z_z

emit_sve_and_pred_z_p_z_z ¶
Source

emit_sve_and_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_ands_p ¶
Source

emit_sve_ands_p :: emit_sve_ands_p_p_p_p_p

emit_sve_ands_p_p_p_p_p ¶
Source

emit_sve_ands_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_asr_pred ¶
Source

emit_sve_asr_pred :: emit_sve_asr_pred_z_p_z_z

emit_sve_asr_pred_z_p_z_z ¶
Source

emit_sve_asr_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_asrr_pred ¶
Source

emit_sve_asrr_pred :: emit_sve_asrr_pred_z_p_z_z

emit_sve_asrr_pred_z_p_z_z ¶
Source

emit_sve_asrr_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bcax_z ¶
Source

emit_sve_bcax_z :: emit_sve_bcax_z_z_z_z_z

emit_sve_bcax_z_z_z_z_z ¶
Source

emit_sve_bcax_z_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bfadd ¶
Source

emit_sve_bfadd :: emit_sve_bfadd_z_p_z_z

emit_sve_bfadd_unpred ¶
Source

emit_sve_bfadd_unpred :: emit_sve_bfadd_unpred_z_z_z

emit_sve_bfadd_unpred_z_z_z ¶
Source

emit_sve_bfadd_unpred_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_bfadd_z_p_z_z ¶
Source

emit_sve_bfadd_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bfclamp ¶
Source

emit_sve_bfclamp :: emit_sve_bfclamp_z_z_z

emit_sve_bfclamp_z_z_z ¶
Source

emit_sve_bfclamp_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_bfcvt ¶
Source

emit_sve_bfcvt :: emit_sve_bfcvt_z_p_z

emit_sve_bfcvt_z_p_z ¶
Source

emit_sve_bfcvt_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_bfcvtnt ¶
Source

emit_sve_bfcvtnt :: emit_sve_bfcvtnt_z_p_z

emit_sve_bfcvtnt_z_p_z ¶
Source

emit_sve_bfcvtnt_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_bfmaxnm ¶
Source

emit_sve_bfmaxnm :: emit_sve_bfmaxnm_z_p_z_z

emit_sve_bfmaxnm_z_p_z_z ¶
Source

emit_sve_bfmaxnm_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bfminnm ¶
Source

emit_sve_bfminnm :: emit_sve_bfminnm_z_p_z_z

emit_sve_bfminnm_z_p_z_z ¶
Source

emit_sve_bfminnm_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bfmla ¶
Source

emit_sve_bfmla :: emit_sve_bfmla_z_p_z_z

emit_sve_bfmla_z_p_z_z ¶
Source

emit_sve_bfmla_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bfmls ¶
Source

emit_sve_bfmls :: emit_sve_bfmls_z_p_z_z

emit_sve_bfmls_z_p_z_z ¶
Source

emit_sve_bfmls_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bfmul ¶
Source

emit_sve_bfmul :: emit_sve_bfmul_z_p_z_z

emit_sve_bfmul_unpred ¶
Source

emit_sve_bfmul_unpred :: emit_sve_bfmul_unpred_z_z_z

emit_sve_bfmul_unpred_z_z_z ¶
Source

emit_sve_bfmul_unpred_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_bfmul_z_p_z_z ¶
Source

emit_sve_bfmul_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bfsub ¶
Source

emit_sve_bfsub :: emit_sve_bfsub_z_p_z_z

emit_sve_bfsub_unpred ¶
Source

emit_sve_bfsub_unpred :: emit_sve_bfsub_unpred_z_z_z

emit_sve_bfsub_unpred_z_z_z ¶
Source

emit_sve_bfsub_unpred_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_bfsub_z_p_z_z ¶
Source

emit_sve_bfsub_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bic_p ¶
Source

emit_sve_bic_p :: emit_sve_bic_p_p_p_p_p

emit_sve_bic_p_p_p_p_p ¶
Source

emit_sve_bic_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bic_pred ¶
Source

emit_sve_bic_pred :: emit_sve_bic_pred_z_p_z_z

emit_sve_bic_pred_z_p_z_z ¶
Source

emit_sve_bic_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bics_p ¶
Source

emit_sve_bics_p :: emit_sve_bics_p_p_p_p_p

emit_sve_bics_p_p_p_p_p ¶
Source

emit_sve_bics_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_brka ¶
Source

emit_sve_brka :: emit_sve_brka_p_p_p

emit_sve_brka_p_p_p ¶
Source

emit_sve_brka_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_brkas ¶
Source

emit_sve_brkas :: emit_sve_brkas_p_p_p

emit_sve_brkas_p_p_p ¶
Source

emit_sve_brkas_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_brkb ¶
Source

emit_sve_brkb :: emit_sve_brkb_p_p_p

emit_sve_brkb_p_p_p ¶
Source

emit_sve_brkb_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_brkbs ¶
Source

emit_sve_brkbs :: emit_sve_brkbs_p_p_p

emit_sve_brkbs_p_p_p ¶
Source

emit_sve_brkbs_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_brkn ¶
Source

emit_sve_brkn :: emit_sve_brkn_p_p_p_p

emit_sve_brkn_p_p_p_p ¶
Source

emit_sve_brkn_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_brkpa ¶
Source

emit_sve_brkpa :: emit_sve_brkpa_p_p_p_p

emit_sve_brkpa_p_p_p_p ¶
Source

emit_sve_brkpa_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_brkpb ¶
Source

emit_sve_brkpb :: emit_sve_brkpb_p_p_p_p

emit_sve_brkpb_p_p_p_p ¶
Source

emit_sve_brkpb_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bsl ¶
Source

emit_sve_bsl :: emit_sve_bsl_z_z_z_z

emit_sve_bsl1n ¶
Source

emit_sve_bsl1n :: emit_sve_bsl1n_z_z_z_z

emit_sve_bsl1n_z_z_z_z ¶
Source

emit_sve_bsl1n_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bsl2n ¶
Source

emit_sve_bsl2n :: emit_sve_bsl2n_z_z_z_z

emit_sve_bsl2n_z_z_z_z ¶
Source

emit_sve_bsl2n_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_bsl_z_z_z_z ¶
Source

emit_sve_bsl_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_cls_pred ¶
Source

emit_sve_cls_pred :: emit_sve_cls_pred_z_p_z

emit_sve_cls_pred_z_p_z ¶
Source

emit_sve_cls_pred_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_clz_pred ¶
Source

emit_sve_clz_pred :: emit_sve_clz_pred_z_p_z

emit_sve_clz_pred_z_p_z ¶
Source

emit_sve_clz_pred_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_cmpeq ¶
Source

emit_sve_cmpeq :: emit_sve_cmpeq_p_p_z_z

emit_sve_cmpeq_p_p_z_z ¶
Source

emit_sve_cmpeq_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_cmpge ¶
Source

emit_sve_cmpge :: emit_sve_cmpge_p_p_z_z

emit_sve_cmpge_p_p_z_z ¶
Source

emit_sve_cmpge_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_cmpgt ¶
Source

emit_sve_cmpgt :: emit_sve_cmpgt_p_p_z_z

emit_sve_cmpgt_p_p_z_z ¶
Source

emit_sve_cmpgt_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_cmphi ¶
Source

emit_sve_cmphi :: emit_sve_cmphi_p_p_z_z

emit_sve_cmphi_p_p_z_z ¶
Source

emit_sve_cmphi_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_cmphs ¶
Source

emit_sve_cmphs :: emit_sve_cmphs_p_p_z_z

emit_sve_cmphs_p_p_z_z ¶
Source

emit_sve_cmphs_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_cmple ¶
Source

emit_sve_cmple :: emit_sve_cmple_p_p_z_z

emit_sve_cmple_p_p_z_z ¶
Source

emit_sve_cmple_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_cmplo ¶
Source

emit_sve_cmplo :: emit_sve_cmplo_p_p_z_z

emit_sve_cmplo_p_p_z_z ¶
Source

emit_sve_cmplo_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_cmpls ¶
Source

emit_sve_cmpls :: emit_sve_cmpls_p_p_z_z

emit_sve_cmpls_p_p_z_z ¶
Source

emit_sve_cmpls_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_cmplt ¶
Source

emit_sve_cmplt :: emit_sve_cmplt_p_p_z_z

emit_sve_cmplt_p_p_z_z ¶
Source

emit_sve_cmplt_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_cmpne ¶
Source

emit_sve_cmpne :: emit_sve_cmpne_p_p_z_z

emit_sve_cmpne_p_p_z_z ¶
Source

emit_sve_cmpne_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_cnt_pred ¶
Source

emit_sve_cnt_pred :: emit_sve_cnt_pred_z_p_z

emit_sve_cnt_pred_z_p_z ¶
Source

emit_sve_cnt_pred_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_compact ¶
Source

emit_sve_compact :: emit_sve_compact_z_p_z

emit_sve_compact_z_p_z ¶
Source

emit_sve_compact_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_cpy_z ¶
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emit_sve_cpy_z :: emit_sve_cpy_z_z_p_r

emit_sve_cpy_z_z_p_r ¶
Source

emit_sve_cpy_z_z_p_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) {…}

emit_sve_dup_z ¶
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emit_sve_dup_z :: emit_sve_dup_z_z_r

emit_sve_dup_z_z_r ¶
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emit_sve_dup_z_z_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) {…}

emit_sve_eor3_z ¶
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emit_sve_eor3_z :: emit_sve_eor3_z_z_z_z_z

emit_sve_eor3_z_z_z_z_z ¶
Source

emit_sve_eor3_z_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_eor_p ¶
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emit_sve_eor_p :: emit_sve_eor_p_p_p_p_p

emit_sve_eor_p_p_p_p_p ¶
Source

emit_sve_eor_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_eor_pred ¶
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emit_sve_eor_pred :: emit_sve_eor_pred_z_p_z_z

emit_sve_eor_pred_z_p_z_z ¶
Source

emit_sve_eor_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_eors_p ¶
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emit_sve_eors_p :: emit_sve_eors_p_p_p_p_p

emit_sve_eors_p_p_p_p_p ¶
Source

emit_sve_eors_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_ext ¶
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emit_sve_ext :: emit_sve_ext_z_z_z_i

emit_sve_ext_z ¶
Source

emit_sve_ext_z :: emit_sve_ext_z_z_z_z_i

emit_sve_ext_z_z_z_i ¶
Source

emit_sve_ext_z_z_z_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) {…}

emit_sve_ext_z_z_z_z_i ¶
Source

emit_sve_ext_z_z_z_z_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) {…}

emit_sve_fabs_z ¶
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emit_sve_fabs_z :: emit_sve_fabs_z_z_p_z

emit_sve_fabs_z_z_p_z ¶
Source

emit_sve_fabs_z_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_fadd_pred ¶
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emit_sve_fadd_pred :: emit_sve_fadd_pred_z_p_z_z

emit_sve_fadd_pred_z_p_z_z ¶
Source

emit_sve_fadd_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fadd_z ¶
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emit_sve_fadd_z :: emit_sve_fadd_z_z_z_z

emit_sve_fadd_z_z_z_z ¶
Source

emit_sve_fadd_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_fcmeq ¶
Source

emit_sve_fcmeq :: emit_sve_fcmeq_p_p_z_z

emit_sve_fcmeq_p_p_z_z ¶
Source

emit_sve_fcmeq_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fcmge ¶
Source

emit_sve_fcmge :: emit_sve_fcmge_p_p_z_z

emit_sve_fcmge_p_p_z_z ¶
Source

emit_sve_fcmge_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fcmgt ¶
Source

emit_sve_fcmgt :: emit_sve_fcmgt_p_p_z_z

emit_sve_fcmgt_p_p_z_z ¶
Source

emit_sve_fcmgt_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fcmle ¶
Source

emit_sve_fcmle :: emit_sve_fcmle_p_p_z

emit_sve_fcmle_p_p_z ¶
Source

emit_sve_fcmle_p_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_fcmlt ¶
Source

emit_sve_fcmlt :: emit_sve_fcmlt_p_p_z

emit_sve_fcmlt_p_p_z ¶
Source

emit_sve_fcmlt_p_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_fcmne ¶
Source

emit_sve_fcmne :: emit_sve_fcmne_p_p_z_z

emit_sve_fcmne_p_p_z_z ¶
Source

emit_sve_fcmne_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fcmuo ¶
Source

emit_sve_fcmuo :: emit_sve_fcmuo_p_p_z_z

emit_sve_fcmuo_p_p_z_z ¶
Source

emit_sve_fcmuo_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fdiv_pred ¶
Source

emit_sve_fdiv_pred :: emit_sve_fdiv_pred_z_p_z_z

emit_sve_fdiv_pred_z_p_z_z ¶
Source

emit_sve_fdiv_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fdivr_pred ¶
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emit_sve_fdivr_pred :: emit_sve_fdivr_pred_z_p_z_z

emit_sve_fdivr_pred_z_p_z_z ¶
Source

emit_sve_fdivr_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fmax_pred ¶
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emit_sve_fmax_pred :: emit_sve_fmax_pred_z_p_z_z

emit_sve_fmax_pred_z_p_z_z ¶
Source

emit_sve_fmax_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fmaxnm_pred ¶
Source

emit_sve_fmaxnm_pred :: emit_sve_fmaxnm_pred_z_p_z_z

emit_sve_fmaxnm_pred_z_p_z_z ¶
Source

emit_sve_fmaxnm_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fmin_pred ¶
Source

emit_sve_fmin_pred :: emit_sve_fmin_pred_z_p_z_z

emit_sve_fmin_pred_z_p_z_z ¶
Source

emit_sve_fmin_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fminnm_pred ¶
Source

emit_sve_fminnm_pred :: emit_sve_fminnm_pred_z_p_z_z

emit_sve_fminnm_pred_z_p_z_z ¶
Source

emit_sve_fminnm_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fmla ¶
Source

emit_sve_fmla :: emit_sve_fmla_z_p_z_z

emit_sve_fmla_idx_d ¶
Source

emit_sve_fmla_idx_d :: emit_sve_fmla_idx_d_z_z_z_i

emit_sve_fmla_idx_d_z_z_z_i ¶
Source

emit_sve_fmla_idx_d_z_z_z_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) {…}

emit_sve_fmla_idx_h ¶
Source

emit_sve_fmla_idx_h :: emit_sve_fmla_idx_h_z_z_z_i

emit_sve_fmla_idx_h_z_z_z_i ¶
Source

emit_sve_fmla_idx_h_z_z_z_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) {…}

emit_sve_fmla_idx_s ¶
Source

emit_sve_fmla_idx_s :: emit_sve_fmla_idx_s_z_z_z_i

emit_sve_fmla_idx_s_z_z_z_i ¶
Source

emit_sve_fmla_idx_s_z_z_z_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) {…}

emit_sve_fmla_z_p_z_z ¶
Source

emit_sve_fmla_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fmls ¶
Source

emit_sve_fmls :: emit_sve_fmls_z_p_z_z

emit_sve_fmls_idx_d ¶
Source

emit_sve_fmls_idx_d :: emit_sve_fmls_idx_d_z_z_z_i

emit_sve_fmls_idx_d_z_z_z_i ¶
Source

emit_sve_fmls_idx_d_z_z_z_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) {…}

emit_sve_fmls_idx_h ¶
Source

emit_sve_fmls_idx_h :: emit_sve_fmls_idx_h_z_z_z_i

emit_sve_fmls_idx_h_z_z_z_i ¶
Source

emit_sve_fmls_idx_h_z_z_z_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) {…}

emit_sve_fmls_idx_s ¶
Source

emit_sve_fmls_idx_s :: emit_sve_fmls_idx_s_z_z_z_i

emit_sve_fmls_idx_s_z_z_z_i ¶
Source

emit_sve_fmls_idx_s_z_z_z_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) {…}

emit_sve_fmls_z_p_z_z ¶
Source

emit_sve_fmls_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fmul_pred ¶
Source

emit_sve_fmul_pred :: emit_sve_fmul_pred_z_p_z_z

emit_sve_fmul_pred_z_p_z_z ¶
Source

emit_sve_fmul_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fmul_z ¶
Source

emit_sve_fmul_z :: emit_sve_fmul_z_z_z_z

emit_sve_fmul_z_z_z_z ¶
Source

emit_sve_fmul_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_fneg_z ¶
Source

emit_sve_fneg_z :: emit_sve_fneg_z_z_p_z

emit_sve_fneg_z_z_p_z ¶
Source

emit_sve_fneg_z_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_fnmla ¶
Source

emit_sve_fnmla :: emit_sve_fnmla_z_p_z_z

emit_sve_fnmla_z_p_z_z ¶
Source

emit_sve_fnmla_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fnmls ¶
Source

emit_sve_fnmls :: emit_sve_fnmls_z_p_z_z

emit_sve_fnmls_z_p_z_z ¶
Source

emit_sve_fnmls_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_frecps ¶
Source

emit_sve_frecps :: emit_sve_frecps_z_z_z

emit_sve_frecps_z_z_z ¶
Source

emit_sve_frecps_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_frecpx_z ¶
Source

emit_sve_frecpx_z :: emit_sve_frecpx_z_z_p_z

emit_sve_frecpx_z_z_p_z ¶
Source

emit_sve_frecpx_z_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_frinta ¶
Source

emit_sve_frinta :: emit_sve_frinta_z_p_z

emit_sve_frinta_z_p_z ¶
Source

emit_sve_frinta_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_frinti ¶
Source

emit_sve_frinti :: emit_sve_frinti_z_p_z

emit_sve_frinti_z_p_z ¶
Source

emit_sve_frinti_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_frintm ¶
Source

emit_sve_frintm :: emit_sve_frintm_z_p_z

emit_sve_frintm_z_p_z ¶
Source

emit_sve_frintm_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_frintn ¶
Source

emit_sve_frintn :: emit_sve_frintn_z_p_z

emit_sve_frintn_z_p_z ¶
Source

emit_sve_frintn_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_frintp ¶
Source

emit_sve_frintp :: emit_sve_frintp_z_p_z

emit_sve_frintp_z_p_z ¶
Source

emit_sve_frintp_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_frintx ¶
Source

emit_sve_frintx :: emit_sve_frintx_z_p_z

emit_sve_frintx_z_p_z ¶
Source

emit_sve_frintx_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_frintz ¶
Source

emit_sve_frintz :: emit_sve_frintz_z_p_z

emit_sve_frintz_z_p_z ¶
Source

emit_sve_frintz_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_frsqrts ¶
Source

emit_sve_frsqrts :: emit_sve_frsqrts_z_z_z

emit_sve_frsqrts_z_z_z ¶
Source

emit_sve_frsqrts_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_fsqrt_z ¶
Source

emit_sve_fsqrt_z :: emit_sve_fsqrt_z_z_p_z

emit_sve_fsqrt_z_z_p_z ¶
Source

emit_sve_fsqrt_z_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_fsub_pred ¶
Source

emit_sve_fsub_pred :: emit_sve_fsub_pred_z_p_z_z

emit_sve_fsub_pred_z_p_z_z ¶
Source

emit_sve_fsub_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_fsub_z ¶
Source

emit_sve_fsub_z :: emit_sve_fsub_z_z_z_z

emit_sve_fsub_z_z_z_z ¶
Source

emit_sve_fsub_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_fsubr_pred ¶
Source

emit_sve_fsubr_pred :: emit_sve_fsubr_pred_z_p_z_z

emit_sve_fsubr_pred_z_p_z_z ¶
Source

emit_sve_fsubr_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_ftsmul ¶
Source

emit_sve_ftsmul :: emit_sve_ftsmul_z_z_z

emit_sve_ftsmul_z_z_z ¶
Source

emit_sve_ftsmul_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_histcnt ¶
Source

emit_sve_histcnt :: emit_sve_histcnt_z_p_z_z

emit_sve_histcnt_z_p_z_z ¶
Source

emit_sve_histcnt_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_histseg ¶
Source

emit_sve_histseg :: emit_sve_histseg_z_z_z

emit_sve_histseg_z_z_z ¶
Source

emit_sve_histseg_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_index_ii ¶
Source

emit_sve_index_ii :: emit_sve_index_ii_z_i_i

emit_sve_index_ii_z_i_i ¶
Source

emit_sve_index_ii_z_i_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) {…}

emit_sve_index_ir ¶
Source

emit_sve_index_ir :: emit_sve_index_ir_z_i_r

emit_sve_index_ir_z_i_r ¶
Source

emit_sve_index_ir_z_i_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) {…}

emit_sve_index_ri ¶
Source

emit_sve_index_ri :: emit_sve_index_ri_z_r_i

emit_sve_index_ri_z_r_i ¶
Source

emit_sve_index_ri_z_r_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) {…}

emit_sve_index_rr ¶
Source

emit_sve_index_rr :: emit_sve_index_rr_z_r_r

emit_sve_index_rr_z_r_r ¶
Source

emit_sve_index_rr_z_r_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) {…}

emit_sve_insr ¶
Source

emit_sve_insr :: emit_sve_insr_z_r

emit_sve_insr_z_r ¶
Source

emit_sve_insr_z_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) {…}

emit_sve_ld1b ¶
Source

emit_sve_ld1b :: emit_sve_ld1b_z_p_m

emit_sve_ld1b_gather_d ¶
Source

emit_sve_ld1b_gather_d :: emit_sve_ld1b_gather_d_z_p_m

emit_sve_ld1b_gather_d_z_p_m ¶
Source

emit_sve_ld1b_gather_d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1b_gather_s ¶
Source

emit_sve_ld1b_gather_s :: emit_sve_ld1b_gather_s_z_p_m

emit_sve_ld1b_gather_s_z_p_m ¶
Source

emit_sve_ld1b_gather_s_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1b_z_p_m ¶
Source

emit_sve_ld1b_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1d ¶
Source

emit_sve_ld1d :: emit_sve_ld1d_z_p_m

emit_sve_ld1d_gather_d ¶
Source

emit_sve_ld1d_gather_d :: emit_sve_ld1d_gather_d_z_p_m

emit_sve_ld1d_gather_d_z_p_m ¶
Source

emit_sve_ld1d_gather_d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1d_z_p_m ¶
Source

emit_sve_ld1d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1h ¶
Source

emit_sve_ld1h :: emit_sve_ld1h_z_p_m

emit_sve_ld1h_gather_d ¶
Source

emit_sve_ld1h_gather_d :: emit_sve_ld1h_gather_d_z_p_m

emit_sve_ld1h_gather_d_z_p_m ¶
Source

emit_sve_ld1h_gather_d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1h_gather_s ¶
Source

emit_sve_ld1h_gather_s :: emit_sve_ld1h_gather_s_z_p_m

emit_sve_ld1h_gather_s_z_p_m ¶
Source

emit_sve_ld1h_gather_s_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1h_z_p_m ¶
Source

emit_sve_ld1h_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1sb ¶
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emit_sve_ld1sb :: emit_sve_ld1sb_z_p_m

emit_sve_ld1sb_gather_d ¶
Source

emit_sve_ld1sb_gather_d :: emit_sve_ld1sb_gather_d_z_p_m

emit_sve_ld1sb_gather_d_z_p_m ¶
Source

emit_sve_ld1sb_gather_d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1sb_gather_s ¶
Source

emit_sve_ld1sb_gather_s :: emit_sve_ld1sb_gather_s_z_p_m

emit_sve_ld1sb_gather_s_z_p_m ¶
Source

emit_sve_ld1sb_gather_s_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1sb_z_p_m ¶
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emit_sve_ld1sb_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1sh ¶
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emit_sve_ld1sh :: emit_sve_ld1sh_z_p_m

emit_sve_ld1sh_gather_d ¶
Source

emit_sve_ld1sh_gather_d :: emit_sve_ld1sh_gather_d_z_p_m

emit_sve_ld1sh_gather_d_z_p_m ¶
Source

emit_sve_ld1sh_gather_d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1sh_gather_s ¶
Source

emit_sve_ld1sh_gather_s :: emit_sve_ld1sh_gather_s_z_p_m

emit_sve_ld1sh_gather_s_z_p_m ¶
Source

emit_sve_ld1sh_gather_s_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1sh_z_p_m ¶
Source

emit_sve_ld1sh_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1sw ¶
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emit_sve_ld1sw :: emit_sve_ld1sw_z_p_m

emit_sve_ld1sw_gather_d ¶
Source

emit_sve_ld1sw_gather_d :: emit_sve_ld1sw_gather_d_z_p_m

emit_sve_ld1sw_gather_d_z_p_m ¶
Source

emit_sve_ld1sw_gather_d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1sw_z_p_m ¶
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emit_sve_ld1sw_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1w ¶
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emit_sve_ld1w :: emit_sve_ld1w_z_p_m

emit_sve_ld1w_gather_d ¶
Source

emit_sve_ld1w_gather_d :: emit_sve_ld1w_gather_d_z_p_m

emit_sve_ld1w_gather_d_z_p_m ¶
Source

emit_sve_ld1w_gather_d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1w_gather_s ¶
Source

emit_sve_ld1w_gather_s :: emit_sve_ld1w_gather_s_z_p_m

emit_sve_ld1w_gather_s_z_p_m ¶
Source

emit_sve_ld1w_gather_s_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ld1w_z_p_m ¶
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emit_sve_ld1w_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ldff1b ¶
Source

emit_sve_ldff1b :: emit_sve_ldff1b_z_p_m

emit_sve_ldff1b_z_p_m ¶
Source

emit_sve_ldff1b_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ldff1d ¶
Source

emit_sve_ldff1d :: emit_sve_ldff1d_z_p_m

emit_sve_ldff1d_z_p_m ¶
Source

emit_sve_ldff1d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ldff1h ¶
Source

emit_sve_ldff1h :: emit_sve_ldff1h_z_p_m

emit_sve_ldff1h_z_p_m ¶
Source

emit_sve_ldff1h_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ldff1w ¶
Source

emit_sve_ldff1w :: emit_sve_ldff1w_z_p_m

emit_sve_ldff1w_z_p_m ¶
Source

emit_sve_ldff1w_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ldnt1b ¶
Source

emit_sve_ldnt1b :: emit_sve_ldnt1b_z_p_m

emit_sve_ldnt1b_z_p_m ¶
Source

emit_sve_ldnt1b_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ldnt1d ¶
Source

emit_sve_ldnt1d :: emit_sve_ldnt1d_z_p_m

emit_sve_ldnt1d_z_p_m ¶
Source

emit_sve_ldnt1d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ldnt1h ¶
Source

emit_sve_ldnt1h :: emit_sve_ldnt1h_z_p_m

emit_sve_ldnt1h_z_p_m ¶
Source

emit_sve_ldnt1h_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ldnt1w ¶
Source

emit_sve_ldnt1w :: emit_sve_ldnt1w_z_p_m

emit_sve_ldnt1w_z_p_m ¶
Source

emit_sve_ldnt1w_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_ldr_p ¶
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emit_sve_ldr_p :: emit_sve_ldr_p_p_m

emit_sve_ldr_p_p_m ¶
Source

emit_sve_ldr_p_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) {…}

emit_sve_ldr_z ¶
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emit_sve_ldr_z :: emit_sve_ldr_z_z_m

emit_sve_ldr_z_z_m ¶
Source

emit_sve_ldr_z_z_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) {…}

emit_sve_lsl_pred ¶
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emit_sve_lsl_pred :: emit_sve_lsl_pred_z_p_z_z

emit_sve_lsl_pred_z_p_z_z ¶
Source

emit_sve_lsl_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_lslr_pred ¶
Source

emit_sve_lslr_pred :: emit_sve_lslr_pred_z_p_z_z

emit_sve_lslr_pred_z_p_z_z ¶
Source

emit_sve_lslr_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_lsr_pred ¶
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emit_sve_lsr_pred :: emit_sve_lsr_pred_z_p_z_z

emit_sve_lsr_pred_z_p_z_z ¶
Source

emit_sve_lsr_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_lsrr_pred ¶
Source

emit_sve_lsrr_pred :: emit_sve_lsrr_pred_z_p_z_z

emit_sve_lsrr_pred_z_p_z_z ¶
Source

emit_sve_lsrr_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_match ¶
Source

emit_sve_match :: emit_sve_match_p_p_z_z

emit_sve_match_p_p_z_z ¶
Source

emit_sve_match_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_mov_p_p_p ¶
Source

emit_sve_mov_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) {…}

Related Procedure Groups

emit_sve_mov_p

emit_sve_mov_p_p_p_p ¶
Source

emit_sve_mov_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

Related Procedure Groups

emit_sve_mov_p

emit_sve_mov_pred ¶
Source

emit_sve_mov_pred :: emit_sve_mov_pred_z_p_z

emit_sve_mov_pred_z_p_z ¶
Source

emit_sve_mov_pred_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_movs_p ¶
Source

emit_sve_movs_p :: emit_sve_movs_p_p_p_p

emit_sve_movs_p_p_p_p ¶
Source

emit_sve_movs_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_mul_pred ¶
Source

emit_sve_mul_pred :: emit_sve_mul_pred_z_p_z_z

emit_sve_mul_pred_z_p_z_z ¶
Source

emit_sve_mul_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_nand_p ¶
Source

emit_sve_nand_p :: emit_sve_nand_p_p_p_p_p

emit_sve_nand_p_p_p_p_p ¶
Source

emit_sve_nand_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_nands_p ¶
Source

emit_sve_nands_p :: emit_sve_nands_p_p_p_p_p

emit_sve_nands_p_p_p_p_p ¶
Source

emit_sve_nands_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_nbsl ¶
Source

emit_sve_nbsl :: emit_sve_nbsl_z_z_z_z

emit_sve_nbsl_z_z_z_z ¶
Source

emit_sve_nbsl_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_neg_pred ¶
Source

emit_sve_neg_pred :: emit_sve_neg_pred_z_p_z

emit_sve_neg_pred_z_p_z ¶
Source

emit_sve_neg_pred_z_p_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_nmatch ¶
Source

emit_sve_nmatch :: emit_sve_nmatch_p_p_z_z

emit_sve_nmatch_p_p_z_z ¶
Source

emit_sve_nmatch_p_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_nor_p ¶
Source

emit_sve_nor_p :: emit_sve_nor_p_p_p_p_p

emit_sve_nor_p_p_p_p_p ¶
Source

emit_sve_nor_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_nors_p ¶
Source

emit_sve_nors_p :: emit_sve_nors_p_p_p_p_p

emit_sve_nors_p_p_p_p_p ¶
Source

emit_sve_nors_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_not_p ¶
Source

emit_sve_not_p :: emit_sve_not_p_p_p_p

emit_sve_not_p_p_p_p ¶
Source

emit_sve_not_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_orn_p ¶
Source

emit_sve_orn_p :: emit_sve_orn_p_p_p_p_p

emit_sve_orn_p_p_p_p_p ¶
Source

emit_sve_orn_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_orns_p ¶
Source

emit_sve_orns_p :: emit_sve_orns_p_p_p_p_p

emit_sve_orns_p_p_p_p_p ¶
Source

emit_sve_orns_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_orr_p ¶
Source

emit_sve_orr_p :: emit_sve_orr_p_p_p_p_p

emit_sve_orr_p_p_p_p_p ¶
Source

emit_sve_orr_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_orr_pred ¶
Source

emit_sve_orr_pred :: emit_sve_orr_pred_z_p_z_z

emit_sve_orr_pred_z_p_z_z ¶
Source

emit_sve_orr_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_orrs_p ¶
Source

emit_sve_orrs_p :: emit_sve_orrs_p_p_p_p_p

emit_sve_orrs_p_p_p_p_p ¶
Source

emit_sve_orrs_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_pfalse ¶
Source

emit_sve_pfalse :: emit_sve_pfalse_p

emit_sve_pfalse_p ¶
Source

emit_sve_pfalse_p :: proc(instructions: ^[dynamic]Instruction, rz: u8) {…}

emit_sve_pfirst ¶
Source

emit_sve_pfirst :: emit_sve_pfirst_p_p_p

emit_sve_pfirst_p_p_p ¶
Source

emit_sve_pfirst_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_pmul_vec ¶
Source

emit_sve_pmul_vec :: emit_sve_pmul_vec_z_z_z

emit_sve_pmul_vec_z_z_z ¶
Source

emit_sve_pmul_vec_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_pmullb ¶
Source

emit_sve_pmullb :: emit_sve_pmullb_z_z_z

emit_sve_pmullb_z_z_z ¶
Source

emit_sve_pmullb_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_pmullt ¶
Source

emit_sve_pmullt :: emit_sve_pmullt_z_z_z

emit_sve_pmullt_z_z_z ¶
Source

emit_sve_pmullt_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_pnext ¶
Source

emit_sve_pnext :: emit_sve_pnext_p_p_p

emit_sve_pnext_p_p_p ¶
Source

emit_sve_pnext_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_prfb ¶
Source

emit_sve_prfb :: emit_sve_prfb_i_p_m

emit_sve_prfb_i_p_m ¶
Source

emit_sve_prfb_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sve_prfd ¶
Source

emit_sve_prfd :: emit_sve_prfd_i_p_m

emit_sve_prfd_i_p_m ¶
Source

emit_sve_prfd_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sve_prfh ¶
Source

emit_sve_prfh :: emit_sve_prfh_i_p_m

emit_sve_prfh_i_p_m ¶
Source

emit_sve_prfh_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sve_prfw ¶
Source

emit_sve_prfw :: emit_sve_prfw_i_p_m

emit_sve_prfw_i_p_m ¶
Source

emit_sve_prfw_i_p_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) {…}

emit_sve_ptrue ¶
Source

emit_sve_ptrue :: emit_sve_ptrue_p_i

emit_sve_ptrue_p_i ¶
Source

emit_sve_ptrue_p_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) {…}

emit_sve_ptrues ¶
Source

emit_sve_ptrues :: emit_sve_ptrues_p_i

emit_sve_ptrues_p_i ¶
Source

emit_sve_ptrues_p_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) {…}

emit_sve_rdffr ¶
Source

emit_sve_rdffr :: emit_sve_rdffr_p

emit_sve_rdffr_p ¶
Source

emit_sve_rdffr_p :: proc(instructions: ^[dynamic]Instruction, rz: u8) {…}

emit_sve_rev_p ¶
Source

emit_sve_rev_p :: emit_sve_rev_p_p_p

emit_sve_rev_p_p_p ¶
Source

emit_sve_rev_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) {…}

emit_sve_rev_z ¶
Source

emit_sve_rev_z :: emit_sve_rev_z_z_z

emit_sve_rev_z_z_z ¶
Source

emit_sve_rev_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) {…}

emit_sve_sabd_pred ¶
Source

emit_sve_sabd_pred :: emit_sve_sabd_pred_z_p_z_z

emit_sve_sabd_pred_z_p_z_z ¶
Source

emit_sve_sabd_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_sbclb ¶
Source

emit_sve_sbclb :: emit_sve_sbclb_z_z_z

emit_sve_sbclb_z_z_z ¶
Source

emit_sve_sbclb_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_sbclt ¶
Source

emit_sve_sbclt :: emit_sve_sbclt_z_z_z

emit_sve_sbclt_z_z_z ¶
Source

emit_sve_sbclt_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_sdiv_pred ¶
Source

emit_sve_sdiv_pred :: emit_sve_sdiv_pred_z_p_z_z

emit_sve_sdiv_pred_z_p_z_z ¶
Source

emit_sve_sdiv_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_sel_p ¶
Source

emit_sve_sel_p :: emit_sve_sel_p_p_p_p_p

emit_sve_sel_p_p_p_p_p ¶
Source

emit_sve_sel_p_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_setffr ¶
Source

emit_sve_setffr :: emit_sve_setffr_none

emit_sve_setffr_none ¶
Source

emit_sve_setffr_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_sve_smax_pred ¶
Source

emit_sve_smax_pred :: emit_sve_smax_pred_z_p_z_z

emit_sve_smax_pred_z_p_z_z ¶
Source

emit_sve_smax_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_smin_pred ¶
Source

emit_sve_smin_pred :: emit_sve_smin_pred_z_p_z_z

emit_sve_smin_pred_z_p_z_z ¶
Source

emit_sve_smin_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_smulh_pred ¶
Source

emit_sve_smulh_pred :: emit_sve_smulh_pred_z_p_z_z

emit_sve_smulh_pred_z_p_z_z ¶
Source

emit_sve_smulh_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_splice ¶
Source

emit_sve_splice :: emit_sve_splice_z_p_z_z

emit_sve_splice_z_p_z_z ¶
Source

emit_sve_splice_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_sqadd_z ¶
Source

emit_sve_sqadd_z :: emit_sve_sqadd_z_z_z_z

emit_sve_sqadd_z_z_z_z ¶
Source

emit_sve_sqadd_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_sqrdmlah ¶
Source

emit_sve_sqrdmlah :: emit_sve_sqrdmlah_z_z_z

emit_sve_sqrdmlah_z_z_z ¶
Source

emit_sve_sqrdmlah_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_sqrdmlsh ¶
Source

emit_sve_sqrdmlsh :: emit_sve_sqrdmlsh_z_z_z

emit_sve_sqrdmlsh_z_z_z ¶
Source

emit_sve_sqrdmlsh_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_sqsub_z ¶
Source

emit_sve_sqsub_z :: emit_sve_sqsub_z_z_z_z

emit_sve_sqsub_z_z_z_z ¶
Source

emit_sve_sqsub_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_st1b ¶
Source

emit_sve_st1b :: emit_sve_st1b_z_p_m

emit_sve_st1b_scatter_d ¶
Source

emit_sve_st1b_scatter_d :: emit_sve_st1b_scatter_d_z_p_m

emit_sve_st1b_scatter_d_z_p_m ¶
Source

emit_sve_st1b_scatter_d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_st1b_scatter_s ¶
Source

emit_sve_st1b_scatter_s :: emit_sve_st1b_scatter_s_z_p_m

emit_sve_st1b_scatter_s_z_p_m ¶
Source

emit_sve_st1b_scatter_s_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_st1b_z_p_m ¶
Source

emit_sve_st1b_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_st1d ¶
Source

emit_sve_st1d :: emit_sve_st1d_z_p_m

emit_sve_st1d_scatter_d ¶
Source

emit_sve_st1d_scatter_d :: emit_sve_st1d_scatter_d_z_p_m

emit_sve_st1d_scatter_d_z_p_m ¶
Source

emit_sve_st1d_scatter_d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_st1d_z_p_m ¶
Source

emit_sve_st1d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_st1h ¶
Source

emit_sve_st1h :: emit_sve_st1h_z_p_m

emit_sve_st1h_scatter_d ¶
Source

emit_sve_st1h_scatter_d :: emit_sve_st1h_scatter_d_z_p_m

emit_sve_st1h_scatter_d_z_p_m ¶
Source

emit_sve_st1h_scatter_d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_st1h_scatter_s ¶
Source

emit_sve_st1h_scatter_s :: emit_sve_st1h_scatter_s_z_p_m

emit_sve_st1h_scatter_s_z_p_m ¶
Source

emit_sve_st1h_scatter_s_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_st1h_z_p_m ¶
Source

emit_sve_st1h_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_st1w ¶
Source

emit_sve_st1w :: emit_sve_st1w_z_p_m

emit_sve_st1w_scatter_d ¶
Source

emit_sve_st1w_scatter_d :: emit_sve_st1w_scatter_d_z_p_m

emit_sve_st1w_scatter_d_z_p_m ¶
Source

emit_sve_st1w_scatter_d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_st1w_scatter_s ¶
Source

emit_sve_st1w_scatter_s :: emit_sve_st1w_scatter_s_z_p_m

emit_sve_st1w_scatter_s_z_p_m ¶
Source

emit_sve_st1w_scatter_s_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_st1w_z_p_m ¶
Source

emit_sve_st1w_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_stnt1b ¶
Source

emit_sve_stnt1b :: emit_sve_stnt1b_z_p_m

emit_sve_stnt1b_z_p_m ¶
Source

emit_sve_stnt1b_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_stnt1d ¶
Source

emit_sve_stnt1d :: emit_sve_stnt1d_z_p_m

emit_sve_stnt1d_z_p_m ¶
Source

emit_sve_stnt1d_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_stnt1h ¶
Source

emit_sve_stnt1h :: emit_sve_stnt1h_z_p_m

emit_sve_stnt1h_z_p_m ¶
Source

emit_sve_stnt1h_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_stnt1w ¶
Source

emit_sve_stnt1w :: emit_sve_stnt1w_z_p_m

emit_sve_stnt1w_z_p_m ¶
Source

emit_sve_stnt1w_z_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) {…}

emit_sve_str_p ¶
Source

emit_sve_str_p :: emit_sve_str_p_p_m

emit_sve_str_p_p_m ¶
Source

emit_sve_str_p_p_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) {…}

emit_sve_str_z ¶
Source

emit_sve_str_z :: emit_sve_str_z_z_m

emit_sve_str_z_z_m ¶
Source

emit_sve_str_z_z_m :: proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) {…}

emit_sve_sub_pred ¶
Source

emit_sve_sub_pred :: emit_sve_sub_pred_z_p_z_z

emit_sve_sub_pred_z_p_z_z ¶
Source

emit_sve_sub_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_sub_z ¶
Source

emit_sve_sub_z :: emit_sve_sub_z_z_z_z

emit_sve_sub_z_z_z_z ¶
Source

emit_sve_sub_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_subr_pred ¶
Source

emit_sve_subr_pred :: emit_sve_subr_pred_z_p_z_z

emit_sve_subr_pred_z_p_z_z ¶
Source

emit_sve_subr_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_tbl ¶
Source

emit_sve_tbl :: emit_sve_tbl_z_z_z

emit_sve_tbl2 ¶
Source

emit_sve_tbl2 :: emit_sve_tbl2_z_z_z

emit_sve_tbl2_z_z_z ¶
Source

emit_sve_tbl2_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_tbl_z_z_z ¶
Source

emit_sve_tbl_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_tbx ¶
Source

emit_sve_tbx :: emit_sve_tbx_z_z_z

emit_sve_tbx_z_z_z ¶
Source

emit_sve_tbx_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_trn1_p ¶
Source

emit_sve_trn1_p :: emit_sve_trn1_p_p_p_p

emit_sve_trn1_p_p_p_p ¶
Source

emit_sve_trn1_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_trn1_z ¶
Source

emit_sve_trn1_z :: emit_sve_trn1_z_z_z_z

emit_sve_trn1_z_z_z_z ¶
Source

emit_sve_trn1_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_trn2_p ¶
Source

emit_sve_trn2_p :: emit_sve_trn2_p_p_p_p

emit_sve_trn2_p_p_p_p ¶
Source

emit_sve_trn2_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_trn2_z ¶
Source

emit_sve_trn2_z :: emit_sve_trn2_z_z_z_z

emit_sve_trn2_z_z_z_z ¶
Source

emit_sve_trn2_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_uabd_pred ¶
Source

emit_sve_uabd_pred :: emit_sve_uabd_pred_z_p_z_z

emit_sve_uabd_pred_z_p_z_z ¶
Source

emit_sve_uabd_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_udiv_pred ¶
Source

emit_sve_udiv_pred :: emit_sve_udiv_pred_z_p_z_z

emit_sve_udiv_pred_z_p_z_z ¶
Source

emit_sve_udiv_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_umax_pred ¶
Source

emit_sve_umax_pred :: emit_sve_umax_pred_z_p_z_z

emit_sve_umax_pred_z_p_z_z ¶
Source

emit_sve_umax_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_umin_pred ¶
Source

emit_sve_umin_pred :: emit_sve_umin_pred_z_p_z_z

emit_sve_umin_pred_z_p_z_z ¶
Source

emit_sve_umin_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_umulh_pred ¶
Source

emit_sve_umulh_pred :: emit_sve_umulh_pred_z_p_z_z

emit_sve_umulh_pred_z_p_z_z ¶
Source

emit_sve_umulh_pred_z_p_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) {…}

emit_sve_uqadd_z ¶
Source

emit_sve_uqadd_z :: emit_sve_uqadd_z_z_z_z

emit_sve_uqadd_z_z_z_z ¶
Source

emit_sve_uqadd_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_uqsub_z ¶
Source

emit_sve_uqsub_z :: emit_sve_uqsub_z_z_z_z

emit_sve_uqsub_z_z_z_z ¶
Source

emit_sve_uqsub_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_uzp1_p ¶
Source

emit_sve_uzp1_p :: emit_sve_uzp1_p_p_p_p

emit_sve_uzp1_p_p_p_p ¶
Source

emit_sve_uzp1_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_uzp1_z ¶
Source

emit_sve_uzp1_z :: emit_sve_uzp1_z_z_z_z

emit_sve_uzp1_z_z_z_z ¶
Source

emit_sve_uzp1_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_uzp2_p ¶
Source

emit_sve_uzp2_p :: emit_sve_uzp2_p_p_p_p

emit_sve_uzp2_p_p_p_p ¶
Source

emit_sve_uzp2_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_uzp2_z ¶
Source

emit_sve_uzp2_z :: emit_sve_uzp2_z_z_z_z

emit_sve_uzp2_z_z_z_z ¶
Source

emit_sve_uzp2_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_whilege ¶
Source

emit_sve_whilege :: emit_sve_whilege_p_r_r

emit_sve_whilege_p_r_r ¶
Source

emit_sve_whilege_p_r_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) {…}

emit_sve_whilegt ¶
Source

emit_sve_whilegt :: emit_sve_whilegt_p_r_r

emit_sve_whilegt_p_r_r ¶
Source

emit_sve_whilegt_p_r_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) {…}

emit_sve_whilehi ¶
Source

emit_sve_whilehi :: emit_sve_whilehi_p_r_r

emit_sve_whilehi_p_r_r ¶
Source

emit_sve_whilehi_p_r_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) {…}

emit_sve_whilehs ¶
Source

emit_sve_whilehs :: emit_sve_whilehs_p_r_r

emit_sve_whilehs_p_r_r ¶
Source

emit_sve_whilehs_p_r_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) {…}

emit_sve_whilele ¶
Source

emit_sve_whilele :: emit_sve_whilele_p_r_r

emit_sve_whilele_p_r_r ¶
Source

emit_sve_whilele_p_r_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) {…}

emit_sve_whilelo ¶
Source

emit_sve_whilelo :: emit_sve_whilelo_p_r_r

emit_sve_whilelo_p_r_r ¶
Source

emit_sve_whilelo_p_r_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) {…}

emit_sve_whilels ¶
Source

emit_sve_whilels :: emit_sve_whilels_p_r_r

emit_sve_whilels_p_r_r ¶
Source

emit_sve_whilels_p_r_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) {…}

emit_sve_whilelt ¶
Source

emit_sve_whilelt :: emit_sve_whilelt_p_r_r

emit_sve_whilelt_p_r_r ¶
Source

emit_sve_whilelt_p_r_r :: proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) {…}

emit_sve_wrffr ¶
Source

emit_sve_wrffr :: emit_sve_wrffr_p

emit_sve_wrffr_p ¶
Source

emit_sve_wrffr_p :: proc(instructions: ^[dynamic]Instruction, rz: u8) {…}

emit_sve_xar_z ¶
Source

emit_sve_xar_z :: emit_sve_xar_z_z_z_z_i

emit_sve_xar_z_z_z_z_i ¶
Source

emit_sve_xar_z_z_z_z_i :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) {…}

emit_sve_zip1_p ¶
Source

emit_sve_zip1_p :: emit_sve_zip1_p_p_p_p

emit_sve_zip1_p_p_p_p ¶
Source

emit_sve_zip1_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_zip1_z ¶
Source

emit_sve_zip1_z :: emit_sve_zip1_z_z_z_z

emit_sve_zip1_z_z_z_z ¶
Source

emit_sve_zip1_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_zip2_p ¶
Source

emit_sve_zip2_p :: emit_sve_zip2_p_p_p_p

emit_sve_zip2_p_p_p_p ¶
Source

emit_sve_zip2_p_p_p_p :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_sve_zip2_z ¶
Source

emit_sve_zip2_z :: emit_sve_zip2_z_z_z_z

emit_sve_zip2_z_z_z_z ¶
Source

emit_sve_zip2_z_z_z_z :: proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) {…}

emit_swp ¶
Source

emit_swp :: emit_swp_r_r_m

emit_swp_r_r_m ¶
Source

emit_swp_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_swpa ¶
Source

emit_swpa :: emit_swpa_r_r_m

emit_swpa_r_r_m ¶
Source

emit_swpa_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_swpal ¶
Source

emit_swpal :: emit_swpal_r_r_m

emit_swpal_r_r_m ¶
Source

emit_swpal_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_swpl ¶
Source

emit_swpl :: emit_swpl_r_r_m

emit_swpl_r_r_m ¶
Source

emit_swpl_r_r_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) {…}

emit_sxtb ¶
Source

emit_sxtb :: emit_sxtb_r_r

emit_sxtb_r_r ¶
Source

emit_sxtb_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sxth ¶
Source

emit_sxth :: emit_sxth_r_r

emit_sxth_r_r ¶
Source

emit_sxth_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sxtl ¶
Source

emit_sxtl :: emit_sxtl_r_r

emit_sxtl2 ¶
Source

emit_sxtl2 :: emit_sxtl2_r_r

emit_sxtl2_r_r ¶
Source

emit_sxtl2_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sxtl_r_r ¶
Source

emit_sxtl_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_sxtw ¶
Source

emit_sxtw :: emit_sxtw_r_r

emit_sxtw_r_r ¶
Source

emit_sxtw_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_tbl ¶
Source

emit_tbl :: emit_tbl_r_r_r

emit_tbl_r_r_r ¶
Source

emit_tbl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_tbnz ¶
Source

emit_tbnz :: emit_tbnz_r_i_l

emit_tbnz_r_i_l ¶
Source

emit_tbnz_r_i_l :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) {…}

emit_tbx ¶
Source

emit_tbx :: emit_tbx_r_r_r

emit_tbx_r_r_r ¶
Source

emit_tbx_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_tbz ¶
Source

emit_tbz :: emit_tbz_r_i_l

emit_tbz_r_i_l ¶
Source

emit_tbz_r_i_l :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) {…}

emit_tcancel ¶
Source

emit_tcancel :: emit_tcancel_i

emit_tcancel_i ¶
Source

emit_tcancel_i :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_tcommit ¶
Source

emit_tcommit :: emit_tcommit_none

emit_tcommit_none ¶
Source

emit_tcommit_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_tlbi_alle1 ¶
Source

emit_tlbi_alle1 :: emit_tlbi_alle1_none

emit_tlbi_alle1_none ¶
Source

emit_tlbi_alle1_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_tlbi_alle1is ¶
Source

emit_tlbi_alle1is :: emit_tlbi_alle1is_none

emit_tlbi_alle1is_none ¶
Source

emit_tlbi_alle1is_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_tlbi_alle2 ¶
Source

emit_tlbi_alle2 :: emit_tlbi_alle2_none

emit_tlbi_alle2_none ¶
Source

emit_tlbi_alle2_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_tlbi_alle2is ¶
Source

emit_tlbi_alle2is :: emit_tlbi_alle2is_none

emit_tlbi_alle2is_none ¶
Source

emit_tlbi_alle2is_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_tlbi_alle3 ¶
Source

emit_tlbi_alle3 :: emit_tlbi_alle3_none

emit_tlbi_alle3_none ¶
Source

emit_tlbi_alle3_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_tlbi_alle3is ¶
Source

emit_tlbi_alle3is :: emit_tlbi_alle3is_none

emit_tlbi_alle3is_none ¶
Source

emit_tlbi_alle3is_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_tlbi_aside1 ¶
Source

emit_tlbi_aside1 :: emit_tlbi_aside1_r

emit_tlbi_aside1_r ¶
Source

emit_tlbi_aside1_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_aside1is ¶
Source

emit_tlbi_aside1is :: emit_tlbi_aside1is_r

emit_tlbi_aside1is_r ¶
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emit_tlbi_aside1is_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_paall ¶
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emit_tlbi_paall :: emit_tlbi_paall_none

emit_tlbi_paall_none ¶
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emit_tlbi_paall_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_tlbi_paallos ¶
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emit_tlbi_paallos :: emit_tlbi_paallos_none

emit_tlbi_paallos_none ¶
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emit_tlbi_paallos_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_tlbi_rpalos ¶
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emit_tlbi_rpalos :: emit_tlbi_rpalos_r

emit_tlbi_rpalos_r ¶
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emit_tlbi_rpalos_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_rpaos ¶
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emit_tlbi_rpaos :: emit_tlbi_rpaos_r

emit_tlbi_rpaos_r ¶
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emit_tlbi_rpaos_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_vaae1 ¶
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emit_tlbi_vaae1 :: emit_tlbi_vaae1_r

emit_tlbi_vaae1_r ¶
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emit_tlbi_vaae1_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_vaae1is ¶
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emit_tlbi_vaae1is :: emit_tlbi_vaae1is_r

emit_tlbi_vaae1is_r ¶
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emit_tlbi_vaae1is_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_vaale1 ¶
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emit_tlbi_vaale1 :: emit_tlbi_vaale1_r

emit_tlbi_vaale1_r ¶
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emit_tlbi_vaale1_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_vaale1is ¶
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emit_tlbi_vaale1is :: emit_tlbi_vaale1is_r

emit_tlbi_vaale1is_r ¶
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emit_tlbi_vaale1is_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_vae1 ¶
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emit_tlbi_vae1 :: emit_tlbi_vae1_r

emit_tlbi_vae1_r ¶
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emit_tlbi_vae1_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_vae1is ¶
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emit_tlbi_vae1is :: emit_tlbi_vae1is_r

emit_tlbi_vae1is_r ¶
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emit_tlbi_vae1is_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_vale1 ¶
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emit_tlbi_vale1 :: emit_tlbi_vale1_r

emit_tlbi_vale1_r ¶
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emit_tlbi_vale1_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_vale1is ¶
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emit_tlbi_vale1is :: emit_tlbi_vale1is_r

emit_tlbi_vale1is_r ¶
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emit_tlbi_vale1is_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_tlbi_vmalle1 ¶
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emit_tlbi_vmalle1 :: emit_tlbi_vmalle1_none

emit_tlbi_vmalle1_none ¶
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emit_tlbi_vmalle1_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_tlbi_vmalle1is ¶
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emit_tlbi_vmalle1is :: emit_tlbi_vmalle1is_none

emit_tlbi_vmalle1is_none ¶
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emit_tlbi_vmalle1is_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_trn1 ¶
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emit_trn1 :: emit_trn1_r_r_r

emit_trn1_r_r_r ¶
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emit_trn1_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_trn2 ¶
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emit_trn2 :: emit_trn2_r_r_r

emit_trn2_r_r_r ¶
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emit_trn2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_tsb_csync ¶
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emit_tsb_csync :: emit_tsb_csync_none

emit_tsb_csync_none ¶
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emit_tsb_csync_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_tst_imm ¶
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emit_tst_imm :: emit_tst_imm_r_i

emit_tst_imm_r_i ¶
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emit_tst_imm_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

emit_tst_sr ¶
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emit_tst_sr :: emit_tst_sr_r_sh

emit_tst_sr_r_sh ¶
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emit_tst_sr_r_sh :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) {…}

emit_tstart ¶
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emit_tstart :: emit_tstart_r

emit_tstart_r ¶
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emit_tstart_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_ttest ¶
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emit_ttest :: emit_ttest_r

emit_ttest_r ¶
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emit_ttest_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_uaba ¶
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emit_uaba :: emit_uaba_r_r_r

emit_uaba_r_r_r ¶
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emit_uaba_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uabd ¶
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emit_uabd :: emit_uabd_r_r_r

emit_uabd_r_r_r ¶
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emit_uabd_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uadalp ¶
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emit_uadalp :: emit_uadalp_r_r

emit_uadalp_r_r ¶
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emit_uadalp_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_uaddl ¶
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emit_uaddl :: emit_uaddl_r_r_r

emit_uaddl2 ¶
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emit_uaddl2 :: emit_uaddl2_r_r_r

emit_uaddl2_r_r_r ¶
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emit_uaddl2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uaddl_r_r_r ¶
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emit_uaddl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uaddlp ¶
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emit_uaddlp :: emit_uaddlp_r_r

emit_uaddlp_r_r ¶
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emit_uaddlp_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_uaddlv ¶
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emit_uaddlv :: emit_uaddlv_r_r

emit_uaddlv_r_r ¶
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emit_uaddlv_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_uaddw ¶
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emit_uaddw :: emit_uaddw_r_r_r

emit_uaddw2 ¶
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emit_uaddw2 :: emit_uaddw2_r_r_r

emit_uaddw2_r_r_r ¶
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emit_uaddw2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uaddw_r_r_r ¶
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emit_uaddw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_ucvtf ¶
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emit_ucvtf :: emit_ucvtf_r_r

emit_ucvtf_h ¶
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emit_ucvtf_h :: emit_ucvtf_h_r_r

emit_ucvtf_h_r_r ¶
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emit_ucvtf_h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_ucvtf_r_r ¶
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emit_ucvtf_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_ucvtf_v ¶
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emit_ucvtf_v :: emit_ucvtf_v_r_r

emit_ucvtf_v_r_r ¶
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emit_ucvtf_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_udiv ¶
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emit_udiv :: emit_udiv_r_r_r

emit_udiv_r_r_r ¶
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emit_udiv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_udot ¶
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emit_udot :: emit_udot_r_r_r

emit_udot_r_r_r ¶
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emit_udot_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uhadd ¶
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emit_uhadd :: emit_uhadd_r_r_r

emit_uhadd_r_r_r ¶
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emit_uhadd_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uhsub ¶
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emit_uhsub :: emit_uhsub_r_r_r

emit_uhsub_r_r_r ¶
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emit_uhsub_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_umaddl ¶
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emit_umaddl :: emit_umaddl_r_r_r_r

emit_umaddl_r_r_r_r ¶
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emit_umaddl_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_umax ¶
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emit_umax :: emit_umax_r_r_r

emit_umax_r_r_r ¶
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emit_umax_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_umaxp ¶
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emit_umaxp :: emit_umaxp_r_r_r

emit_umaxp_r_r_r ¶
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emit_umaxp_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_umaxv ¶
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emit_umaxv :: emit_umaxv_r_r

emit_umaxv_r_r ¶
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emit_umaxv_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_umin ¶
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emit_umin :: emit_umin_r_r_r

emit_umin_r_r_r ¶
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emit_umin_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uminp ¶
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emit_uminp :: emit_uminp_r_r_r

emit_uminp_r_r_r ¶
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emit_uminp_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uminv ¶
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emit_uminv :: emit_uminv_r_r

emit_uminv_r_r ¶
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emit_uminv_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_umlal ¶
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emit_umlal :: emit_umlal_r_r_r

emit_umlal2 ¶
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emit_umlal2 :: emit_umlal2_r_r_r

emit_umlal2_r_r_r ¶
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emit_umlal2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_umlal_r_r_r ¶
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emit_umlal_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_umlsl ¶
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emit_umlsl :: emit_umlsl_r_r_r

emit_umlsl2 ¶
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emit_umlsl2 :: emit_umlsl2_r_r_r

emit_umlsl2_r_r_r ¶
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emit_umlsl2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_umlsl_r_r_r ¶
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emit_umlsl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_umsubl ¶
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emit_umsubl :: emit_umsubl_r_r_r_r

emit_umsubl_r_r_r_r ¶
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emit_umsubl_r_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) {…}

emit_umulh ¶
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emit_umulh :: emit_umulh_r_r_r

emit_umulh_r_r_r ¶
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emit_umulh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_umull2_v ¶
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emit_umull2_v :: emit_umull2_v_r_r_r

emit_umull2_v_r_r_r ¶
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emit_umull2_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_umull_v ¶
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emit_umull_v :: emit_umull_v_r_r_r

emit_umull_v_r_r_r ¶
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emit_umull_v_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uqadd ¶
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emit_uqadd :: emit_uqadd_r_r_r

emit_uqadd_r_r_r ¶
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emit_uqadd_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uqrshrn ¶
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emit_uqrshrn :: emit_uqrshrn_r_r_i

emit_uqrshrn2 ¶
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emit_uqrshrn2 :: emit_uqrshrn2_r_r_i

emit_uqrshrn2_r_r_i ¶
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emit_uqrshrn2_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_uqrshrn_r_r_i ¶
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emit_uqrshrn_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_uqshrn ¶
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emit_uqshrn :: emit_uqshrn_r_r_i

emit_uqshrn2 ¶
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emit_uqshrn2 :: emit_uqshrn2_r_r_i

emit_uqshrn2_r_r_i ¶
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emit_uqshrn2_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_uqshrn_r_r_i ¶
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emit_uqshrn_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_uqsub ¶
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emit_uqsub :: emit_uqsub_r_r_r

emit_uqsub_r_r_r ¶
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emit_uqsub_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uqxtn ¶
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emit_uqxtn :: emit_uqxtn_r_r

emit_uqxtn2 ¶
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emit_uqxtn2 :: emit_uqxtn2_r_r

emit_uqxtn2_r_r ¶
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emit_uqxtn2_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_uqxtn_r_r ¶
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emit_uqxtn_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_urecpe_v ¶
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emit_urecpe_v :: emit_urecpe_v_r_r

emit_urecpe_v_r_r ¶
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emit_urecpe_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_urhadd ¶
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emit_urhadd :: emit_urhadd_r_r_r

emit_urhadd_r_r_r ¶
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emit_urhadd_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_urshl ¶
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emit_urshl :: emit_urshl_r_r_r

emit_urshl_r_r_r ¶
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emit_urshl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_urshr ¶
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emit_urshr :: emit_urshr_r_r_i

emit_urshr_r_r_i ¶
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emit_urshr_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_ursqrte_v ¶
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emit_ursqrte_v :: emit_ursqrte_v_r_r

emit_ursqrte_v_r_r ¶
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emit_ursqrte_v_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_ursra ¶
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emit_ursra :: emit_ursra_r_r_i

emit_ursra_r_r_i ¶
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emit_ursra_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_usdot ¶
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emit_usdot :: emit_usdot_r_r_r

emit_usdot_r_r_r ¶
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emit_usdot_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_ushl ¶
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emit_ushl :: emit_ushl_r_r_r

emit_ushl_r_r_r ¶
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emit_ushl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_ushll ¶
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emit_ushll :: emit_ushll_r_r_i

emit_ushll2 ¶
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emit_ushll2 :: emit_ushll2_r_r_i

emit_ushll2_r_r_i ¶
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emit_ushll2_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_ushll_r_r_i ¶
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emit_ushll_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_ushr ¶
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emit_ushr :: emit_ushr_r_r_i

emit_ushr_r_r_i ¶
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emit_ushr_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_usra ¶
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emit_usra :: emit_usra_r_r_i

emit_usra_r_r_i ¶
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emit_usra_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

emit_usubl ¶
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emit_usubl :: emit_usubl_r_r_r

emit_usubl2 ¶
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emit_usubl2 :: emit_usubl2_r_r_r

emit_usubl2_r_r_r ¶
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emit_usubl2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_usubl_r_r_r ¶
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emit_usubl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_usubw ¶
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emit_usubw :: emit_usubw_r_r_r

emit_usubw2 ¶
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emit_usubw2 :: emit_usubw2_r_r_r

emit_usubw2_r_r_r ¶
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emit_usubw2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_usubw_r_r_r ¶
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emit_usubw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uxtb ¶
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emit_uxtb :: emit_uxtb_r_r

emit_uxtb_r_r ¶
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emit_uxtb_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_uxth ¶
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emit_uxth :: emit_uxth_r_r

emit_uxth_r_r ¶
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emit_uxth_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_uxtl ¶
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emit_uxtl :: emit_uxtl_r_r

emit_uxtl2 ¶
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emit_uxtl2 :: emit_uxtl2_r_r

emit_uxtl2_r_r ¶
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emit_uxtl2_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_uxtl_r_r ¶
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emit_uxtl_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_uxtw ¶
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emit_uxtw :: emit_uxtw_r_r

emit_uxtw_r_r ¶
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emit_uxtw_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_uzp1 ¶
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emit_uzp1 :: emit_uzp1_r_r_r

emit_uzp1_r_r_r ¶
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emit_uzp1_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_uzp2 ¶
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emit_uzp2 :: emit_uzp2_r_r_r

emit_uzp2_r_r_r ¶
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emit_uzp2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_wfe ¶
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emit_wfe :: emit_wfe_none

emit_wfe_none ¶
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emit_wfe_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_wfet ¶
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emit_wfet :: emit_wfet_r

emit_wfet_r ¶
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emit_wfet_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_wfi ¶
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emit_wfi :: emit_wfi_none

emit_wfi_none ¶
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emit_wfi_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_wfit ¶
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emit_wfit :: emit_wfit_r

emit_wfit_r ¶
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emit_wfit_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_xar ¶
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emit_xar :: emit_xar_r_r_r_i

emit_xar_r_r_r_i ¶
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emit_xar_r_r_r_i :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) {…}

emit_xpacd ¶
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emit_xpacd :: emit_xpacd_r

emit_xpacd_r ¶
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emit_xpacd_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_xpaci ¶
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emit_xpaci :: emit_xpaci_r

emit_xpaci_r ¶
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emit_xpaci_r :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

emit_xpaclri ¶
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emit_xpaclri :: emit_xpaclri_none

emit_xpaclri_none ¶
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emit_xpaclri_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_xtn ¶
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emit_xtn :: emit_xtn_r_r

emit_xtn2 ¶
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emit_xtn2 :: emit_xtn2_r_r

emit_xtn2_r_r ¶
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emit_xtn2_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_xtn_r_r ¶
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emit_xtn_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

emit_yield ¶
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emit_yield :: emit_yield_none

emit_yield_none ¶
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emit_yield_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_zip1 ¶
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emit_zip1 :: emit_zip1_r_r_r

emit_zip1_r_r_r ¶
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emit_zip1_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

emit_zip2 ¶
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emit_zip2 :: emit_zip2_r_r_r

emit_zip2_r_r_r ¶
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emit_zip2_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

encode ¶
Source

encode :: proc(
	instructions: []Instruction, 
	label_defs:   []rexcode_isa.Label_Definition, 
	code:         []u8, 
	relocs:       ^[dynamic]Relocation, 
	errors:       ^[dynamic]rexcode_isa.Error, 
	endianness:   Endianness = .LITTLE, 
	resolve:      bool = true, 
	base_address: u64 = 0, 
) -> (byte_count: u32, ok: bool) {…}

encode_bitmask_imm ¶
Source

encode_bitmask_imm :: proc "contextless" (value: u64, is_64: bool) -> (n: u8, immr: u8, imms: u8, ok: bool) {…}

encode_bitmask_imm runs the bitmask-immediate algorithm and returns the three component fields (N, immr, imms) along with a success flag.

encode_max_code_size ¶
Source

encode_max_code_size :: proc "contextless" (instructions: []Instruction) -> int {…}

encode_max_relocation_count ¶
Source

encode_max_relocation_count :: proc "contextless" (instructions: []Instruction) -> int {…}

encode_reserve ¶
Source

encode_reserve :: proc(code: ^[dynamic]u8, relocs: ^[dynamic]Relocation, instructions: []Instruction) {…}

Pre-size the caller's encode outputs (code grown by length so code[:] is a valid emit target; relocs reserved by capacity) so the encode hot path never reallocates. Allocates no new buffers; pass nil to skip either array.

fprint ¶
Source

fprint :: proc(
	fd:           ^os.File, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

fprintln ¶
Source

fprintln :: proc(
	fd:           ^os.File, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

h_reg ¶
Source

h_reg :: proc "contextless" (n: u8) -> Register {…}

inst_abs_v ¶
Source

inst_abs_v :: inst_abs_v_r_r

inst_abs_v_r_r ¶
Source

inst_abs_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_adc ¶
Source

inst_adc :: inst_adc_r_r_r

inst_adc_r_r_r ¶
Source

inst_adc_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_adcs ¶
Source

inst_adcs :: inst_adcs_r_r_r

inst_adcs_r_r_r ¶
Source

inst_adcs_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_add_er ¶
Source

inst_add_er :: inst_add_er_r_r_ex

inst_add_er_r_r_ex ¶
Source

inst_add_er_r_r_ex :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction {…}

inst_add_imm ¶
Source

inst_add_imm :: inst_add_imm_r_r_i

inst_add_imm_r_r_i ¶
Source

inst_add_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_add_sr ¶
Source

inst_add_sr :: inst_add_sr_r_r_sh

inst_add_sr_r_r_sh ¶
Source

inst_add_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_add_v ¶
Source

inst_add_v :: inst_add_v_r_r_r

inst_add_v_r_r_r ¶
Source

inst_add_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_addg ¶
Source

inst_addg :: inst_addg_r_r_i_i

inst_addg_r_r_i_i ¶
Source

inst_addg_r_r_i_i :: proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction {…}

inst_addhn ¶
Source

inst_addhn :: inst_addhn_r_r_r

inst_addhn2 ¶
Source

inst_addhn2 :: inst_addhn2_r_r_r

inst_addhn2_r_r_r ¶
Source

inst_addhn2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_addhn_r_r_r ¶
Source

inst_addhn_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_addp_v ¶
Source

inst_addp_v :: inst_addp_v_r_r_r

inst_addp_v_r_r_r ¶
Source

inst_addp_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_adds_er ¶
Source

inst_adds_er :: inst_adds_er_r_r_ex

inst_adds_er_r_r_ex ¶
Source

inst_adds_er_r_r_ex :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction {…}

inst_adds_imm ¶
Source

inst_adds_imm :: inst_adds_imm_r_r_i

inst_adds_imm_r_r_i ¶
Source

inst_adds_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_adds_sr ¶
Source

inst_adds_sr :: inst_adds_sr_r_r_sh

inst_adds_sr_r_r_sh ¶
Source

inst_adds_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_addv ¶
Source

inst_addv :: inst_addv_r_r

inst_addv_r_r ¶
Source

inst_addv_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_adr ¶
Source

inst_adr :: inst_adr_r_l

inst_adr_r_l ¶
Source

inst_adr_r_l :: proc "contextless" (dst: Register, label: u32) -> Instruction {…}

inst_adrp ¶
Source

inst_adrp :: inst_adrp_r_l

inst_adrp_r_l ¶
Source

inst_adrp_r_l :: proc "contextless" (dst: Register, label: u32) -> Instruction {…}

inst_aesd ¶
Source

inst_aesd :: inst_aesd_r_r

inst_aesd_r_r ¶
Source

inst_aesd_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_aese ¶
Source

inst_aese :: inst_aese_r_r

inst_aese_r_r ¶
Source

inst_aese_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_aesimc ¶
Source

inst_aesimc :: inst_aesimc_r_r

inst_aesimc_r_r ¶
Source

inst_aesimc_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_aesmc ¶
Source

inst_aesmc :: inst_aesmc_r_r

inst_aesmc_r_r ¶
Source

inst_aesmc_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_amx_clr ¶
Source

inst_amx_clr :: inst_amx_clr_none

inst_amx_clr_none ¶
Source

inst_amx_clr_none :: proc "contextless" () -> Instruction {…}

inst_amx_extrx ¶
Source

inst_amx_extrx :: inst_amx_extrx_r

inst_amx_extrx_r ¶
Source

inst_amx_extrx_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_extry ¶
Source

inst_amx_extry :: inst_amx_extry_r

inst_amx_extry_r ¶
Source

inst_amx_extry_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_fma16 ¶
Source

inst_amx_fma16 :: inst_amx_fma16_r

inst_amx_fma16_r ¶
Source

inst_amx_fma16_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_fma32 ¶
Source

inst_amx_fma32 :: inst_amx_fma32_r

inst_amx_fma32_r ¶
Source

inst_amx_fma32_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_fma64 ¶
Source

inst_amx_fma64 :: inst_amx_fma64_r

inst_amx_fma64_r ¶
Source

inst_amx_fma64_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_fms16 ¶
Source

inst_amx_fms16 :: inst_amx_fms16_r

inst_amx_fms16_r ¶
Source

inst_amx_fms16_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_fms32 ¶
Source

inst_amx_fms32 :: inst_amx_fms32_r

inst_amx_fms32_r ¶
Source

inst_amx_fms32_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_fms64 ¶
Source

inst_amx_fms64 :: inst_amx_fms64_r

inst_amx_fms64_r ¶
Source

inst_amx_fms64_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_genlut ¶
Source

inst_amx_genlut :: inst_amx_genlut_r

inst_amx_genlut_r ¶
Source

inst_amx_genlut_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_ldx ¶
Source

inst_amx_ldx :: inst_amx_ldx_r

inst_amx_ldx_r ¶
Source

inst_amx_ldx_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_ldy ¶
Source

inst_amx_ldy :: inst_amx_ldy_r

inst_amx_ldy_r ¶
Source

inst_amx_ldy_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_ldz ¶
Source

inst_amx_ldz :: inst_amx_ldz_r

inst_amx_ldz_r ¶
Source

inst_amx_ldz_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_ldzi ¶
Source

inst_amx_ldzi :: inst_amx_ldzi_r

inst_amx_ldzi_r ¶
Source

inst_amx_ldzi_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_mac16 ¶
Source

inst_amx_mac16 :: inst_amx_mac16_r

inst_amx_mac16_r ¶
Source

inst_amx_mac16_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_matfp ¶
Source

inst_amx_matfp :: inst_amx_matfp_r

inst_amx_matfp_r ¶
Source

inst_amx_matfp_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_matint ¶
Source

inst_amx_matint :: inst_amx_matint_r

inst_amx_matint_r ¶
Source

inst_amx_matint_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_set ¶
Source

inst_amx_set :: inst_amx_set_none

inst_amx_set_none ¶
Source

inst_amx_set_none :: proc "contextless" () -> Instruction {…}

inst_amx_stx ¶
Source

inst_amx_stx :: inst_amx_stx_r

inst_amx_stx_r ¶
Source

inst_amx_stx_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_sty ¶
Source

inst_amx_sty :: inst_amx_sty_r

inst_amx_sty_r ¶
Source

inst_amx_sty_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_stz ¶
Source

inst_amx_stz :: inst_amx_stz_r

inst_amx_stz_r ¶
Source

inst_amx_stz_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_stzi ¶
Source

inst_amx_stzi :: inst_amx_stzi_r

inst_amx_stzi_r ¶
Source

inst_amx_stzi_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_vecfp ¶
Source

inst_amx_vecfp :: inst_amx_vecfp_r

inst_amx_vecfp_r ¶
Source

inst_amx_vecfp_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_amx_vecint ¶
Source

inst_amx_vecint :: inst_amx_vecint_r

inst_amx_vecint_r ¶
Source

inst_amx_vecint_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_and_imm ¶
Source

inst_and_imm :: inst_and_imm_r_r_i

inst_and_imm_r_r_i ¶
Source

inst_and_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_and_sr ¶
Source

inst_and_sr :: inst_and_sr_r_r_sh

inst_and_sr_r_r_sh ¶
Source

inst_and_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_and_v ¶
Source

inst_and_v :: inst_and_v_r_r_r

inst_and_v_r_r_r ¶
Source

inst_and_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_ands_imm ¶
Source

inst_ands_imm :: inst_ands_imm_r_r_i

inst_ands_imm_r_r_i ¶
Source

inst_ands_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_ands_sr ¶
Source

inst_ands_sr :: inst_ands_sr_r_r_sh

inst_ands_sr_r_r_sh ¶
Source

inst_ands_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_asr_imm ¶
Source

inst_asr_imm :: inst_asr_imm_r_r_i

inst_asr_imm_r_r_i ¶
Source

inst_asr_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_asrv ¶
Source

inst_asrv :: inst_asrv_r_r_r

inst_asrv_r_r_r ¶
Source

inst_asrv_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_at_s12e0r ¶
Source

inst_at_s12e0r :: inst_at_s12e0r_r

inst_at_s12e0r_r ¶
Source

inst_at_s12e0r_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s12e0w ¶
Source

inst_at_s12e0w :: inst_at_s12e0w_r

inst_at_s12e0w_r ¶
Source

inst_at_s12e0w_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s12e1r ¶
Source

inst_at_s12e1r :: inst_at_s12e1r_r

inst_at_s12e1r_r ¶
Source

inst_at_s12e1r_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s12e1w ¶
Source

inst_at_s12e1w :: inst_at_s12e1w_r

inst_at_s12e1w_r ¶
Source

inst_at_s12e1w_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s1e0r ¶
Source

inst_at_s1e0r :: inst_at_s1e0r_r

inst_at_s1e0r_r ¶
Source

inst_at_s1e0r_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s1e0w ¶
Source

inst_at_s1e0w :: inst_at_s1e0w_r

inst_at_s1e0w_r ¶
Source

inst_at_s1e0w_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s1e1a ¶
Source

inst_at_s1e1a :: inst_at_s1e1a_r

inst_at_s1e1a_r ¶
Source

inst_at_s1e1a_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s1e1r ¶
Source

inst_at_s1e1r :: inst_at_s1e1r_r

inst_at_s1e1r_r ¶
Source

inst_at_s1e1r_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s1e1w ¶
Source

inst_at_s1e1w :: inst_at_s1e1w_r

inst_at_s1e1w_r ¶
Source

inst_at_s1e1w_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s1e2r ¶
Source

inst_at_s1e2r :: inst_at_s1e2r_r

inst_at_s1e2r_r ¶
Source

inst_at_s1e2r_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s1e2w ¶
Source

inst_at_s1e2w :: inst_at_s1e2w_r

inst_at_s1e2w_r ¶
Source

inst_at_s1e2w_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s1e3r ¶
Source

inst_at_s1e3r :: inst_at_s1e3r_r

inst_at_s1e3r_r ¶
Source

inst_at_s1e3r_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_at_s1e3w ¶
Source

inst_at_s1e3w :: inst_at_s1e3w_r

inst_at_s1e3w_r ¶
Source

inst_at_s1e3w_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_autda ¶
Source

inst_autda :: inst_autda_r_r

inst_autda_r_r ¶
Source

inst_autda_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_autdb ¶
Source

inst_autdb :: inst_autdb_r_r

inst_autdb_r_r ¶
Source

inst_autdb_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_autdza ¶
Source

inst_autdza :: inst_autdza_r

inst_autdza_r ¶
Source

inst_autdza_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_autdzb ¶
Source

inst_autdzb :: inst_autdzb_r

inst_autdzb_r ¶
Source

inst_autdzb_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_autia ¶
Source

inst_autia :: inst_autia_r_r

inst_autia1716 ¶
Source

inst_autia1716 :: inst_autia1716_none

inst_autia1716_none ¶
Source

inst_autia1716_none :: proc "contextless" () -> Instruction {…}

inst_autia_r_r ¶
Source

inst_autia_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_autiasp ¶
Source

inst_autiasp :: inst_autiasp_none

inst_autiasp_none ¶
Source

inst_autiasp_none :: proc "contextless" () -> Instruction {…}

inst_autib ¶
Source

inst_autib :: inst_autib_r_r

inst_autib1716 ¶
Source

inst_autib1716 :: inst_autib1716_none

inst_autib1716_none ¶
Source

inst_autib1716_none :: proc "contextless" () -> Instruction {…}

inst_autib_r_r ¶
Source

inst_autib_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_autibsp ¶
Source

inst_autibsp :: inst_autibsp_none

inst_autibsp_none ¶
Source

inst_autibsp_none :: proc "contextless" () -> Instruction {…}

inst_autiza ¶
Source

inst_autiza :: inst_autiza_r

inst_autiza_r ¶
Source

inst_autiza_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_autizb ¶
Source

inst_autizb :: inst_autizb_r

inst_autizb_r ¶
Source

inst_autizb_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_b ¶
Source

inst_b :: inst_b_l

inst_b_cond ¶
Source

inst_b_cond :: inst_b_cond_c_l

inst_b_cond_c_l ¶
Source

inst_b_cond_c_l :: proc "contextless" (cond: Cond, label: u32) -> Instruction {…}

inst_b_l ¶
Source

inst_b_l :: proc "contextless" (label: u32) -> Instruction {…}

inst_bc_cond ¶
Source

inst_bc_cond :: inst_bc_cond_c_l

inst_bc_cond_c_l ¶
Source

inst_bc_cond_c_l :: proc "contextless" (cond: Cond, label: u32) -> Instruction {…}

inst_bcax ¶
Source

inst_bcax :: inst_bcax_r_r_r_r

inst_bcax_r_r_r_r ¶
Source

inst_bcax_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_bfcvt ¶
Source

inst_bfcvt :: inst_bfcvt_r_r

inst_bfcvt_r_r ¶
Source

inst_bfcvt_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_bfcvtn ¶
Source

inst_bfcvtn :: inst_bfcvtn_r_r

inst_bfcvtn2 ¶
Source

inst_bfcvtn2 :: inst_bfcvtn2_r_r

inst_bfcvtn2_r_r ¶
Source

inst_bfcvtn2_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_bfcvtn_r_r ¶
Source

inst_bfcvtn_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_bfdot ¶
Source

inst_bfdot :: inst_bfdot_r_r_r

inst_bfdot_r_r_r ¶
Source

inst_bfdot_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_bfmlalb ¶
Source

inst_bfmlalb :: inst_bfmlalb_r_r_r

inst_bfmlalb_r_r_r ¶
Source

inst_bfmlalb_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_bfmlalt ¶
Source

inst_bfmlalt :: inst_bfmlalt_r_r_r

inst_bfmlalt_r_r_r ¶
Source

inst_bfmlalt_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_bfmmla ¶
Source

inst_bfmmla :: inst_bfmmla_r_r_r

inst_bfmmla_r_r_r ¶
Source

inst_bfmmla_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_bic_sr ¶
Source

inst_bic_sr :: inst_bic_sr_r_r_sh

inst_bic_sr_r_r_sh ¶
Source

inst_bic_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_bic_v ¶
Source

inst_bic_v :: inst_bic_v_r_r_r

inst_bic_v_r_r_r ¶
Source

inst_bic_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_bics_sr ¶
Source

inst_bics_sr :: inst_bics_sr_r_r_sh

inst_bics_sr_r_r_sh ¶
Source

inst_bics_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_bif ¶
Source

inst_bif :: inst_bif_r_r_r

inst_bif_r_r_r ¶
Source

inst_bif_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_bit ¶
Source

inst_bit :: inst_bit_r_r_r

inst_bit_r_r_r ¶
Source

inst_bit_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_bl ¶
Source

inst_bl :: inst_bl_l

inst_bl_l ¶
Source

inst_bl_l :: proc "contextless" (label: u32) -> Instruction {…}

inst_blr ¶
Source

inst_blr :: inst_blr_r

inst_blr_r ¶
Source

inst_blr_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_blraa ¶
Source

inst_blraa :: inst_blraa_r_r

inst_blraa_r_r ¶
Source

inst_blraa_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_blraaz ¶
Source

inst_blraaz :: inst_blraaz_r

inst_blraaz_r ¶
Source

inst_blraaz_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_blrab ¶
Source

inst_blrab :: inst_blrab_r_r

inst_blrab_r_r ¶
Source

inst_blrab_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_blrabz ¶
Source

inst_blrabz :: inst_blrabz_r

inst_blrabz_r ¶
Source

inst_blrabz_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_br ¶
Source

inst_br :: inst_br_r

inst_br_r ¶
Source

inst_br_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_braa ¶
Source

inst_braa :: inst_braa_r_r

inst_braa_r_r ¶
Source

inst_braa_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_braaz ¶
Source

inst_braaz :: inst_braaz_r

inst_braaz_r ¶
Source

inst_braaz_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_brab ¶
Source

inst_brab :: inst_brab_r_r

inst_brab_r_r ¶
Source

inst_brab_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_brabz ¶
Source

inst_brabz :: inst_brabz_r

inst_brabz_r ¶
Source

inst_brabz_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_branch ¶
Source

inst_branch :: proc "contextless" (m: Mnemonic, label_id: u32) -> Instruction {…}

PC-relative branch (B, BL).

inst_brk ¶
Source

inst_brk :: inst_brk_i

inst_brk_i ¶
Source

inst_brk_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_bsl ¶
Source

inst_bsl :: inst_bsl_r_r_r

inst_bsl_r_r_r ¶
Source

inst_bsl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_bti ¶
Source

inst_bti :: inst_bti_i

inst_bti_c ¶
Source

inst_bti_c :: inst_bti_c_none

inst_bti_c_none ¶
Source

inst_bti_c_none :: proc "contextless" () -> Instruction {…}

inst_bti_i ¶
Source

inst_bti_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_bti_j ¶
Source

inst_bti_j :: inst_bti_j_none

inst_bti_j_none ¶
Source

inst_bti_j_none :: proc "contextless" () -> Instruction {…}

inst_bti_jc ¶
Source

inst_bti_jc :: inst_bti_jc_none

inst_bti_jc_none ¶
Source

inst_bti_jc_none :: proc "contextless" () -> Instruction {…}

inst_cas ¶
Source

inst_cas :: inst_cas_r_r_m

inst_cas_r_r_m ¶
Source

inst_cas_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_casa ¶
Source

inst_casa :: inst_casa_r_r_m

inst_casa_r_r_m ¶
Source

inst_casa_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_casab ¶
Source

inst_casab :: inst_casab_r_r_m

inst_casab_r_r_m ¶
Source

inst_casab_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_casah ¶
Source

inst_casah :: inst_casah_r_r_m

inst_casah_r_r_m ¶
Source

inst_casah_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_casal ¶
Source

inst_casal :: inst_casal_r_r_m

inst_casal_r_r_m ¶
Source

inst_casal_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_casalb ¶
Source

inst_casalb :: inst_casalb_r_r_m

inst_casalb_r_r_m ¶
Source

inst_casalb_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_casalh ¶
Source

inst_casalh :: inst_casalh_r_r_m

inst_casalh_r_r_m ¶
Source

inst_casalh_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_casb ¶
Source

inst_casb :: inst_casb_r_r_m

inst_casb_r_r_m ¶
Source

inst_casb_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_cash ¶
Source

inst_cash :: inst_cash_r_r_m

inst_cash_r_r_m ¶
Source

inst_cash_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_casl ¶
Source

inst_casl :: inst_casl_r_r_m

inst_casl_r_r_m ¶
Source

inst_casl_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_caslb ¶
Source

inst_caslb :: inst_caslb_r_r_m

inst_caslb_r_r_m ¶
Source

inst_caslb_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_caslh ¶
Source

inst_caslh :: inst_caslh_r_r_m

inst_caslh_r_r_m ¶
Source

inst_caslh_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_casp ¶
Source

inst_casp :: inst_casp_r_r_m

inst_casp_r_r_m ¶
Source

inst_casp_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_caspa ¶
Source

inst_caspa :: inst_caspa_r_r_m

inst_caspa_r_r_m ¶
Source

inst_caspa_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_caspal ¶
Source

inst_caspal :: inst_caspal_r_r_m

inst_caspal_r_r_m ¶
Source

inst_caspal_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_caspl ¶
Source

inst_caspl :: inst_caspl_r_r_m

inst_caspl_r_r_m ¶
Source

inst_caspl_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_cbnz ¶
Source

inst_cbnz :: inst_cbnz_r_l

inst_cbnz_r_l ¶
Source

inst_cbnz_r_l :: proc "contextless" (dst: Register, label: u32) -> Instruction {…}

inst_cbz ¶
Source

inst_cbz :: inst_cbz_r_l

inst_cbz_r_l ¶
Source

inst_cbz_r_l :: proc "contextless" (dst: Register, label: u32) -> Instruction {…}

inst_ccmn_imm ¶
Source

inst_ccmn_imm :: inst_ccmn_imm_r_i_i_c

inst_ccmn_imm_r_i_i_c ¶
Source

inst_ccmn_imm_r_i_i_c :: proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction {…}

inst_ccmn_reg ¶
Source

inst_ccmn_reg :: inst_ccmn_reg_r_r_i_c

inst_ccmn_reg_r_r_i_c ¶
Source

inst_ccmn_reg_r_r_i_c :: proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction {…}

inst_ccmp_imm ¶
Source

inst_ccmp_imm :: inst_ccmp_imm_r_i_i_c

inst_ccmp_imm_r_i_i_c ¶
Source

inst_ccmp_imm_r_i_i_c :: proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction {…}

inst_ccmp_reg ¶
Source

inst_ccmp_reg :: inst_ccmp_reg_r_r_i_c

inst_ccmp_reg_r_r_i_c ¶
Source

inst_ccmp_reg_r_r_i_c :: proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction {…}

inst_cls ¶
Source

inst_cls :: inst_cls_r_r

inst_cls_r_r ¶
Source

inst_cls_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_cls_v ¶
Source

inst_cls_v :: inst_cls_v_r_r

inst_cls_v_r_r ¶
Source

inst_cls_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_clz ¶
Source

inst_clz :: inst_clz_r_r

inst_clz_r_r ¶
Source

inst_clz_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_clz_v ¶
Source

inst_clz_v :: inst_clz_v_r_r

inst_clz_v_r_r ¶
Source

inst_clz_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_cmeq ¶
Source

inst_cmeq :: inst_cmeq_r_r_r

inst_cmeq_r_r_r ¶
Source

inst_cmeq_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_cmge ¶
Source

inst_cmge :: inst_cmge_r_r_r

inst_cmge_r_r_r ¶
Source

inst_cmge_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_cmgt ¶
Source

inst_cmgt :: inst_cmgt_r_r_r

inst_cmgt_r_r_r ¶
Source

inst_cmgt_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_cmhi ¶
Source

inst_cmhi :: inst_cmhi_r_r_r

inst_cmhi_r_r_r ¶
Source

inst_cmhi_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_cmhs ¶
Source

inst_cmhs :: inst_cmhs_r_r_r

inst_cmhs_r_r_r ¶
Source

inst_cmhs_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_cmle ¶
Source

inst_cmle :: inst_cmle_r_r

inst_cmle_r_r ¶
Source

inst_cmle_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_cmlt ¶
Source

inst_cmlt :: inst_cmlt_r_r

inst_cmlt_r_r ¶
Source

inst_cmlt_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_cmn_er ¶
Source

inst_cmn_er :: inst_cmn_er_r_ex

inst_cmn_er_r_ex ¶
Source

inst_cmn_er_r_ex :: proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction {…}

inst_cmn_imm ¶
Source

inst_cmn_imm :: inst_cmn_imm_r_i

inst_cmn_imm_r_i ¶
Source

inst_cmn_imm_r_i :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

inst_cmn_sr ¶
Source

inst_cmn_sr :: inst_cmn_sr_r_sh

inst_cmn_sr_r_sh ¶
Source

inst_cmn_sr_r_sh :: proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction {…}

inst_cmp_er ¶
Source

inst_cmp_er :: inst_cmp_er_r_ex

inst_cmp_er_r_ex ¶
Source

inst_cmp_er_r_ex :: proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction {…}

inst_cmp_imm ¶
Source

inst_cmp_imm :: inst_cmp_imm_r_i

inst_cmp_imm_r_i ¶
Source

inst_cmp_imm_r_i :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

inst_cmp_sr ¶
Source

inst_cmp_sr :: inst_cmp_sr_r_sh

inst_cmp_sr_r_sh ¶
Source

inst_cmp_sr_r_sh :: proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction {…}

inst_cmtst ¶
Source

inst_cmtst :: inst_cmtst_r_r_r

inst_cmtst_r_r_r ¶
Source

inst_cmtst_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_cnt ¶
Source

inst_cnt :: inst_cnt_r_r

inst_cnt_r_r ¶
Source

inst_cnt_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_cpye ¶
Source

inst_cpye :: inst_cpye_r_r_r

inst_cpye_r_r_r ¶
Source

inst_cpye_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_cpyfe ¶
Source

inst_cpyfe :: inst_cpyfe_r_r_r

inst_cpyfe_r_r_r ¶
Source

inst_cpyfe_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_cpyfm ¶
Source

inst_cpyfm :: inst_cpyfm_r_r_r

inst_cpyfm_r_r_r ¶
Source

inst_cpyfm_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_cpyfp ¶
Source

inst_cpyfp :: inst_cpyfp_r_r_r

inst_cpyfp_r_r_r ¶
Source

inst_cpyfp_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_cpym ¶
Source

inst_cpym :: inst_cpym_r_r_r

inst_cpym_r_r_r ¶
Source

inst_cpym_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_cpyp ¶
Source

inst_cpyp :: inst_cpyp_r_r_r

inst_cpyp_r_r_r ¶
Source

inst_cpyp_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_crc32b ¶
Source

inst_crc32b :: inst_crc32b_r_r_r

inst_crc32b_r_r_r ¶
Source

inst_crc32b_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_crc32cb ¶
Source

inst_crc32cb :: inst_crc32cb_r_r_r

inst_crc32cb_r_r_r ¶
Source

inst_crc32cb_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_crc32ch ¶
Source

inst_crc32ch :: inst_crc32ch_r_r_r

inst_crc32ch_r_r_r ¶
Source

inst_crc32ch_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_crc32cw ¶
Source

inst_crc32cw :: inst_crc32cw_r_r_r

inst_crc32cw_r_r_r ¶
Source

inst_crc32cw_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_crc32cx ¶
Source

inst_crc32cx :: inst_crc32cx_r_r_r

inst_crc32cx_r_r_r ¶
Source

inst_crc32cx_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_crc32h ¶
Source

inst_crc32h :: inst_crc32h_r_r_r

inst_crc32h_r_r_r ¶
Source

inst_crc32h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_crc32w ¶
Source

inst_crc32w :: inst_crc32w_r_r_r

inst_crc32w_r_r_r ¶
Source

inst_crc32w_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_crc32x ¶
Source

inst_crc32x :: inst_crc32x_r_r_r

inst_crc32x_r_r_r ¶
Source

inst_crc32x_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_csdb ¶
Source

inst_csdb :: inst_csdb_none

inst_csdb_none ¶
Source

inst_csdb_none :: proc "contextless" () -> Instruction {…}

inst_csel ¶
Source

inst_csel :: inst_csel_r_r_r_c

inst_csel_r_r_r_c ¶
Source

inst_csel_r_r_r_c :: proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction {…}

inst_csinc ¶
Source

inst_csinc :: inst_csinc_r_r_r_c

inst_csinc_r_r_r_c ¶
Source

inst_csinc_r_r_r_c :: proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction {…}

inst_csinv ¶
Source

inst_csinv :: inst_csinv_r_r_r_c

inst_csinv_r_r_r_c ¶
Source

inst_csinv_r_r_r_c :: proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction {…}

inst_csneg ¶
Source

inst_csneg :: inst_csneg_r_r_r_c

inst_csneg_r_r_r_c ¶
Source

inst_csneg_r_r_r_c :: proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction {…}

inst_dc_cigdpapa ¶
Source

inst_dc_cigdpapa :: inst_dc_cigdpapa_r

inst_dc_cigdpapa_r ¶
Source

inst_dc_cigdpapa_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_dc_cipapa ¶
Source

inst_dc_cipapa :: inst_dc_cipapa_r

inst_dc_cipapa_r ¶
Source

inst_dc_cipapa_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_dc_cisw ¶
Source

inst_dc_cisw :: inst_dc_cisw_r

inst_dc_cisw_r ¶
Source

inst_dc_cisw_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_dc_civac ¶
Source

inst_dc_civac :: inst_dc_civac_r

inst_dc_civac_r ¶
Source

inst_dc_civac_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_dc_csw ¶
Source

inst_dc_csw :: inst_dc_csw_r

inst_dc_csw_r ¶
Source

inst_dc_csw_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_dc_cvac ¶
Source

inst_dc_cvac :: inst_dc_cvac_r

inst_dc_cvac_r ¶
Source

inst_dc_cvac_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_dc_cvau ¶
Source

inst_dc_cvau :: inst_dc_cvau_r

inst_dc_cvau_r ¶
Source

inst_dc_cvau_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_dc_isw ¶
Source

inst_dc_isw :: inst_dc_isw_r

inst_dc_isw_r ¶
Source

inst_dc_isw_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_dc_ivac ¶
Source

inst_dc_ivac :: inst_dc_ivac_r

inst_dc_ivac_r ¶
Source

inst_dc_ivac_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_dc_zva ¶
Source

inst_dc_zva :: inst_dc_zva_r

inst_dc_zva_r ¶
Source

inst_dc_zva_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_dgh ¶
Source

inst_dgh :: inst_dgh_none

inst_dgh_none ¶
Source

inst_dgh_none :: proc "contextless" () -> Instruction {…}

inst_dmb ¶
Source

inst_dmb :: inst_dmb_i

inst_dmb_i ¶
Source

inst_dmb_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_dsb ¶
Source

inst_dsb :: inst_dsb_i

inst_dsb_i ¶
Source

inst_dsb_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_dup_v_r_r ¶
Source

inst_dup_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

Related Procedure Groups

inst_dup_v

inst_dup_v_r_r_i ¶
Source

inst_dup_v_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

Related Procedure Groups

inst_dup_v

inst_eon_sr ¶
Source

inst_eon_sr :: inst_eon_sr_r_r_sh

inst_eon_sr_r_r_sh ¶
Source

inst_eon_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_eor3 ¶
Source

inst_eor3 :: inst_eor3_r_r_r_r

inst_eor3_r_r_r_r ¶
Source

inst_eor3_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_eor_imm ¶
Source

inst_eor_imm :: inst_eor_imm_r_r_i

inst_eor_imm_r_r_i ¶
Source

inst_eor_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_eor_sr ¶
Source

inst_eor_sr :: inst_eor_sr_r_r_sh

inst_eor_sr_r_r_sh ¶
Source

inst_eor_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_eor_v ¶
Source

inst_eor_v :: inst_eor_v_r_r_r

inst_eor_v_r_r_r ¶
Source

inst_eor_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_eret ¶
Source

inst_eret :: inst_eret_none

inst_eret_none ¶
Source

inst_eret_none :: proc "contextless" () -> Instruction {…}

inst_eretaa ¶
Source

inst_eretaa :: inst_eretaa_none

inst_eretaa_none ¶
Source

inst_eretaa_none :: proc "contextless" () -> Instruction {…}

inst_eretab ¶
Source

inst_eretab :: inst_eretab_none

inst_eretab_none ¶
Source

inst_eretab_none :: proc "contextless" () -> Instruction {…}

inst_ext_v ¶
Source

inst_ext_v :: inst_ext_v_r_r_r_i

inst_ext_v_r_r_r_i ¶
Source

inst_ext_v_r_r_r_i :: proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction {…}

inst_extr ¶
Source

inst_extr :: inst_extr_r_r_r_i

inst_extr_r_r_r_i ¶
Source

inst_extr_r_r_r_i :: proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction {…}

inst_fabs ¶
Source

inst_fabs :: inst_fabs_r_r

inst_fabs_h ¶
Source

inst_fabs_h :: inst_fabs_h_r_r

inst_fabs_h_r_r ¶
Source

inst_fabs_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fabs_r_r ¶
Source

inst_fabs_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fabs_v ¶
Source

inst_fabs_v :: inst_fabs_v_r_r

inst_fabs_v_r_r ¶
Source

inst_fabs_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_facge ¶
Source

inst_facge :: inst_facge_r_r_r

inst_facge_r_r_r ¶
Source

inst_facge_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_facgt ¶
Source

inst_facgt :: inst_facgt_r_r_r

inst_facgt_r_r_r ¶
Source

inst_facgt_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fadd ¶
Source

inst_fadd :: inst_fadd_r_r_r

inst_fadd_h ¶
Source

inst_fadd_h :: inst_fadd_h_r_r_r

inst_fadd_h_r_r_r ¶
Source

inst_fadd_h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fadd_r_r_r ¶
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inst_fadd_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fadd_v ¶
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inst_fadd_v :: inst_fadd_v_r_r_r

inst_fadd_v_r_r_r ¶
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inst_fadd_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_faddp_v ¶
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inst_faddp_v :: inst_faddp_v_r_r_r

inst_faddp_v_r_r_r ¶
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inst_faddp_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fcadd_2d ¶
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inst_fcadd_2d :: inst_fcadd_2d_r_r_r_i

inst_fcadd_2d_r_r_r_i ¶
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inst_fcadd_2d_r_r_r_i :: proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction {…}

inst_fcadd_4h ¶
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inst_fcadd_4h :: inst_fcadd_4h_r_r_r_i

inst_fcadd_4h_r_r_r_i ¶
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inst_fcadd_4h_r_r_r_i :: proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction {…}

inst_fcadd_4s ¶
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inst_fcadd_4s :: inst_fcadd_4s_r_r_r_i

inst_fcadd_4s_r_r_r_i ¶
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inst_fcadd_4s_r_r_r_i :: proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction {…}

inst_fcadd_8h ¶
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inst_fcadd_8h :: inst_fcadd_8h_r_r_r_i

inst_fcadd_8h_r_r_r_i ¶
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inst_fcadd_8h_r_r_r_i :: proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction {…}

inst_fcmeq ¶
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inst_fcmeq :: inst_fcmeq_r_r_r

inst_fcmeq_r_r_r ¶
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inst_fcmeq_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fcmge ¶
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inst_fcmge :: inst_fcmge_r_r_r

inst_fcmge_r_r_r ¶
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inst_fcmge_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fcmgt ¶
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inst_fcmgt :: inst_fcmgt_r_r_r

inst_fcmgt_r_r_r ¶
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inst_fcmgt_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fcmla_2d ¶
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inst_fcmla_2d :: inst_fcmla_2d_r_r_r_i

inst_fcmla_2d_r_r_r_i ¶
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inst_fcmla_2d_r_r_r_i :: proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction {…}

inst_fcmla_4h ¶
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inst_fcmla_4h :: inst_fcmla_4h_r_r_r_i

inst_fcmla_4h_r_r_r_i ¶
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inst_fcmla_4h_r_r_r_i :: proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction {…}

inst_fcmla_4s ¶
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inst_fcmla_4s :: inst_fcmla_4s_r_r_r_i

inst_fcmla_4s_r_r_r_i ¶
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inst_fcmla_4s_r_r_r_i :: proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction {…}

inst_fcmla_8h ¶
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inst_fcmla_8h :: inst_fcmla_8h_r_r_r_i

inst_fcmla_8h_r_r_r_i ¶
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inst_fcmla_8h_r_r_r_i :: proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction {…}

inst_fcmle ¶
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inst_fcmle :: inst_fcmle_r_r

inst_fcmle_r_r ¶
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inst_fcmle_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcmlt ¶
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inst_fcmlt :: inst_fcmlt_r_r

inst_fcmlt_r_r ¶
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inst_fcmlt_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcmp ¶
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inst_fcmp :: inst_fcmp_r_r

inst_fcmp_h ¶
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inst_fcmp_h :: inst_fcmp_h_r_r

inst_fcmp_h_r_r ¶
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inst_fcmp_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcmp_r_r ¶
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inst_fcmp_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcmpe ¶
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inst_fcmpe :: inst_fcmpe_r_r

inst_fcmpe_h ¶
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inst_fcmpe_h :: inst_fcmpe_h_r_r

inst_fcmpe_h_r_r ¶
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inst_fcmpe_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcmpe_r_r ¶
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inst_fcmpe_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcsel ¶
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inst_fcsel :: inst_fcsel_r_r_r_c

inst_fcsel_h ¶
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inst_fcsel_h :: inst_fcsel_h_r_r_r_c

inst_fcsel_h_r_r_r_c ¶
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inst_fcsel_h_r_r_r_c :: proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction {…}

inst_fcsel_r_r_r_c ¶
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inst_fcsel_r_r_r_c :: proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction {…}

inst_fcvt ¶
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inst_fcvt :: inst_fcvt_r_r

inst_fcvt_d_h ¶
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inst_fcvt_d_h :: inst_fcvt_d_h_r_r

inst_fcvt_d_h_r_r ¶
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inst_fcvt_d_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvt_h_d ¶
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inst_fcvt_h_d :: inst_fcvt_h_d_r_r

inst_fcvt_h_d_r_r ¶
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inst_fcvt_h_d_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvt_h_s ¶
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inst_fcvt_h_s :: inst_fcvt_h_s_r_r

inst_fcvt_h_s_r_r ¶
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inst_fcvt_h_s_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvt_r_r ¶
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inst_fcvt_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvt_s_h ¶
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inst_fcvt_s_h :: inst_fcvt_s_h_r_r

inst_fcvt_s_h_r_r ¶
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inst_fcvt_s_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtas ¶
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inst_fcvtas :: inst_fcvtas_r_r

inst_fcvtas_r_r ¶
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inst_fcvtas_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtas_v ¶
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inst_fcvtas_v :: inst_fcvtas_v_r_r

inst_fcvtas_v_r_r ¶
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inst_fcvtas_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtau ¶
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inst_fcvtau :: inst_fcvtau_r_r

inst_fcvtau_r_r ¶
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inst_fcvtau_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtau_v ¶
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inst_fcvtau_v :: inst_fcvtau_v_r_r

inst_fcvtau_v_r_r ¶
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inst_fcvtau_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtl ¶
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inst_fcvtl :: inst_fcvtl_r_r

inst_fcvtl2 ¶
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inst_fcvtl2 :: inst_fcvtl2_r_r

inst_fcvtl2_r_r ¶
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inst_fcvtl2_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtl_r_r ¶
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inst_fcvtl_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtms ¶
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inst_fcvtms :: inst_fcvtms_r_r

inst_fcvtms_r_r ¶
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inst_fcvtms_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtms_v ¶
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inst_fcvtms_v :: inst_fcvtms_v_r_r

inst_fcvtms_v_r_r ¶
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inst_fcvtms_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtmu ¶
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inst_fcvtmu :: inst_fcvtmu_r_r

inst_fcvtmu_r_r ¶
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inst_fcvtmu_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtmu_v ¶
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inst_fcvtmu_v :: inst_fcvtmu_v_r_r

inst_fcvtmu_v_r_r ¶
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inst_fcvtmu_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtn ¶
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inst_fcvtn :: inst_fcvtn_r_r

inst_fcvtn2 ¶
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inst_fcvtn2 :: inst_fcvtn2_r_r

inst_fcvtn2_r_r ¶
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inst_fcvtn2_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtn_r_r ¶
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inst_fcvtn_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtns ¶
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inst_fcvtns :: inst_fcvtns_r_r

inst_fcvtns_r_r ¶
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inst_fcvtns_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtns_v ¶
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inst_fcvtns_v :: inst_fcvtns_v_r_r

inst_fcvtns_v_r_r ¶
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inst_fcvtns_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtnu ¶
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inst_fcvtnu :: inst_fcvtnu_r_r

inst_fcvtnu_r_r ¶
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inst_fcvtnu_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtnu_v ¶
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inst_fcvtnu_v :: inst_fcvtnu_v_r_r

inst_fcvtnu_v_r_r ¶
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inst_fcvtnu_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtps ¶
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inst_fcvtps :: inst_fcvtps_r_r

inst_fcvtps_r_r ¶
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inst_fcvtps_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtps_v ¶
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inst_fcvtps_v :: inst_fcvtps_v_r_r

inst_fcvtps_v_r_r ¶
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inst_fcvtps_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtpu ¶
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inst_fcvtpu :: inst_fcvtpu_r_r

inst_fcvtpu_r_r ¶
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inst_fcvtpu_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtpu_v ¶
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inst_fcvtpu_v :: inst_fcvtpu_v_r_r

inst_fcvtpu_v_r_r ¶
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inst_fcvtpu_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtxn ¶
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inst_fcvtxn :: inst_fcvtxn_r_r

inst_fcvtxn2 ¶
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inst_fcvtxn2 :: inst_fcvtxn2_r_r

inst_fcvtxn2_r_r ¶
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inst_fcvtxn2_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtxn_r_r ¶
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inst_fcvtxn_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtzs ¶
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inst_fcvtzs :: inst_fcvtzs_r_r

inst_fcvtzs_h ¶
Source

inst_fcvtzs_h :: inst_fcvtzs_h_r_r

inst_fcvtzs_h_r_r ¶
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inst_fcvtzs_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtzs_r_r ¶
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inst_fcvtzs_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtzs_v ¶
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inst_fcvtzs_v :: inst_fcvtzs_v_r_r

inst_fcvtzs_v_r_r ¶
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inst_fcvtzs_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtzu ¶
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inst_fcvtzu :: inst_fcvtzu_r_r

inst_fcvtzu_h ¶
Source

inst_fcvtzu_h :: inst_fcvtzu_h_r_r

inst_fcvtzu_h_r_r ¶
Source

inst_fcvtzu_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtzu_r_r ¶
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inst_fcvtzu_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fcvtzu_v ¶
Source

inst_fcvtzu_v :: inst_fcvtzu_v_r_r

inst_fcvtzu_v_r_r ¶
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inst_fcvtzu_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fdiv ¶
Source

inst_fdiv :: inst_fdiv_r_r_r

inst_fdiv_h ¶
Source

inst_fdiv_h :: inst_fdiv_h_r_r_r

inst_fdiv_h_r_r_r ¶
Source

inst_fdiv_h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fdiv_r_r_r ¶
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inst_fdiv_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fdiv_v ¶
Source

inst_fdiv_v :: inst_fdiv_v_r_r_r

inst_fdiv_v_r_r_r ¶
Source

inst_fdiv_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmadd ¶
Source

inst_fmadd :: inst_fmadd_r_r_r_r

inst_fmadd_h ¶
Source

inst_fmadd_h :: inst_fmadd_h_r_r_r_r

inst_fmadd_h_r_r_r_r ¶
Source

inst_fmadd_h_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_fmadd_r_r_r_r ¶
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inst_fmadd_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_fmax ¶
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inst_fmax :: inst_fmax_r_r_r

inst_fmax_h ¶
Source

inst_fmax_h :: inst_fmax_h_r_r_r

inst_fmax_h_r_r_r ¶
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inst_fmax_h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmax_r_r_r ¶
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inst_fmax_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmax_v ¶
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inst_fmax_v :: inst_fmax_v_r_r_r

inst_fmax_v_r_r_r ¶
Source

inst_fmax_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmaxnm ¶
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inst_fmaxnm :: inst_fmaxnm_r_r_r

inst_fmaxnm_h ¶
Source

inst_fmaxnm_h :: inst_fmaxnm_h_r_r_r

inst_fmaxnm_h_r_r_r ¶
Source

inst_fmaxnm_h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmaxnm_r_r_r ¶
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inst_fmaxnm_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmaxnm_v ¶
Source

inst_fmaxnm_v :: inst_fmaxnm_v_r_r_r

inst_fmaxnm_v_r_r_r ¶
Source

inst_fmaxnm_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmaxnmp ¶
Source

inst_fmaxnmp :: inst_fmaxnmp_r_r_r

inst_fmaxnmp_r_r_r ¶
Source

inst_fmaxnmp_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmaxnmv ¶
Source

inst_fmaxnmv :: inst_fmaxnmv_r_r

inst_fmaxnmv_r_r ¶
Source

inst_fmaxnmv_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fmaxp_v ¶
Source

inst_fmaxp_v :: inst_fmaxp_v_r_r_r

inst_fmaxp_v_r_r_r ¶
Source

inst_fmaxp_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmaxv_v ¶
Source

inst_fmaxv_v :: inst_fmaxv_v_r_r

inst_fmaxv_v_r_r ¶
Source

inst_fmaxv_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fmin ¶
Source

inst_fmin :: inst_fmin_r_r_r

inst_fmin_h ¶
Source

inst_fmin_h :: inst_fmin_h_r_r_r

inst_fmin_h_r_r_r ¶
Source

inst_fmin_h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmin_r_r_r ¶
Source

inst_fmin_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmin_v ¶
Source

inst_fmin_v :: inst_fmin_v_r_r_r

inst_fmin_v_r_r_r ¶
Source

inst_fmin_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fminnm ¶
Source

inst_fminnm :: inst_fminnm_r_r_r

inst_fminnm_h ¶
Source

inst_fminnm_h :: inst_fminnm_h_r_r_r

inst_fminnm_h_r_r_r ¶
Source

inst_fminnm_h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fminnm_r_r_r ¶
Source

inst_fminnm_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fminnm_v ¶
Source

inst_fminnm_v :: inst_fminnm_v_r_r_r

inst_fminnm_v_r_r_r ¶
Source

inst_fminnm_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fminnmp ¶
Source

inst_fminnmp :: inst_fminnmp_r_r_r

inst_fminnmp_r_r_r ¶
Source

inst_fminnmp_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fminnmv ¶
Source

inst_fminnmv :: inst_fminnmv_r_r

inst_fminnmv_r_r ¶
Source

inst_fminnmv_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fminp_v ¶
Source

inst_fminp_v :: inst_fminp_v_r_r_r

inst_fminp_v_r_r_r ¶
Source

inst_fminp_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fminv_v ¶
Source

inst_fminv_v :: inst_fminv_v_r_r

inst_fminv_v_r_r ¶
Source

inst_fminv_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fmla_v ¶
Source

inst_fmla_v :: inst_fmla_v_r_r_r

inst_fmla_v_r_r_r ¶
Source

inst_fmla_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmls_v ¶
Source

inst_fmls_v :: inst_fmls_v_r_r_r

inst_fmls_v_r_r_r ¶
Source

inst_fmls_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmov_gen ¶
Source

inst_fmov_gen :: inst_fmov_gen_r_r

inst_fmov_gen_r_r ¶
Source

inst_fmov_gen_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fmov_h ¶
Source

inst_fmov_h :: inst_fmov_h_r_r

inst_fmov_h_r_r ¶
Source

inst_fmov_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fmov_imm ¶
Source

inst_fmov_imm :: inst_fmov_imm_r_i

inst_fmov_imm_r_i ¶
Source

inst_fmov_imm_r_i :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

inst_fmov_reg ¶
Source

inst_fmov_reg :: inst_fmov_reg_r_r

inst_fmov_reg_r_r ¶
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inst_fmov_reg_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fmov_v_imm ¶
Source

inst_fmov_v_imm :: inst_fmov_v_imm_r_i

inst_fmov_v_imm_r_i ¶
Source

inst_fmov_v_imm_r_i :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

inst_fmsub ¶
Source

inst_fmsub :: inst_fmsub_r_r_r_r

inst_fmsub_h ¶
Source

inst_fmsub_h :: inst_fmsub_h_r_r_r_r

inst_fmsub_h_r_r_r_r ¶
Source

inst_fmsub_h_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_fmsub_r_r_r_r ¶
Source

inst_fmsub_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_fmul ¶
Source

inst_fmul :: inst_fmul_r_r_r

inst_fmul_h ¶
Source

inst_fmul_h :: inst_fmul_h_r_r_r

inst_fmul_h_r_r_r ¶
Source

inst_fmul_h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmul_r_r_r ¶
Source

inst_fmul_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmul_v ¶
Source

inst_fmul_v :: inst_fmul_v_r_r_r

inst_fmul_v_r_r_r ¶
Source

inst_fmul_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fmulx ¶
Source

inst_fmulx :: inst_fmulx_r_r_r

inst_fmulx_r_r_r ¶
Source

inst_fmulx_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fneg ¶
Source

inst_fneg :: inst_fneg_r_r

inst_fneg_h ¶
Source

inst_fneg_h :: inst_fneg_h_r_r

inst_fneg_h_r_r ¶
Source

inst_fneg_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fneg_r_r ¶
Source

inst_fneg_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fneg_v ¶
Source

inst_fneg_v :: inst_fneg_v_r_r

inst_fneg_v_r_r ¶
Source

inst_fneg_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fnmadd ¶
Source

inst_fnmadd :: inst_fnmadd_r_r_r_r

inst_fnmadd_h ¶
Source

inst_fnmadd_h :: inst_fnmadd_h_r_r_r_r

inst_fnmadd_h_r_r_r_r ¶
Source

inst_fnmadd_h_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_fnmadd_r_r_r_r ¶
Source

inst_fnmadd_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_fnmsub ¶
Source

inst_fnmsub :: inst_fnmsub_r_r_r_r

inst_fnmsub_h ¶
Source

inst_fnmsub_h :: inst_fnmsub_h_r_r_r_r

inst_fnmsub_h_r_r_r_r ¶
Source

inst_fnmsub_h_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_fnmsub_r_r_r_r ¶
Source

inst_fnmsub_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_fnmul ¶
Source

inst_fnmul :: inst_fnmul_r_r_r

inst_fnmul_h ¶
Source

inst_fnmul_h :: inst_fnmul_h_r_r_r

inst_fnmul_h_r_r_r ¶
Source

inst_fnmul_h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fnmul_r_r_r ¶
Source

inst_fnmul_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_frecpe ¶
Source

inst_frecpe :: inst_frecpe_r_r

inst_frecpe_r_r ¶
Source

inst_frecpe_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frecps ¶
Source

inst_frecps :: inst_frecps_r_r_r

inst_frecps_r_r_r ¶
Source

inst_frecps_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_frecpx ¶
Source

inst_frecpx :: inst_frecpx_r_r

inst_frecpx_r_r ¶
Source

inst_frecpx_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frinta ¶
Source

inst_frinta :: inst_frinta_r_r

inst_frinta_r_r ¶
Source

inst_frinta_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frinta_v ¶
Source

inst_frinta_v :: inst_frinta_v_r_r

inst_frinta_v_r_r ¶
Source

inst_frinta_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frinti ¶
Source

inst_frinti :: inst_frinti_r_r

inst_frinti_r_r ¶
Source

inst_frinti_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frinti_v ¶
Source

inst_frinti_v :: inst_frinti_v_r_r

inst_frinti_v_r_r ¶
Source

inst_frinti_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frintm ¶
Source

inst_frintm :: inst_frintm_r_r

inst_frintm_r_r ¶
Source

inst_frintm_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frintm_v ¶
Source

inst_frintm_v :: inst_frintm_v_r_r

inst_frintm_v_r_r ¶
Source

inst_frintm_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frintn ¶
Source

inst_frintn :: inst_frintn_r_r

inst_frintn_r_r ¶
Source

inst_frintn_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frintn_v ¶
Source

inst_frintn_v :: inst_frintn_v_r_r

inst_frintn_v_r_r ¶
Source

inst_frintn_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frintp ¶
Source

inst_frintp :: inst_frintp_r_r

inst_frintp_r_r ¶
Source

inst_frintp_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frintp_v ¶
Source

inst_frintp_v :: inst_frintp_v_r_r

inst_frintp_v_r_r ¶
Source

inst_frintp_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frintx ¶
Source

inst_frintx :: inst_frintx_r_r

inst_frintx_r_r ¶
Source

inst_frintx_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frintx_v ¶
Source

inst_frintx_v :: inst_frintx_v_r_r

inst_frintx_v_r_r ¶
Source

inst_frintx_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frintz ¶
Source

inst_frintz :: inst_frintz_r_r

inst_frintz_r_r ¶
Source

inst_frintz_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frintz_v ¶
Source

inst_frintz_v :: inst_frintz_v_r_r

inst_frintz_v_r_r ¶
Source

inst_frintz_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frsqrte ¶
Source

inst_frsqrte :: inst_frsqrte_r_r

inst_frsqrte_r_r ¶
Source

inst_frsqrte_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_frsqrts ¶
Source

inst_frsqrts :: inst_frsqrts_r_r_r

inst_frsqrts_r_r_r ¶
Source

inst_frsqrts_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fsqrt ¶
Source

inst_fsqrt :: inst_fsqrt_r_r

inst_fsqrt_h ¶
Source

inst_fsqrt_h :: inst_fsqrt_h_r_r

inst_fsqrt_h_r_r ¶
Source

inst_fsqrt_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fsqrt_r_r ¶
Source

inst_fsqrt_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fsqrt_v ¶
Source

inst_fsqrt_v :: inst_fsqrt_v_r_r

inst_fsqrt_v_r_r ¶
Source

inst_fsqrt_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_fsub ¶
Source

inst_fsub :: inst_fsub_r_r_r

inst_fsub_h ¶
Source

inst_fsub_h :: inst_fsub_h_r_r_r

inst_fsub_h_r_r_r ¶
Source

inst_fsub_h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fsub_r_r_r ¶
Source

inst_fsub_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_fsub_v ¶
Source

inst_fsub_v :: inst_fsub_v_r_r_r

inst_fsub_v_r_r_r ¶
Source

inst_fsub_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_gmi ¶
Source

inst_gmi :: inst_gmi_r_r_r

inst_gmi_r_r_r ¶
Source

inst_gmi_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_hint ¶
Source

inst_hint :: inst_hint_i

inst_hint_i ¶
Source

inst_hint_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_hlt ¶
Source

inst_hlt :: inst_hlt_i

inst_hlt_i ¶
Source

inst_hlt_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_hvc ¶
Source

inst_hvc :: inst_hvc_i

inst_hvc_i ¶
Source

inst_hvc_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_ic_iallu ¶
Source

inst_ic_iallu :: inst_ic_iallu_none

inst_ic_iallu_none ¶
Source

inst_ic_iallu_none :: proc "contextless" () -> Instruction {…}

inst_ic_ialluis ¶
Source

inst_ic_ialluis :: inst_ic_ialluis_none

inst_ic_ialluis_none ¶
Source

inst_ic_ialluis_none :: proc "contextless" () -> Instruction {…}

inst_ic_ivau ¶
Source

inst_ic_ivau :: inst_ic_ivau_r

inst_ic_ivau_r ¶
Source

inst_ic_ivau_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_ins_r_i_r ¶
Source

inst_ins_r_i_r :: proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction {…}

Related Procedure Groups

inst_ins

inst_ins_r_i_r_i ¶
Source

inst_ins_r_i_r_i :: proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction {…}

Related Procedure Groups

inst_ins

inst_irg ¶
Source

inst_irg :: inst_irg_r_r_r

inst_irg_r_r_r ¶
Source

inst_irg_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_isb ¶
Source

inst_isb :: inst_isb_i

inst_isb_i ¶
Source

inst_isb_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_ld1 ¶
Source

inst_ld1 :: inst_ld1_r_m

inst_ld1_lane ¶
Source

inst_ld1_lane :: inst_ld1_lane_r_i_m

inst_ld1_lane_r_i_m ¶
Source

inst_ld1_lane_r_i_m :: proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction {…}

inst_ld1_r_m ¶
Source

inst_ld1_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ld1r ¶
Source

inst_ld1r :: inst_ld1r_r_m

inst_ld1r_r_m ¶
Source

inst_ld1r_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ld2 ¶
Source

inst_ld2 :: inst_ld2_r_m

inst_ld2_lane ¶
Source

inst_ld2_lane :: inst_ld2_lane_r_i_m

inst_ld2_lane_r_i_m ¶
Source

inst_ld2_lane_r_i_m :: proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction {…}

inst_ld2_r_m ¶
Source

inst_ld2_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ld2r ¶
Source

inst_ld2r :: inst_ld2r_r_m

inst_ld2r_r_m ¶
Source

inst_ld2r_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ld3 ¶
Source

inst_ld3 :: inst_ld3_r_m

inst_ld3_lane ¶
Source

inst_ld3_lane :: inst_ld3_lane_r_i_m

inst_ld3_lane_r_i_m ¶
Source

inst_ld3_lane_r_i_m :: proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction {…}

inst_ld3_r_m ¶
Source

inst_ld3_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ld3r ¶
Source

inst_ld3r :: inst_ld3r_r_m

inst_ld3r_r_m ¶
Source

inst_ld3r_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ld4 ¶
Source

inst_ld4 :: inst_ld4_r_m

inst_ld4_lane ¶
Source

inst_ld4_lane :: inst_ld4_lane_r_i_m

inst_ld4_lane_r_i_m ¶
Source

inst_ld4_lane_r_i_m :: proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction {…}

inst_ld4_r_m ¶
Source

inst_ld4_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ld4r ¶
Source

inst_ld4r :: inst_ld4r_r_m

inst_ld4r_r_m ¶
Source

inst_ld4r_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldadd ¶
Source

inst_ldadd :: inst_ldadd_r_r_m

inst_ldadd_r_r_m ¶
Source

inst_ldadd_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldadda ¶
Source

inst_ldadda :: inst_ldadda_r_r_m

inst_ldadda_r_r_m ¶
Source

inst_ldadda_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldaddal ¶
Source

inst_ldaddal :: inst_ldaddal_r_r_m

inst_ldaddal_r_r_m ¶
Source

inst_ldaddal_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldaddl ¶
Source

inst_ldaddl :: inst_ldaddl_r_r_m

inst_ldaddl_r_r_m ¶
Source

inst_ldaddl_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldapr ¶
Source

inst_ldapr :: inst_ldapr_r_m

inst_ldapr_r_m ¶
Source

inst_ldapr_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldaprb ¶
Source

inst_ldaprb :: inst_ldaprb_r_m

inst_ldaprb_r_m ¶
Source

inst_ldaprb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldaprh ¶
Source

inst_ldaprh :: inst_ldaprh_r_m

inst_ldaprh_r_m ¶
Source

inst_ldaprh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldapur ¶
Source

inst_ldapur :: inst_ldapur_r_m

inst_ldapur_r_m ¶
Source

inst_ldapur_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldapurb ¶
Source

inst_ldapurb :: inst_ldapurb_r_m

inst_ldapurb_r_m ¶
Source

inst_ldapurb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldapurh ¶
Source

inst_ldapurh :: inst_ldapurh_r_m

inst_ldapurh_r_m ¶
Source

inst_ldapurh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldapursb ¶
Source

inst_ldapursb :: inst_ldapursb_r_m

inst_ldapursb_r_m ¶
Source

inst_ldapursb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldapursh ¶
Source

inst_ldapursh :: inst_ldapursh_r_m

inst_ldapursh_r_m ¶
Source

inst_ldapursh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldapursw ¶
Source

inst_ldapursw :: inst_ldapursw_r_m

inst_ldapursw_r_m ¶
Source

inst_ldapursw_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldar ¶
Source

inst_ldar :: inst_ldar_r_m

inst_ldar_r_m ¶
Source

inst_ldar_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldarb ¶
Source

inst_ldarb :: inst_ldarb_r_m

inst_ldarb_r_m ¶
Source

inst_ldarb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldarh ¶
Source

inst_ldarh :: inst_ldarh_r_m

inst_ldarh_r_m ¶
Source

inst_ldarh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldaxp ¶
Source

inst_ldaxp :: inst_ldaxp_r_r_m

inst_ldaxp_r_r_m ¶
Source

inst_ldaxp_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldaxr ¶
Source

inst_ldaxr :: inst_ldaxr_r_m

inst_ldaxr_r_m ¶
Source

inst_ldaxr_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldaxrb ¶
Source

inst_ldaxrb :: inst_ldaxrb_r_m

inst_ldaxrb_r_m ¶
Source

inst_ldaxrb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldaxrh ¶
Source

inst_ldaxrh :: inst_ldaxrh_r_m

inst_ldaxrh_r_m ¶
Source

inst_ldaxrh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldclr ¶
Source

inst_ldclr :: inst_ldclr_r_r_m

inst_ldclr_r_r_m ¶
Source

inst_ldclr_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldclra ¶
Source

inst_ldclra :: inst_ldclra_r_r_m

inst_ldclra_r_r_m ¶
Source

inst_ldclra_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldclral ¶
Source

inst_ldclral :: inst_ldclral_r_r_m

inst_ldclral_r_r_m ¶
Source

inst_ldclral_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldclrl ¶
Source

inst_ldclrl :: inst_ldclrl_r_r_m

inst_ldclrl_r_r_m ¶
Source

inst_ldclrl_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldeor ¶
Source

inst_ldeor :: inst_ldeor_r_r_m

inst_ldeor_r_r_m ¶
Source

inst_ldeor_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldeora ¶
Source

inst_ldeora :: inst_ldeora_r_r_m

inst_ldeora_r_r_m ¶
Source

inst_ldeora_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldeoral ¶
Source

inst_ldeoral :: inst_ldeoral_r_r_m

inst_ldeoral_r_r_m ¶
Source

inst_ldeoral_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldeorl ¶
Source

inst_ldeorl :: inst_ldeorl_r_r_m

inst_ldeorl_r_r_m ¶
Source

inst_ldeorl_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldg ¶
Source

inst_ldg :: inst_ldg_r_m

inst_ldg_r_m ¶
Source

inst_ldg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldgm ¶
Source

inst_ldgm :: inst_ldgm_r_m

inst_ldgm_r_m ¶
Source

inst_ldgm_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldnp ¶
Source

inst_ldnp :: inst_ldnp_r_r_m

inst_ldnp_r_r_m ¶
Source

inst_ldnp_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldp ¶
Source

inst_ldp :: inst_ldp_r_r_m

inst_ldp_post ¶
Source

inst_ldp_post :: inst_ldp_post_r_r_m

inst_ldp_post_r_r_m ¶
Source

inst_ldp_post_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldp_pre ¶
Source

inst_ldp_pre :: inst_ldp_pre_r_r_m

inst_ldp_pre_r_r_m ¶
Source

inst_ldp_pre_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldp_r_r_m ¶
Source

inst_ldp_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldp_stp ¶
Source

inst_ldp_stp :: proc "contextless" (m: Mnemonic, rt, rt2: Register, mm: Memory) -> Instruction {…}

Load/store pair: Rt, Rt2, memory.

inst_ldp_v ¶
Source

inst_ldp_v :: inst_ldp_v_r_r_m

inst_ldp_v_r_r_m ¶
Source

inst_ldp_v_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldpsw ¶
Source

inst_ldpsw :: inst_ldpsw_r_r_m

inst_ldpsw_post ¶
Source

inst_ldpsw_post :: inst_ldpsw_post_r_r_m

inst_ldpsw_post_r_r_m ¶
Source

inst_ldpsw_post_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldpsw_pre ¶
Source

inst_ldpsw_pre :: inst_ldpsw_pre_r_r_m

inst_ldpsw_pre_r_r_m ¶
Source

inst_ldpsw_pre_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldpsw_r_r_m ¶
Source

inst_ldpsw_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldr ¶
Source

inst_ldr :: inst_ldr_r_m

inst_ldr_lit ¶
Source

inst_ldr_lit :: inst_ldr_lit_r_l

inst_ldr_lit_r_l ¶
Source

inst_ldr_lit_r_l :: proc "contextless" (dst: Register, label: u32) -> Instruction {…}

inst_ldr_post ¶
Source

inst_ldr_post :: inst_ldr_post_r_m

inst_ldr_post_r_m ¶
Source

inst_ldr_post_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldr_pre ¶
Source

inst_ldr_pre :: inst_ldr_pre_r_m

inst_ldr_pre_r_m ¶
Source

inst_ldr_pre_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldr_r_m ¶
Source

inst_ldr_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldr_reg ¶
Source

inst_ldr_reg :: inst_ldr_reg_r_m

inst_ldr_reg_r_m ¶
Source

inst_ldr_reg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldr_v ¶
Source

inst_ldr_v :: inst_ldr_v_r_m

inst_ldr_v_r_m ¶
Source

inst_ldr_v_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldraa ¶
Source

inst_ldraa :: inst_ldraa_r_m

inst_ldraa_pre ¶
Source

inst_ldraa_pre :: inst_ldraa_pre_r_m

inst_ldraa_pre_r_m ¶
Source

inst_ldraa_pre_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldraa_r_m ¶
Source

inst_ldraa_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrab ¶
Source

inst_ldrab :: inst_ldrab_r_m

inst_ldrab_pre ¶
Source

inst_ldrab_pre :: inst_ldrab_pre_r_m

inst_ldrab_pre_r_m ¶
Source

inst_ldrab_pre_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrab_r_m ¶
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inst_ldrab_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrb ¶
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inst_ldrb :: inst_ldrb_r_m

inst_ldrb_post ¶
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inst_ldrb_post :: inst_ldrb_post_r_m

inst_ldrb_post_r_m ¶
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inst_ldrb_post_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrb_pre ¶
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inst_ldrb_pre :: inst_ldrb_pre_r_m

inst_ldrb_pre_r_m ¶
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inst_ldrb_pre_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrb_r_m ¶
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inst_ldrb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrb_reg ¶
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inst_ldrb_reg :: inst_ldrb_reg_r_m

inst_ldrb_reg_r_m ¶
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inst_ldrb_reg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrh ¶
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inst_ldrh :: inst_ldrh_r_m

inst_ldrh_post ¶
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inst_ldrh_post :: inst_ldrh_post_r_m

inst_ldrh_post_r_m ¶
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inst_ldrh_post_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrh_pre ¶
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inst_ldrh_pre :: inst_ldrh_pre_r_m

inst_ldrh_pre_r_m ¶
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inst_ldrh_pre_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrh_r_m ¶
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inst_ldrh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrh_reg ¶
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inst_ldrh_reg :: inst_ldrh_reg_r_m

inst_ldrh_reg_r_m ¶
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inst_ldrh_reg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrsb ¶
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inst_ldrsb :: inst_ldrsb_r_m

inst_ldrsb_r_m ¶
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inst_ldrsb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrsb_reg ¶
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inst_ldrsb_reg :: inst_ldrsb_reg_r_m

inst_ldrsb_reg_r_m ¶
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inst_ldrsb_reg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrsh ¶
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inst_ldrsh :: inst_ldrsh_r_m

inst_ldrsh_r_m ¶
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inst_ldrsh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrsh_reg ¶
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inst_ldrsh_reg :: inst_ldrsh_reg_r_m

inst_ldrsh_reg_r_m ¶
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inst_ldrsh_reg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrsw ¶
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inst_ldrsw :: inst_ldrsw_r_m

inst_ldrsw_r_m ¶
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inst_ldrsw_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldrsw_reg ¶
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inst_ldrsw_reg :: inst_ldrsw_reg_r_m

inst_ldrsw_reg_r_m ¶
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inst_ldrsw_reg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldset ¶
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inst_ldset :: inst_ldset_r_r_m

inst_ldset_r_r_m ¶
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inst_ldset_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldseta ¶
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inst_ldseta :: inst_ldseta_r_r_m

inst_ldseta_r_r_m ¶
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inst_ldseta_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldsetal ¶
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inst_ldsetal :: inst_ldsetal_r_r_m

inst_ldsetal_r_r_m ¶
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inst_ldsetal_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldsetl ¶
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inst_ldsetl :: inst_ldsetl_r_r_m

inst_ldsetl_r_r_m ¶
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inst_ldsetl_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldsmax ¶
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inst_ldsmax :: inst_ldsmax_r_r_m

inst_ldsmax_r_r_m ¶
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inst_ldsmax_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldsmaxa ¶
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inst_ldsmaxa :: inst_ldsmaxa_r_r_m

inst_ldsmaxa_r_r_m ¶
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inst_ldsmaxa_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldsmaxal ¶
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inst_ldsmaxal :: inst_ldsmaxal_r_r_m

inst_ldsmaxal_r_r_m ¶
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inst_ldsmaxal_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldsmaxl ¶
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inst_ldsmaxl :: inst_ldsmaxl_r_r_m

inst_ldsmaxl_r_r_m ¶
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inst_ldsmaxl_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldsmin ¶
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inst_ldsmin :: inst_ldsmin_r_r_m

inst_ldsmin_r_r_m ¶
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inst_ldsmin_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldsmina ¶
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inst_ldsmina :: inst_ldsmina_r_r_m

inst_ldsmina_r_r_m ¶
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inst_ldsmina_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldsminal ¶
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inst_ldsminal :: inst_ldsminal_r_r_m

inst_ldsminal_r_r_m ¶
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inst_ldsminal_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldsminl ¶
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inst_ldsminl :: inst_ldsminl_r_r_m

inst_ldsminl_r_r_m ¶
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inst_ldsminl_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldst ¶
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inst_ldst :: proc "contextless" (m: Mnemonic, rt: Register, mm: Memory) -> Instruction {…}

Load/store register: Rt + memory.

inst_ldumax ¶
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inst_ldumax :: inst_ldumax_r_r_m

inst_ldumax_r_r_m ¶
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inst_ldumax_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldumaxa ¶
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inst_ldumaxa :: inst_ldumaxa_r_r_m

inst_ldumaxa_r_r_m ¶
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inst_ldumaxa_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldumaxal ¶
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inst_ldumaxal :: inst_ldumaxal_r_r_m

inst_ldumaxal_r_r_m ¶
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inst_ldumaxal_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldumaxl ¶
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inst_ldumaxl :: inst_ldumaxl_r_r_m

inst_ldumaxl_r_r_m ¶
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inst_ldumaxl_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldumin ¶
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inst_ldumin :: inst_ldumin_r_r_m

inst_ldumin_r_r_m ¶
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inst_ldumin_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldumina ¶
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inst_ldumina :: inst_ldumina_r_r_m

inst_ldumina_r_r_m ¶
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inst_ldumina_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_lduminal ¶
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inst_lduminal :: inst_lduminal_r_r_m

inst_lduminal_r_r_m ¶
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inst_lduminal_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_lduminl ¶
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inst_lduminl :: inst_lduminl_r_r_m

inst_lduminl_r_r_m ¶
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inst_lduminl_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldur ¶
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inst_ldur :: inst_ldur_r_m

inst_ldur_r_m ¶
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inst_ldur_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldur_v ¶
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inst_ldur_v :: inst_ldur_v_r_m

inst_ldur_v_r_m ¶
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inst_ldur_v_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldurb ¶
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inst_ldurb :: inst_ldurb_r_m

inst_ldurb_r_m ¶
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inst_ldurb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldurh ¶
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inst_ldurh :: inst_ldurh_r_m

inst_ldurh_r_m ¶
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inst_ldurh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldursb ¶
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inst_ldursb :: inst_ldursb_r_m

inst_ldursb_r_m ¶
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inst_ldursb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldursh ¶
Source

inst_ldursh :: inst_ldursh_r_m

inst_ldursh_r_m ¶
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inst_ldursh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldursw ¶
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inst_ldursw :: inst_ldursw_r_m

inst_ldursw_r_m ¶
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inst_ldursw_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldxp ¶
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inst_ldxp :: inst_ldxp_r_r_m

inst_ldxp_r_r_m ¶
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inst_ldxp_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_ldxr ¶
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inst_ldxr :: inst_ldxr_r_m

inst_ldxr_r_m ¶
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inst_ldxr_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldxrb ¶
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inst_ldxrb :: inst_ldxrb_r_m

inst_ldxrb_r_m ¶
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inst_ldxrb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_ldxrh ¶
Source

inst_ldxrh :: inst_ldxrh_r_m

inst_ldxrh_r_m ¶
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inst_ldxrh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_lsl_imm ¶
Source

inst_lsl_imm :: inst_lsl_imm_r_r_i

inst_lsl_imm_r_r_i ¶
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inst_lsl_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_lslv ¶
Source

inst_lslv :: inst_lslv_r_r_r

inst_lslv_r_r_r ¶
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inst_lslv_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_lsr_imm ¶
Source

inst_lsr_imm :: inst_lsr_imm_r_r_i

inst_lsr_imm_r_r_i ¶
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inst_lsr_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_lsrv ¶
Source

inst_lsrv :: inst_lsrv_r_r_r

inst_lsrv_r_r_r ¶
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inst_lsrv_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_madd ¶
Source

inst_madd :: inst_madd_r_r_r_r

inst_madd_r_r_r_r ¶
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inst_madd_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_mla_v ¶
Source

inst_mla_v :: inst_mla_v_r_r_r

inst_mla_v_r_r_r ¶
Source

inst_mla_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_mls_v ¶
Source

inst_mls_v :: inst_mls_v_r_r_r

inst_mls_v_r_r_r ¶
Source

inst_mls_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_mov_bitmask ¶
Source

inst_mov_bitmask :: inst_mov_bitmask_r_i

inst_mov_bitmask_r_i ¶
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inst_mov_bitmask_r_i :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

inst_mov_imm ¶
Source

inst_mov_imm :: proc "contextless" (m: Mnemonic, rd: Register, imm: i64, hw: u8) -> Instruction {…}

MOVZ/MOVN/MOVK with explicit hw shift (0/16/32/48).

inst_mov_reg ¶
Source

inst_mov_reg :: inst_mov_reg_r_r

inst_mov_reg_r_r ¶
Source

inst_mov_reg_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_mov_v ¶
Source

inst_mov_v :: inst_mov_v_r_r

inst_mov_v_alias ¶
Source

inst_mov_v_alias :: inst_mov_v_alias_r_r

inst_mov_v_alias_r_r ¶
Source

inst_mov_v_alias_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_mov_v_r_r ¶
Source

inst_mov_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_movi ¶
Source

inst_movi :: inst_movi_r_i

inst_movi_r_i ¶
Source

inst_movi_r_i :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

inst_movk ¶
Source

inst_movk :: inst_movk_r_i_i

inst_movk_r_i_i ¶
Source

inst_movk_r_i_i :: proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction {…}

inst_movn ¶
Source

inst_movn :: inst_movn_r_i_i

inst_movn_r_i_i ¶
Source

inst_movn_r_i_i :: proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction {…}

inst_movz ¶
Source

inst_movz :: inst_movz_r_i_i

inst_movz_r_i_i ¶
Source

inst_movz_r_i_i :: proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction {…}

inst_mrs ¶
Source

inst_mrs :: inst_mrs_r_i

inst_mrs_r_i ¶
Source

inst_mrs_r_i :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

inst_msr_imm ¶
Source

inst_msr_imm :: inst_msr_imm_i_i

inst_msr_imm_i_i ¶
Source

inst_msr_imm_i_i :: proc "contextless" (imm: i64, imm2: i64) -> Instruction {…}

inst_msr_reg ¶
Source

inst_msr_reg :: inst_msr_reg_i_r

inst_msr_reg_i_r ¶
Source

inst_msr_reg_i_r :: proc "contextless" (imm: i64, src: Register) -> Instruction {…}

inst_msub ¶
Source

inst_msub :: inst_msub_r_r_r_r

inst_msub_r_r_r_r ¶
Source

inst_msub_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_mul_v ¶
Source

inst_mul_v :: inst_mul_v_r_r_r

inst_mul_v_r_r_r ¶
Source

inst_mul_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_mvn ¶
Source

inst_mvn :: inst_mvn_r_r

inst_mvn_r_r ¶
Source

inst_mvn_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_mvn_v ¶
Source

inst_mvn_v :: inst_mvn_v_r_r

inst_mvn_v_r_r ¶
Source

inst_mvn_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_mvni ¶
Source

inst_mvni :: inst_mvni_r_i

inst_mvni_r_i ¶
Source

inst_mvni_r_i :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

inst_neg_sr ¶
Source

inst_neg_sr :: inst_neg_sr_r_sh

inst_neg_sr_r_sh ¶
Source

inst_neg_sr_r_sh :: proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction {…}

inst_neg_v ¶
Source

inst_neg_v :: inst_neg_v_r_r

inst_neg_v_r_r ¶
Source

inst_neg_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_negs ¶
Source

inst_negs :: inst_negs_r_sh

inst_negs_r_sh ¶
Source

inst_negs_r_sh :: proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction {…}

inst_ngc ¶
Source

inst_ngc :: inst_ngc_r_r

inst_ngc_r_r ¶
Source

inst_ngc_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_ngcs ¶
Source

inst_ngcs :: inst_ngcs_r_r

inst_ngcs_r_r ¶
Source

inst_ngcs_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_none ¶
Source

inst_none :: proc "contextless" (m: Mnemonic) -> Instruction {…}

inst_nop ¶
Source

inst_nop :: inst_nop_none

inst_nop_none ¶
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inst_nop_none :: proc "contextless" () -> Instruction {…}

inst_not_v ¶
Source

inst_not_v :: inst_not_v_r_r

inst_not_v_alias ¶
Source

inst_not_v_alias :: inst_not_v_alias_r_r

inst_not_v_alias_r_r ¶
Source

inst_not_v_alias_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_not_v_r_r ¶
Source

inst_not_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_orn_sr ¶
Source

inst_orn_sr :: inst_orn_sr_r_r_sh

inst_orn_sr_r_r_sh ¶
Source

inst_orn_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_orn_v ¶
Source

inst_orn_v :: inst_orn_v_r_r_r

inst_orn_v_r_r_r ¶
Source

inst_orn_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_orr_imm ¶
Source

inst_orr_imm :: inst_orr_imm_r_r_i

inst_orr_imm_r_r_i ¶
Source

inst_orr_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_orr_sr ¶
Source

inst_orr_sr :: inst_orr_sr_r_r_sh

inst_orr_sr_r_r_sh ¶
Source

inst_orr_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_orr_v ¶
Source

inst_orr_v :: inst_orr_v_r_r_r

inst_orr_v_r_r_r ¶
Source

inst_orr_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_pacda ¶
Source

inst_pacda :: inst_pacda_r_r

inst_pacda_r_r ¶
Source

inst_pacda_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_pacdb ¶
Source

inst_pacdb :: inst_pacdb_r_r

inst_pacdb_r_r ¶
Source

inst_pacdb_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_pacdza ¶
Source

inst_pacdza :: inst_pacdza_r

inst_pacdza_r ¶
Source

inst_pacdza_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_pacdzb ¶
Source

inst_pacdzb :: inst_pacdzb_r

inst_pacdzb_r ¶
Source

inst_pacdzb_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_pacga ¶
Source

inst_pacga :: inst_pacga_r_r_r

inst_pacga_r_r_r ¶
Source

inst_pacga_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_pacia ¶
Source

inst_pacia :: inst_pacia_r_r

inst_pacia1716 ¶
Source

inst_pacia1716 :: inst_pacia1716_none

inst_pacia1716_none ¶
Source

inst_pacia1716_none :: proc "contextless" () -> Instruction {…}

inst_pacia_r_r ¶
Source

inst_pacia_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_paciasp ¶
Source

inst_paciasp :: inst_paciasp_none

inst_paciasp_none ¶
Source

inst_paciasp_none :: proc "contextless" () -> Instruction {…}

inst_pacib ¶
Source

inst_pacib :: inst_pacib_r_r

inst_pacib1716 ¶
Source

inst_pacib1716 :: inst_pacib1716_none

inst_pacib1716_none ¶
Source

inst_pacib1716_none :: proc "contextless" () -> Instruction {…}

inst_pacib_r_r ¶
Source

inst_pacib_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_pacibsp ¶
Source

inst_pacibsp :: inst_pacibsp_none

inst_pacibsp_none ¶
Source

inst_pacibsp_none :: proc "contextless" () -> Instruction {…}

inst_paciza ¶
Source

inst_paciza :: inst_paciza_r

inst_paciza_r ¶
Source

inst_paciza_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_pacizb ¶
Source

inst_pacizb :: inst_pacizb_r

inst_pacizb_r ¶
Source

inst_pacizb_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_pmull ¶
Source

inst_pmull :: inst_pmull_r_r_r

inst_pmull2 ¶
Source

inst_pmull2 :: inst_pmull2_r_r_r

inst_pmull2_r_r_r ¶
Source

inst_pmull2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_pmull_r_r_r ¶
Source

inst_pmull_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_prfm ¶
Source

inst_prfm :: inst_prfm_i_m

inst_prfm_i_m ¶
Source

inst_prfm_i_m :: proc "contextless" (imm: i64, mem: Memory) -> Instruction {…}

inst_prfm_lit ¶
Source

inst_prfm_lit :: inst_prfm_lit_i_l

inst_prfm_lit_i_l ¶
Source

inst_prfm_lit_i_l :: proc "contextless" (imm: i64, label: u32) -> Instruction {…}

inst_prfum ¶
Source

inst_prfum :: inst_prfum_i_m

inst_prfum_i_m ¶
Source

inst_prfum_i_m :: proc "contextless" (imm: i64, mem: Memory) -> Instruction {…}

inst_psb_csync ¶
Source

inst_psb_csync :: inst_psb_csync_none

inst_psb_csync_none ¶
Source

inst_psb_csync_none :: proc "contextless" () -> Instruction {…}

inst_r ¶
Source

inst_r :: proc "contextless" (m: Mnemonic, r: Register) -> Instruction {…}

Single-register (e.g. BR, BLR).

inst_r_i ¶
Source

inst_r_i :: proc "contextless" (m: Mnemonic, rd: Register, imm: i64) -> Instruction {…}

1-register + immediate (e.g. MOVZ).

inst_r_r ¶
Source

inst_r_r :: proc "contextless" (m: Mnemonic, rd, rn: Register) -> Instruction {…}

2-register (e.g. CLZ, RBIT).

inst_r_r_i ¶
Source

inst_r_r_i :: proc "contextless" (m: Mnemonic, rd, rn: Register, imm: i64) -> Instruction {…}

2-register + immediate (e.g. ADD imm).

inst_r_r_r ¶
Source

inst_r_r_r :: proc "contextless" (m: Mnemonic, rd, rn, rm: Register) -> Instruction {…}

3-register (e.g. ADD shifted, MUL, UDIV, ASRV).

inst_r_r_r_r ¶
Source

inst_r_r_r_r :: proc "contextless" (m: Mnemonic, rd, rn, rm, ra: Register) -> Instruction {…}

4-register R4-type (MADD, MSUB, SMADDL, ...).

inst_raddhn ¶
Source

inst_raddhn :: inst_raddhn_r_r_r

inst_raddhn2 ¶
Source

inst_raddhn2 :: inst_raddhn2_r_r_r

inst_raddhn2_r_r_r ¶
Source

inst_raddhn2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_raddhn_r_r_r ¶
Source

inst_raddhn_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_rax1 ¶
Source

inst_rax1 :: inst_rax1_r_r_r

inst_rax1_r_r_r ¶
Source

inst_rax1_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_rbit ¶
Source

inst_rbit :: inst_rbit_r_r

inst_rbit_r_r ¶
Source

inst_rbit_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_rbit_v ¶
Source

inst_rbit_v :: inst_rbit_v_r_r

inst_rbit_v_r_r ¶
Source

inst_rbit_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_ret_none ¶
Source

inst_ret_none :: proc "contextless" () -> Instruction {…}

Related Procedure Groups

inst_ret

inst_ret_r ¶
Source

inst_ret_r :: proc "contextless" (dst: Register) -> Instruction {…}

Related Procedure Groups

inst_ret

inst_retaa ¶
Source

inst_retaa :: inst_retaa_none

inst_retaa_none ¶
Source

inst_retaa_none :: proc "contextless" () -> Instruction {…}

inst_retab ¶
Source

inst_retab :: inst_retab_none

inst_retab_none ¶
Source

inst_retab_none :: proc "contextless" () -> Instruction {…}

inst_rev ¶
Source

inst_rev :: inst_rev_r_r

inst_rev16 ¶
Source

inst_rev16 :: inst_rev16_r_r

inst_rev16_r_r ¶
Source

inst_rev16_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_rev16_v ¶
Source

inst_rev16_v :: inst_rev16_v_r_r

inst_rev16_v_r_r ¶
Source

inst_rev16_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_rev32 ¶
Source

inst_rev32 :: inst_rev32_r_r

inst_rev32_r_r ¶
Source

inst_rev32_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_rev32_v ¶
Source

inst_rev32_v :: inst_rev32_v_r_r

inst_rev32_v_r_r ¶
Source

inst_rev32_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_rev64 ¶
Source

inst_rev64 :: inst_rev64_r_r

inst_rev64_r_r ¶
Source

inst_rev64_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_rev_r_r ¶
Source

inst_rev_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_ror_imm ¶
Source

inst_ror_imm :: inst_ror_imm_r_r_i

inst_ror_imm_r_r_i ¶
Source

inst_ror_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_rorv ¶
Source

inst_rorv :: inst_rorv_r_r_r

inst_rorv_r_r_r ¶
Source

inst_rorv_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_rshrn ¶
Source

inst_rshrn :: inst_rshrn_r_r_i

inst_rshrn2 ¶
Source

inst_rshrn2 :: inst_rshrn2_r_r_i

inst_rshrn2_r_r_i ¶
Source

inst_rshrn2_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_rshrn_r_r_i ¶
Source

inst_rshrn_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_rsubhn ¶
Source

inst_rsubhn :: inst_rsubhn_r_r_r

inst_rsubhn2 ¶
Source

inst_rsubhn2 :: inst_rsubhn2_r_r_r

inst_rsubhn2_r_r_r ¶
Source

inst_rsubhn2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_rsubhn_r_r_r ¶
Source

inst_rsubhn_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_saba ¶
Source

inst_saba :: inst_saba_r_r_r

inst_saba_r_r_r ¶
Source

inst_saba_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sabd ¶
Source

inst_sabd :: inst_sabd_r_r_r

inst_sabd_r_r_r ¶
Source

inst_sabd_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sadalp ¶
Source

inst_sadalp :: inst_sadalp_r_r

inst_sadalp_r_r ¶
Source

inst_sadalp_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_saddl ¶
Source

inst_saddl :: inst_saddl_r_r_r

inst_saddl2 ¶
Source

inst_saddl2 :: inst_saddl2_r_r_r

inst_saddl2_r_r_r ¶
Source

inst_saddl2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_saddl_r_r_r ¶
Source

inst_saddl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_saddlp ¶
Source

inst_saddlp :: inst_saddlp_r_r

inst_saddlp_r_r ¶
Source

inst_saddlp_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_saddlv ¶
Source

inst_saddlv :: inst_saddlv_r_r

inst_saddlv_r_r ¶
Source

inst_saddlv_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_saddw ¶
Source

inst_saddw :: inst_saddw_r_r_r

inst_saddw2 ¶
Source

inst_saddw2 :: inst_saddw2_r_r_r

inst_saddw2_r_r_r ¶
Source

inst_saddw2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_saddw_r_r_r ¶
Source

inst_saddw_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sb ¶
Source

inst_sb :: inst_sb_none

inst_sb_none ¶
Source

inst_sb_none :: proc "contextless" () -> Instruction {…}

inst_sbc ¶
Source

inst_sbc :: inst_sbc_r_r_r

inst_sbc_r_r_r ¶
Source

inst_sbc_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sbcs ¶
Source

inst_sbcs :: inst_sbcs_r_r_r

inst_sbcs_r_r_r ¶
Source

inst_sbcs_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_scvtf ¶
Source

inst_scvtf :: inst_scvtf_r_r

inst_scvtf_h ¶
Source

inst_scvtf_h :: inst_scvtf_h_r_r

inst_scvtf_h_r_r ¶
Source

inst_scvtf_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_scvtf_r_r ¶
Source

inst_scvtf_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_scvtf_v ¶
Source

inst_scvtf_v :: inst_scvtf_v_r_r

inst_scvtf_v_r_r ¶
Source

inst_scvtf_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sdiv ¶
Source

inst_sdiv :: inst_sdiv_r_r_r

inst_sdiv_r_r_r ¶
Source

inst_sdiv_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sdot ¶
Source

inst_sdot :: inst_sdot_r_r_r

inst_sdot_r_r_r ¶
Source

inst_sdot_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sete ¶
Source

inst_sete :: inst_sete_r_r_r

inst_sete_r_r_r ¶
Source

inst_sete_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_setm ¶
Source

inst_setm :: inst_setm_r_r_r

inst_setm_r_r_r ¶
Source

inst_setm_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_setp ¶
Source

inst_setp :: inst_setp_r_r_r

inst_setp_r_r_r ¶
Source

inst_setp_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sev ¶
Source

inst_sev :: inst_sev_none

inst_sev_none ¶
Source

inst_sev_none :: proc "contextless" () -> Instruction {…}

inst_sevl ¶
Source

inst_sevl :: inst_sevl_none

inst_sevl_none ¶
Source

inst_sevl_none :: proc "contextless" () -> Instruction {…}

inst_sha1c ¶
Source

inst_sha1c :: inst_sha1c_r_r_r

inst_sha1c_r_r_r ¶
Source

inst_sha1c_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sha1h ¶
Source

inst_sha1h :: inst_sha1h_r_r

inst_sha1h_r_r ¶
Source

inst_sha1h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sha1m ¶
Source

inst_sha1m :: inst_sha1m_r_r_r

inst_sha1m_r_r_r ¶
Source

inst_sha1m_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sha1p ¶
Source

inst_sha1p :: inst_sha1p_r_r_r

inst_sha1p_r_r_r ¶
Source

inst_sha1p_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sha1su0 ¶
Source

inst_sha1su0 :: inst_sha1su0_r_r_r

inst_sha1su0_r_r_r ¶
Source

inst_sha1su0_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sha1su1 ¶
Source

inst_sha1su1 :: inst_sha1su1_r_r

inst_sha1su1_r_r ¶
Source

inst_sha1su1_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sha256h ¶
Source

inst_sha256h :: inst_sha256h_r_r_r

inst_sha256h2 ¶
Source

inst_sha256h2 :: inst_sha256h2_r_r_r

inst_sha256h2_r_r_r ¶
Source

inst_sha256h2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sha256h_r_r_r ¶
Source

inst_sha256h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sha256su0 ¶
Source

inst_sha256su0 :: inst_sha256su0_r_r

inst_sha256su0_r_r ¶
Source

inst_sha256su0_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sha256su1 ¶
Source

inst_sha256su1 :: inst_sha256su1_r_r_r

inst_sha256su1_r_r_r ¶
Source

inst_sha256su1_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sha512h ¶
Source

inst_sha512h :: inst_sha512h_r_r_r

inst_sha512h2 ¶
Source

inst_sha512h2 :: inst_sha512h2_r_r_r

inst_sha512h2_r_r_r ¶
Source

inst_sha512h2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sha512h_r_r_r ¶
Source

inst_sha512h_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sha512su0 ¶
Source

inst_sha512su0 :: inst_sha512su0_r_r

inst_sha512su0_r_r ¶
Source

inst_sha512su0_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sha512su1 ¶
Source

inst_sha512su1 :: inst_sha512su1_r_r_r

inst_sha512su1_r_r_r ¶
Source

inst_sha512su1_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_shadd ¶
Source

inst_shadd :: inst_shadd_r_r_r

inst_shadd_r_r_r ¶
Source

inst_shadd_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_shl_v ¶
Source

inst_shl_v :: inst_shl_v_r_r_i

inst_shl_v_r_r_i ¶
Source

inst_shl_v_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_shrn ¶
Source

inst_shrn :: inst_shrn_r_r_i

inst_shrn2 ¶
Source

inst_shrn2 :: inst_shrn2_r_r_i

inst_shrn2_r_r_i ¶
Source

inst_shrn2_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_shrn_r_r_i ¶
Source

inst_shrn_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_shsub ¶
Source

inst_shsub :: inst_shsub_r_r_r

inst_shsub_r_r_r ¶
Source

inst_shsub_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sli ¶
Source

inst_sli :: inst_sli_r_r_i

inst_sli_r_r_i ¶
Source

inst_sli_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sm3partw1 ¶
Source

inst_sm3partw1 :: inst_sm3partw1_r_r_r

inst_sm3partw1_r_r_r ¶
Source

inst_sm3partw1_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sm3partw2 ¶
Source

inst_sm3partw2 :: inst_sm3partw2_r_r_r

inst_sm3partw2_r_r_r ¶
Source

inst_sm3partw2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sm3ss1 ¶
Source

inst_sm3ss1 :: inst_sm3ss1_r_r_r_r

inst_sm3ss1_r_r_r_r ¶
Source

inst_sm3ss1_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_sm3tt1a ¶
Source

inst_sm3tt1a :: inst_sm3tt1a_r_r_r

inst_sm3tt1a_r_r_r ¶
Source

inst_sm3tt1a_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sm3tt1b ¶
Source

inst_sm3tt1b :: inst_sm3tt1b_r_r_r

inst_sm3tt1b_r_r_r ¶
Source

inst_sm3tt1b_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sm3tt2a ¶
Source

inst_sm3tt2a :: inst_sm3tt2a_r_r_r

inst_sm3tt2a_r_r_r ¶
Source

inst_sm3tt2a_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sm3tt2b ¶
Source

inst_sm3tt2b :: inst_sm3tt2b_r_r_r

inst_sm3tt2b_r_r_r ¶
Source

inst_sm3tt2b_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sm4e ¶
Source

inst_sm4e :: inst_sm4e_r_r

inst_sm4e_r_r ¶
Source

inst_sm4e_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sm4ekey ¶
Source

inst_sm4ekey :: inst_sm4ekey_r_r_r

inst_sm4ekey_r_r_r ¶
Source

inst_sm4ekey_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_smaddl ¶
Source

inst_smaddl :: inst_smaddl_r_r_r_r

inst_smaddl_r_r_r_r ¶
Source

inst_smaddl_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_smax ¶
Source

inst_smax :: inst_smax_r_r_r

inst_smax_r_r_r ¶
Source

inst_smax_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_smaxp ¶
Source

inst_smaxp :: inst_smaxp_r_r_r

inst_smaxp_r_r_r ¶
Source

inst_smaxp_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_smaxv ¶
Source

inst_smaxv :: inst_smaxv_r_r

inst_smaxv_r_r ¶
Source

inst_smaxv_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_smc ¶
Source

inst_smc :: inst_smc_i

inst_smc_i ¶
Source

inst_smc_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_sme2_ld1b_x2 ¶
Source

inst_sme2_ld1b_x2 :: inst_sme2_ld1b_x2_z_p_m

inst_sme2_ld1b_x2_z_p_m ¶
Source

inst_sme2_ld1b_x2_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_ld1b_x4 ¶
Source

inst_sme2_ld1b_x4 :: inst_sme2_ld1b_x4_z_p_m

inst_sme2_ld1b_x4_z_p_m ¶
Source

inst_sme2_ld1b_x4_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_ld1d_x2 ¶
Source

inst_sme2_ld1d_x2 :: inst_sme2_ld1d_x2_z_p_m

inst_sme2_ld1d_x2_z_p_m ¶
Source

inst_sme2_ld1d_x2_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_ld1d_x4 ¶
Source

inst_sme2_ld1d_x4 :: inst_sme2_ld1d_x4_z_p_m

inst_sme2_ld1d_x4_z_p_m ¶
Source

inst_sme2_ld1d_x4_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_ld1h_x2 ¶
Source

inst_sme2_ld1h_x2 :: inst_sme2_ld1h_x2_z_p_m

inst_sme2_ld1h_x2_z_p_m ¶
Source

inst_sme2_ld1h_x2_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_ld1h_x4 ¶
Source

inst_sme2_ld1h_x4 :: inst_sme2_ld1h_x4_z_p_m

inst_sme2_ld1h_x4_z_p_m ¶
Source

inst_sme2_ld1h_x4_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_ld1w_x2 ¶
Source

inst_sme2_ld1w_x2 :: inst_sme2_ld1w_x2_z_p_m

inst_sme2_ld1w_x2_z_p_m ¶
Source

inst_sme2_ld1w_x2_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_ld1w_x4 ¶
Source

inst_sme2_ld1w_x4 :: inst_sme2_ld1w_x4_z_p_m

inst_sme2_ld1w_x4_z_p_m ¶
Source

inst_sme2_ld1w_x4_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_luti2_b ¶
Source

inst_sme2_luti2_b :: inst_sme2_luti2_b_z_z_z_i

inst_sme2_luti2_b_z_z_z_i ¶
Source

inst_sme2_luti2_b_z_z_z_i :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction {…}

inst_sme2_luti4_b ¶
Source

inst_sme2_luti4_b :: inst_sme2_luti4_b_z_z_z_i

inst_sme2_luti4_b_z_z_z_i ¶
Source

inst_sme2_luti4_b_z_z_z_i :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction {…}

inst_sme2_st1b_x2 ¶
Source

inst_sme2_st1b_x2 :: inst_sme2_st1b_x2_z_p_m

inst_sme2_st1b_x2_z_p_m ¶
Source

inst_sme2_st1b_x2_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_st1b_x4 ¶
Source

inst_sme2_st1b_x4 :: inst_sme2_st1b_x4_z_p_m

inst_sme2_st1b_x4_z_p_m ¶
Source

inst_sme2_st1b_x4_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_st1d_x2 ¶
Source

inst_sme2_st1d_x2 :: inst_sme2_st1d_x2_z_p_m

inst_sme2_st1d_x2_z_p_m ¶
Source

inst_sme2_st1d_x2_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_st1d_x4 ¶
Source

inst_sme2_st1d_x4 :: inst_sme2_st1d_x4_z_p_m

inst_sme2_st1d_x4_z_p_m ¶
Source

inst_sme2_st1d_x4_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_st1h_x2 ¶
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inst_sme2_st1h_x2 :: inst_sme2_st1h_x2_z_p_m

inst_sme2_st1h_x2_z_p_m ¶
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inst_sme2_st1h_x2_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_st1h_x4 ¶
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inst_sme2_st1h_x4 :: inst_sme2_st1h_x4_z_p_m

inst_sme2_st1h_x4_z_p_m ¶
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inst_sme2_st1h_x4_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_st1w_x2 ¶
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inst_sme2_st1w_x2 :: inst_sme2_st1w_x2_z_p_m

inst_sme2_st1w_x2_z_p_m ¶
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inst_sme2_st1w_x2_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_st1w_x4 ¶
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inst_sme2_st1w_x4 :: inst_sme2_st1w_x4_z_p_m

inst_sme2_st1w_x4_z_p_m ¶
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inst_sme2_st1w_x4_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sme2_uzp_3 ¶
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inst_sme2_uzp_3 :: inst_sme2_uzp_3_z_z_z

inst_sme2_uzp_3_z_z_z ¶
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inst_sme2_uzp_3_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme2_uzp_4 ¶
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inst_sme2_uzp_4 :: inst_sme2_uzp_4_z_z

inst_sme2_uzp_4_z_z ¶
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inst_sme2_uzp_4_z_z :: proc "contextless" (rz: u8, rz2: u8) -> Instruction {…}

inst_sme2_zip_3 ¶
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inst_sme2_zip_3 :: inst_sme2_zip_3_z_z_z

inst_sme2_zip_3_z_z_z ¶
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inst_sme2_zip_3_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme2_zip_4 ¶
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inst_sme2_zip_4 :: inst_sme2_zip_4_z_z

inst_sme2_zip_4_z_z ¶
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inst_sme2_zip_4_z_z :: proc "contextless" (rz: u8, rz2: u8) -> Instruction {…}

inst_sme_addha ¶
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inst_sme_addha :: inst_sme_addha_i_p_p_z

inst_sme_addha_i_p_p_z ¶
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inst_sme_addha_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_addva ¶
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inst_sme_addva :: inst_sme_addva_i_p_p_z

inst_sme_addva_i_p_p_z ¶
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inst_sme_addva_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_bfmopa ¶
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inst_sme_bfmopa :: inst_sme_bfmopa_i_p_p_z

inst_sme_bfmopa_i_p_p_z ¶
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inst_sme_bfmopa_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_bfmops ¶
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inst_sme_bfmops :: inst_sme_bfmops_i_p_p_z

inst_sme_bfmops_i_p_p_z ¶
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inst_sme_bfmops_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_fmopa ¶
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inst_sme_fmopa :: inst_sme_fmopa_i_p_p_z

inst_sme_fmopa_i_p_p_z ¶
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inst_sme_fmopa_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_fmops ¶
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inst_sme_fmops :: inst_sme_fmops_i_p_p_z

inst_sme_fmops_i_p_p_z ¶
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inst_sme_fmops_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_ld1b_tile ¶
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inst_sme_ld1b_tile :: inst_sme_ld1b_tile_i_p_m

inst_sme_ld1b_tile_i_p_m ¶
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inst_sme_ld1b_tile_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sme_ld1b_za ¶
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inst_sme_ld1b_za :: inst_sme_ld1b_tile_i_p_m

inst_sme_ld1d_tile ¶
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inst_sme_ld1d_tile :: inst_sme_ld1d_tile_i_p_m

inst_sme_ld1d_tile_i_p_m ¶
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inst_sme_ld1d_tile_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sme_ld1d_za ¶
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inst_sme_ld1d_za :: inst_sme_ld1d_tile_i_p_m

inst_sme_ld1h_tile ¶
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inst_sme_ld1h_tile :: inst_sme_ld1h_tile_i_p_m

inst_sme_ld1h_tile_i_p_m ¶
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inst_sme_ld1h_tile_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sme_ld1h_za ¶
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inst_sme_ld1h_za :: inst_sme_ld1h_tile_i_p_m

inst_sme_ld1q_tile ¶
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inst_sme_ld1q_tile :: inst_sme_ld1q_tile_i_p_m

inst_sme_ld1q_tile_i_p_m ¶
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inst_sme_ld1q_tile_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sme_ld1q_za ¶
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inst_sme_ld1q_za :: inst_sme_ld1q_tile_i_p_m

inst_sme_ld1w_tile ¶
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inst_sme_ld1w_tile :: inst_sme_ld1w_tile_i_p_m

inst_sme_ld1w_tile_i_p_m ¶
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inst_sme_ld1w_tile_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sme_ld1w_za ¶
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inst_sme_ld1w_za :: inst_sme_ld1w_tile_i_p_m

inst_sme_ldr_za ¶
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inst_sme_ldr_za :: inst_sme_ldr_za_i_m

inst_sme_ldr_za_i_m ¶
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inst_sme_ldr_za_i_m :: proc "contextless" (imm: i64, mem: Memory) -> Instruction {…}

inst_sme_mova_tile_from_z ¶
Source

inst_sme_mova_tile_from_z :: inst_sme_mova_tile_from_z_i_p_z

inst_sme_mova_tile_from_z_i_p_z ¶
Source

inst_sme_mova_tile_from_z_i_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction {…}

inst_sme_mova_to_z ¶
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inst_sme_mova_to_z :: inst_sme_mova_z_from_tile_z_p_i

inst_sme_mova_to_za ¶
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inst_sme_mova_to_za :: inst_sme_mova_tile_from_z_i_p_z

inst_sme_mova_z_from_tile ¶
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inst_sme_mova_z_from_tile :: inst_sme_mova_z_from_tile_z_p_i

inst_sme_mova_z_from_tile_z_p_i ¶
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inst_sme_mova_z_from_tile_z_p_i :: proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction {…}

inst_sme_rdsvl ¶
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inst_sme_rdsvl :: inst_sme_rdsvl_r_i

inst_sme_rdsvl_r_i ¶
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inst_sme_rdsvl_r_i :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

inst_sme_smopa ¶
Source

inst_sme_smopa :: inst_sme_smopa_i_p_p_z

inst_sme_smopa_i_p_p_z ¶
Source

inst_sme_smopa_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_smops ¶
Source

inst_sme_smops :: inst_sme_smops_i_p_p_z

inst_sme_smops_i_p_p_z ¶
Source

inst_sme_smops_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_smstart ¶
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inst_sme_smstart :: inst_sme_smstart_none

inst_sme_smstart_none ¶
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inst_sme_smstart_none :: proc "contextless" () -> Instruction {…}

inst_sme_smstop ¶
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inst_sme_smstop :: inst_sme_smstop_none

inst_sme_smstop_none ¶
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inst_sme_smstop_none :: proc "contextless" () -> Instruction {…}

inst_sme_st1b_tile ¶
Source

inst_sme_st1b_tile :: inst_sme_st1b_tile_i_p_m

inst_sme_st1b_tile_i_p_m ¶
Source

inst_sme_st1b_tile_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sme_st1b_za ¶
Source

inst_sme_st1b_za :: inst_sme_st1b_tile_i_p_m

inst_sme_st1d_tile ¶
Source

inst_sme_st1d_tile :: inst_sme_st1d_tile_i_p_m

inst_sme_st1d_tile_i_p_m ¶
Source

inst_sme_st1d_tile_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sme_st1d_za ¶
Source

inst_sme_st1d_za :: inst_sme_st1d_tile_i_p_m

inst_sme_st1h_tile ¶
Source

inst_sme_st1h_tile :: inst_sme_st1h_tile_i_p_m

inst_sme_st1h_tile_i_p_m ¶
Source

inst_sme_st1h_tile_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sme_st1h_za ¶
Source

inst_sme_st1h_za :: inst_sme_st1h_tile_i_p_m

inst_sme_st1q_tile ¶
Source

inst_sme_st1q_tile :: inst_sme_st1q_tile_i_p_m

inst_sme_st1q_tile_i_p_m ¶
Source

inst_sme_st1q_tile_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sme_st1q_za ¶
Source

inst_sme_st1q_za :: inst_sme_st1q_tile_i_p_m

inst_sme_st1w_tile ¶
Source

inst_sme_st1w_tile :: inst_sme_st1w_tile_i_p_m

inst_sme_st1w_tile_i_p_m ¶
Source

inst_sme_st1w_tile_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sme_st1w_za ¶
Source

inst_sme_st1w_za :: inst_sme_st1w_tile_i_p_m

inst_sme_str_za ¶
Source

inst_sme_str_za :: inst_sme_str_za_i_m

inst_sme_str_za_i_m ¶
Source

inst_sme_str_za_i_m :: proc "contextless" (imm: i64, mem: Memory) -> Instruction {…}

inst_sme_sumopa ¶
Source

inst_sme_sumopa :: inst_sme_sumopa_i_p_p_z

inst_sme_sumopa_i_p_p_z ¶
Source

inst_sme_sumopa_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_umopa ¶
Source

inst_sme_umopa :: inst_sme_umopa_i_p_p_z

inst_sme_umopa_i_p_p_z ¶
Source

inst_sme_umopa_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_umops ¶
Source

inst_sme_umops :: inst_sme_umops_i_p_p_z

inst_sme_umops_i_p_p_z ¶
Source

inst_sme_umops_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_usmopa ¶
Source

inst_sme_usmopa :: inst_sme_usmopa_i_p_p_z

inst_sme_usmopa_i_p_p_z ¶
Source

inst_sme_usmopa_i_p_p_z :: proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sme_zero ¶
Source

inst_sme_zero :: inst_sme_zero_i

inst_sme_zero_i ¶
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inst_sme_zero_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_smin ¶
Source

inst_smin :: inst_smin_r_r_r

inst_smin_r_r_r ¶
Source

inst_smin_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sminp ¶
Source

inst_sminp :: inst_sminp_r_r_r

inst_sminp_r_r_r ¶
Source

inst_sminp_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sminv ¶
Source

inst_sminv :: inst_sminv_r_r

inst_sminv_r_r ¶
Source

inst_sminv_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_smlal ¶
Source

inst_smlal :: inst_smlal_r_r_r

inst_smlal2 ¶
Source

inst_smlal2 :: inst_smlal2_r_r_r

inst_smlal2_r_r_r ¶
Source

inst_smlal2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_smlal_r_r_r ¶
Source

inst_smlal_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_smlsl ¶
Source

inst_smlsl :: inst_smlsl_r_r_r

inst_smlsl2 ¶
Source

inst_smlsl2 :: inst_smlsl2_r_r_r

inst_smlsl2_r_r_r ¶
Source

inst_smlsl2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_smlsl_r_r_r ¶
Source

inst_smlsl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_smsubl ¶
Source

inst_smsubl :: inst_smsubl_r_r_r_r

inst_smsubl_r_r_r_r ¶
Source

inst_smsubl_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_smulh ¶
Source

inst_smulh :: inst_smulh_r_r_r

inst_smulh_r_r_r ¶
Source

inst_smulh_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_smull2_v ¶
Source

inst_smull2_v :: inst_smull2_v_r_r_r

inst_smull2_v_r_r_r ¶
Source

inst_smull2_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_smull_v ¶
Source

inst_smull_v :: inst_smull_v_r_r_r

inst_smull_v_r_r_r ¶
Source

inst_smull_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sqadd ¶
Source

inst_sqadd :: inst_sqadd_r_r_r

inst_sqadd_r_r_r ¶
Source

inst_sqadd_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sqdmlal ¶
Source

inst_sqdmlal :: inst_sqdmlal_r_r_r

inst_sqdmlal2 ¶
Source

inst_sqdmlal2 :: inst_sqdmlal2_r_r_r

inst_sqdmlal2_r_r_r ¶
Source

inst_sqdmlal2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sqdmlal_r_r_r ¶
Source

inst_sqdmlal_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sqdmlsl ¶
Source

inst_sqdmlsl :: inst_sqdmlsl_r_r_r

inst_sqdmlsl2 ¶
Source

inst_sqdmlsl2 :: inst_sqdmlsl2_r_r_r

inst_sqdmlsl2_r_r_r ¶
Source

inst_sqdmlsl2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sqdmlsl_r_r_r ¶
Source

inst_sqdmlsl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sqdmulh ¶
Source

inst_sqdmulh :: inst_sqdmulh_r_r_r

inst_sqdmulh_r_r_r ¶
Source

inst_sqdmulh_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sqdmull ¶
Source

inst_sqdmull :: inst_sqdmull_r_r_r

inst_sqdmull2 ¶
Source

inst_sqdmull2 :: inst_sqdmull2_r_r_r

inst_sqdmull2_r_r_r ¶
Source

inst_sqdmull2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sqdmull_r_r_r ¶
Source

inst_sqdmull_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sqrdmulh ¶
Source

inst_sqrdmulh :: inst_sqrdmulh_r_r_r

inst_sqrdmulh_r_r_r ¶
Source

inst_sqrdmulh_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sqrshrn ¶
Source

inst_sqrshrn :: inst_sqrshrn_r_r_i

inst_sqrshrn2 ¶
Source

inst_sqrshrn2 :: inst_sqrshrn2_r_r_i

inst_sqrshrn2_r_r_i ¶
Source

inst_sqrshrn2_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sqrshrn_r_r_i ¶
Source

inst_sqrshrn_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sqrshrun ¶
Source

inst_sqrshrun :: inst_sqrshrun_r_r_i

inst_sqrshrun2 ¶
Source

inst_sqrshrun2 :: inst_sqrshrun2_r_r_i

inst_sqrshrun2_r_r_i ¶
Source

inst_sqrshrun2_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sqrshrun_r_r_i ¶
Source

inst_sqrshrun_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sqshl_v ¶
Source

inst_sqshl_v :: inst_sqshl_v_r_r_i

inst_sqshl_v_r_r_i ¶
Source

inst_sqshl_v_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sqshlu ¶
Source

inst_sqshlu :: inst_sqshlu_r_r_i

inst_sqshlu_r_r_i ¶
Source

inst_sqshlu_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sqshrn ¶
Source

inst_sqshrn :: inst_sqshrn_r_r_i

inst_sqshrn2 ¶
Source

inst_sqshrn2 :: inst_sqshrn2_r_r_i

inst_sqshrn2_r_r_i ¶
Source

inst_sqshrn2_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sqshrn_r_r_i ¶
Source

inst_sqshrn_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sqshrun ¶
Source

inst_sqshrun :: inst_sqshrun_r_r_i

inst_sqshrun2 ¶
Source

inst_sqshrun2 :: inst_sqshrun2_r_r_i

inst_sqshrun2_r_r_i ¶
Source

inst_sqshrun2_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sqshrun_r_r_i ¶
Source

inst_sqshrun_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sqsub ¶
Source

inst_sqsub :: inst_sqsub_r_r_r

inst_sqsub_r_r_r ¶
Source

inst_sqsub_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sqxtn ¶
Source

inst_sqxtn :: inst_sqxtn_r_r

inst_sqxtn2 ¶
Source

inst_sqxtn2 :: inst_sqxtn2_r_r

inst_sqxtn2_r_r ¶
Source

inst_sqxtn2_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sqxtn_r_r ¶
Source

inst_sqxtn_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sqxtun ¶
Source

inst_sqxtun :: inst_sqxtun_r_r

inst_sqxtun2 ¶
Source

inst_sqxtun2 :: inst_sqxtun2_r_r

inst_sqxtun2_r_r ¶
Source

inst_sqxtun2_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sqxtun_r_r ¶
Source

inst_sqxtun_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_srhadd ¶
Source

inst_srhadd :: inst_srhadd_r_r_r

inst_srhadd_r_r_r ¶
Source

inst_srhadd_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sri ¶
Source

inst_sri :: inst_sri_r_r_i

inst_sri_r_r_i ¶
Source

inst_sri_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_srshl ¶
Source

inst_srshl :: inst_srshl_r_r_r

inst_srshl_r_r_r ¶
Source

inst_srshl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_srshr ¶
Source

inst_srshr :: inst_srshr_r_r_i

inst_srshr_r_r_i ¶
Source

inst_srshr_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_srsra ¶
Source

inst_srsra :: inst_srsra_r_r_i

inst_srsra_r_r_i ¶
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inst_srsra_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sshl ¶
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inst_sshl :: inst_sshl_r_r_r

inst_sshl_r_r_r ¶
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inst_sshl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_sshll ¶
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inst_sshll :: inst_sshll_r_r_i

inst_sshll2 ¶
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inst_sshll2 :: inst_sshll2_r_r_i

inst_sshll2_r_r_i ¶
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inst_sshll2_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sshll_r_r_i ¶
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inst_sshll_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sshr ¶
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inst_sshr :: inst_sshr_r_r_i

inst_sshr_r_r_i ¶
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inst_sshr_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_ssra ¶
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inst_ssra :: inst_ssra_r_r_i

inst_ssra_r_r_i ¶
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inst_ssra_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_ssubl ¶
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inst_ssubl :: inst_ssubl_r_r_r

inst_ssubl2 ¶
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inst_ssubl2 :: inst_ssubl2_r_r_r

inst_ssubl2_r_r_r ¶
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inst_ssubl2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_ssubl_r_r_r ¶
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inst_ssubl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_ssubw ¶
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inst_ssubw :: inst_ssubw_r_r_r

inst_ssubw2 ¶
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inst_ssubw2 :: inst_ssubw2_r_r_r

inst_ssubw2_r_r_r ¶
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inst_ssubw2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_ssubw_r_r_r ¶
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inst_ssubw_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_st1 ¶
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inst_st1 :: inst_st1_r_m

inst_st1_lane ¶
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inst_st1_lane :: inst_st1_lane_r_i_m

inst_st1_lane_r_i_m ¶
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inst_st1_lane_r_i_m :: proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction {…}

inst_st1_r_m ¶
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inst_st1_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_st2 ¶
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inst_st2 :: inst_st2_r_m

inst_st2_lane ¶
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inst_st2_lane :: inst_st2_lane_r_i_m

inst_st2_lane_r_i_m ¶
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inst_st2_lane_r_i_m :: proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction {…}

inst_st2_r_m ¶
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inst_st2_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_st2g ¶
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inst_st2g :: inst_st2g_r_m

inst_st2g_r_m ¶
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inst_st2g_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_st3 ¶
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inst_st3 :: inst_st3_r_m

inst_st3_lane ¶
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inst_st3_lane :: inst_st3_lane_r_i_m

inst_st3_lane_r_i_m ¶
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inst_st3_lane_r_i_m :: proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction {…}

inst_st3_r_m ¶
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inst_st3_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_st4 ¶
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inst_st4 :: inst_st4_r_m

inst_st4_lane ¶
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inst_st4_lane :: inst_st4_lane_r_i_m

inst_st4_lane_r_i_m ¶
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inst_st4_lane_r_i_m :: proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction {…}

inst_st4_r_m ¶
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inst_st4_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stg ¶
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inst_stg :: inst_stg_r_m

inst_stg_r_m ¶
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inst_stg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stgm ¶
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inst_stgm :: inst_stgm_r_m

inst_stgm_r_m ¶
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inst_stgm_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stgp ¶
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inst_stgp :: inst_stgp_r_r_m

inst_stgp_r_r_m ¶
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inst_stgp_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_stlr ¶
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inst_stlr :: inst_stlr_r_m

inst_stlr_r_m ¶
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inst_stlr_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stlrb ¶
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inst_stlrb :: inst_stlrb_r_m

inst_stlrb_r_m ¶
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inst_stlrb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stlrh ¶
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inst_stlrh :: inst_stlrh_r_m

inst_stlrh_r_m ¶
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inst_stlrh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stlur ¶
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inst_stlur :: inst_stlur_r_m

inst_stlur_r_m ¶
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inst_stlur_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stlurb ¶
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inst_stlurb :: inst_stlurb_r_m

inst_stlurb_r_m ¶
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inst_stlurb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stlurh ¶
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inst_stlurh :: inst_stlurh_r_m

inst_stlurh_r_m ¶
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inst_stlurh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stlxp ¶
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inst_stlxp :: inst_stlxp_r_r_r_m

inst_stlxp_r_r_r_m ¶
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inst_stlxp_r_r_r_m :: proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction {…}

inst_stlxr ¶
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inst_stlxr :: inst_stlxr_r_r_m

inst_stlxr_r_r_m ¶
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inst_stlxr_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_stlxrb ¶
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inst_stlxrb :: inst_stlxrb_r_r_m

inst_stlxrb_r_r_m ¶
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inst_stlxrb_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_stlxrh ¶
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inst_stlxrh :: inst_stlxrh_r_r_m

inst_stlxrh_r_r_m ¶
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inst_stlxrh_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_stnp ¶
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inst_stnp :: inst_stnp_r_r_m

inst_stnp_r_r_m ¶
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inst_stnp_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_stp ¶
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inst_stp :: inst_stp_r_r_m

inst_stp_post ¶
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inst_stp_post :: inst_stp_post_r_r_m

inst_stp_post_r_r_m ¶
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inst_stp_post_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_stp_pre ¶
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inst_stp_pre :: inst_stp_pre_r_r_m

inst_stp_pre_r_r_m ¶
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inst_stp_pre_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_stp_r_r_m ¶
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inst_stp_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_stp_v ¶
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inst_stp_v :: inst_stp_v_r_r_m

inst_stp_v_r_r_m ¶
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inst_stp_v_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_str ¶
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inst_str :: inst_str_r_m

inst_str_post ¶
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inst_str_post :: inst_str_post_r_m

inst_str_post_r_m ¶
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inst_str_post_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_str_pre ¶
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inst_str_pre :: inst_str_pre_r_m

inst_str_pre_r_m ¶
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inst_str_pre_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_str_r_m ¶
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inst_str_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_str_reg ¶
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inst_str_reg :: inst_str_reg_r_m

inst_str_reg_r_m ¶
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inst_str_reg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_str_v ¶
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inst_str_v :: inst_str_v_r_m

inst_str_v_r_m ¶
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inst_str_v_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_strb ¶
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inst_strb :: inst_strb_r_m

inst_strb_post ¶
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inst_strb_post :: inst_strb_post_r_m

inst_strb_post_r_m ¶
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inst_strb_post_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_strb_pre ¶
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inst_strb_pre :: inst_strb_pre_r_m

inst_strb_pre_r_m ¶
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inst_strb_pre_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_strb_r_m ¶
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inst_strb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_strb_reg ¶
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inst_strb_reg :: inst_strb_reg_r_m

inst_strb_reg_r_m ¶
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inst_strb_reg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_strh ¶
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inst_strh :: inst_strh_r_m

inst_strh_post ¶
Source

inst_strh_post :: inst_strh_post_r_m

inst_strh_post_r_m ¶
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inst_strh_post_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_strh_pre ¶
Source

inst_strh_pre :: inst_strh_pre_r_m

inst_strh_pre_r_m ¶
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inst_strh_pre_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_strh_r_m ¶
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inst_strh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_strh_reg ¶
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inst_strh_reg :: inst_strh_reg_r_m

inst_strh_reg_r_m ¶
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inst_strh_reg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stur ¶
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inst_stur :: inst_stur_r_m

inst_stur_r_m ¶
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inst_stur_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stur_v ¶
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inst_stur_v :: inst_stur_v_r_m

inst_stur_v_r_m ¶
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inst_stur_v_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_sturb ¶
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inst_sturb :: inst_sturb_r_m

inst_sturb_r_m ¶
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inst_sturb_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_sturh ¶
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inst_sturh :: inst_sturh_r_m

inst_sturh_r_m ¶
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inst_sturh_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stxp ¶
Source

inst_stxp :: inst_stxp_r_r_r_m

inst_stxp_r_r_r_m ¶
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inst_stxp_r_r_r_m :: proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction {…}

inst_stxr ¶
Source

inst_stxr :: inst_stxr_r_r_m

inst_stxr_r_r_m ¶
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inst_stxr_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_stxrb ¶
Source

inst_stxrb :: inst_stxrb_r_r_m

inst_stxrb_r_r_m ¶
Source

inst_stxrb_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_stxrh ¶
Source

inst_stxrh :: inst_stxrh_r_r_m

inst_stxrh_r_r_m ¶
Source

inst_stxrh_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_stz2g ¶
Source

inst_stz2g :: inst_stz2g_r_m

inst_stz2g_r_m ¶
Source

inst_stz2g_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stzg ¶
Source

inst_stzg :: inst_stzg_r_m

inst_stzg_r_m ¶
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inst_stzg_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_stzgm ¶
Source

inst_stzgm :: inst_stzgm_r_m

inst_stzgm_r_m ¶
Source

inst_stzgm_r_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

inst_sub_er ¶
Source

inst_sub_er :: inst_sub_er_r_r_ex

inst_sub_er_r_r_ex ¶
Source

inst_sub_er_r_r_ex :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction {…}

inst_sub_imm ¶
Source

inst_sub_imm :: inst_sub_imm_r_r_i

inst_sub_imm_r_r_i ¶
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inst_sub_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_sub_sr ¶
Source

inst_sub_sr :: inst_sub_sr_r_r_sh

inst_sub_sr_r_r_sh ¶
Source

inst_sub_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_sub_v ¶
Source

inst_sub_v :: inst_sub_v_r_r_r

inst_sub_v_r_r_r ¶
Source

inst_sub_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_subg ¶
Source

inst_subg :: inst_subg_r_r_i_i

inst_subg_r_r_i_i ¶
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inst_subg_r_r_i_i :: proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction {…}

inst_subhn ¶
Source

inst_subhn :: inst_subhn_r_r_r

inst_subhn2 ¶
Source

inst_subhn2 :: inst_subhn2_r_r_r

inst_subhn2_r_r_r ¶
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inst_subhn2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_subhn_r_r_r ¶
Source

inst_subhn_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_subp ¶
Source

inst_subp :: inst_subp_r_r_r

inst_subp_r_r_r ¶
Source

inst_subp_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_subps ¶
Source

inst_subps :: inst_subps_r_r_r

inst_subps_r_r_r ¶
Source

inst_subps_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_subs_er ¶
Source

inst_subs_er :: inst_subs_er_r_r_ex

inst_subs_er_r_r_ex ¶
Source

inst_subs_er_r_r_ex :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction {…}

inst_subs_imm ¶
Source

inst_subs_imm :: inst_subs_imm_r_r_i

inst_subs_imm_r_r_i ¶
Source

inst_subs_imm_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_subs_sr ¶
Source

inst_subs_sr :: inst_subs_sr_r_r_sh

inst_subs_sr_r_r_sh ¶
Source

inst_subs_sr_r_r_sh :: proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction {…}

inst_svc ¶
Source

inst_svc :: inst_svc_i

inst_svc_i ¶
Source

inst_svc_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_sve_abs_pred ¶
Source

inst_sve_abs_pred :: inst_sve_abs_pred_z_p_z

inst_sve_abs_pred_z_p_z ¶
Source

inst_sve_abs_pred_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_adclb ¶
Source

inst_sve_adclb :: inst_sve_adclb_z_z_z

inst_sve_adclb_z_z_z ¶
Source

inst_sve_adclb_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_adclt ¶
Source

inst_sve_adclt :: inst_sve_adclt_z_z_z

inst_sve_adclt_z_z_z ¶
Source

inst_sve_adclt_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_add_pred ¶
Source

inst_sve_add_pred :: inst_sve_add_pred_z_p_z_z

inst_sve_add_pred_z_p_z_z ¶
Source

inst_sve_add_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_add_z ¶
Source

inst_sve_add_z :: inst_sve_add_z_z_z_z

inst_sve_add_z_z_z_z ¶
Source

inst_sve_add_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_aesd ¶
Source

inst_sve_aesd :: inst_sve_aesd_z_z

inst_sve_aesd_z_z ¶
Source

inst_sve_aesd_z_z :: proc "contextless" (rz: u8, rz2: u8) -> Instruction {…}

inst_sve_aese ¶
Source

inst_sve_aese :: inst_sve_aese_z_z

inst_sve_aese_z_z ¶
Source

inst_sve_aese_z_z :: proc "contextless" (rz: u8, rz2: u8) -> Instruction {…}

inst_sve_aesimc ¶
Source

inst_sve_aesimc :: inst_sve_aesimc_z

inst_sve_aesimc_z ¶
Source

inst_sve_aesimc_z :: proc "contextless" (rz: u8) -> Instruction {…}

inst_sve_aesmc ¶
Source

inst_sve_aesmc :: inst_sve_aesmc_z

inst_sve_aesmc_z ¶
Source

inst_sve_aesmc_z :: proc "contextless" (rz: u8) -> Instruction {…}

inst_sve_and_p ¶
Source

inst_sve_and_p :: inst_sve_and_p_p_p_p_p

inst_sve_and_p_p_p_p_p ¶
Source

inst_sve_and_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_and_pred ¶
Source

inst_sve_and_pred :: inst_sve_and_pred_z_p_z_z

inst_sve_and_pred_z_p_z_z ¶
Source

inst_sve_and_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_ands_p ¶
Source

inst_sve_ands_p :: inst_sve_ands_p_p_p_p_p

inst_sve_ands_p_p_p_p_p ¶
Source

inst_sve_ands_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_asr_pred ¶
Source

inst_sve_asr_pred :: inst_sve_asr_pred_z_p_z_z

inst_sve_asr_pred_z_p_z_z ¶
Source

inst_sve_asr_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_asrr_pred ¶
Source

inst_sve_asrr_pred :: inst_sve_asrr_pred_z_p_z_z

inst_sve_asrr_pred_z_p_z_z ¶
Source

inst_sve_asrr_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bcax_z ¶
Source

inst_sve_bcax_z :: inst_sve_bcax_z_z_z_z_z

inst_sve_bcax_z_z_z_z_z ¶
Source

inst_sve_bcax_z_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bfadd ¶
Source

inst_sve_bfadd :: inst_sve_bfadd_z_p_z_z

inst_sve_bfadd_unpred ¶
Source

inst_sve_bfadd_unpred :: inst_sve_bfadd_unpred_z_z_z

inst_sve_bfadd_unpred_z_z_z ¶
Source

inst_sve_bfadd_unpred_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_bfadd_z_p_z_z ¶
Source

inst_sve_bfadd_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bfclamp ¶
Source

inst_sve_bfclamp :: inst_sve_bfclamp_z_z_z

inst_sve_bfclamp_z_z_z ¶
Source

inst_sve_bfclamp_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_bfcvt ¶
Source

inst_sve_bfcvt :: inst_sve_bfcvt_z_p_z

inst_sve_bfcvt_z_p_z ¶
Source

inst_sve_bfcvt_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_bfcvtnt ¶
Source

inst_sve_bfcvtnt :: inst_sve_bfcvtnt_z_p_z

inst_sve_bfcvtnt_z_p_z ¶
Source

inst_sve_bfcvtnt_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_bfmaxnm ¶
Source

inst_sve_bfmaxnm :: inst_sve_bfmaxnm_z_p_z_z

inst_sve_bfmaxnm_z_p_z_z ¶
Source

inst_sve_bfmaxnm_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bfminnm ¶
Source

inst_sve_bfminnm :: inst_sve_bfminnm_z_p_z_z

inst_sve_bfminnm_z_p_z_z ¶
Source

inst_sve_bfminnm_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bfmla ¶
Source

inst_sve_bfmla :: inst_sve_bfmla_z_p_z_z

inst_sve_bfmla_z_p_z_z ¶
Source

inst_sve_bfmla_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bfmls ¶
Source

inst_sve_bfmls :: inst_sve_bfmls_z_p_z_z

inst_sve_bfmls_z_p_z_z ¶
Source

inst_sve_bfmls_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bfmul ¶
Source

inst_sve_bfmul :: inst_sve_bfmul_z_p_z_z

inst_sve_bfmul_unpred ¶
Source

inst_sve_bfmul_unpred :: inst_sve_bfmul_unpred_z_z_z

inst_sve_bfmul_unpred_z_z_z ¶
Source

inst_sve_bfmul_unpred_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_bfmul_z_p_z_z ¶
Source

inst_sve_bfmul_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bfsub ¶
Source

inst_sve_bfsub :: inst_sve_bfsub_z_p_z_z

inst_sve_bfsub_unpred ¶
Source

inst_sve_bfsub_unpred :: inst_sve_bfsub_unpred_z_z_z

inst_sve_bfsub_unpred_z_z_z ¶
Source

inst_sve_bfsub_unpred_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_bfsub_z_p_z_z ¶
Source

inst_sve_bfsub_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bic_p ¶
Source

inst_sve_bic_p :: inst_sve_bic_p_p_p_p_p

inst_sve_bic_p_p_p_p_p ¶
Source

inst_sve_bic_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bic_pred ¶
Source

inst_sve_bic_pred :: inst_sve_bic_pred_z_p_z_z

inst_sve_bic_pred_z_p_z_z ¶
Source

inst_sve_bic_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bics_p ¶
Source

inst_sve_bics_p :: inst_sve_bics_p_p_p_p_p

inst_sve_bics_p_p_p_p_p ¶
Source

inst_sve_bics_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_brka ¶
Source

inst_sve_brka :: inst_sve_brka_p_p_p

inst_sve_brka_p_p_p ¶
Source

inst_sve_brka_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_brkas ¶
Source

inst_sve_brkas :: inst_sve_brkas_p_p_p

inst_sve_brkas_p_p_p ¶
Source

inst_sve_brkas_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_brkb ¶
Source

inst_sve_brkb :: inst_sve_brkb_p_p_p

inst_sve_brkb_p_p_p ¶
Source

inst_sve_brkb_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_brkbs ¶
Source

inst_sve_brkbs :: inst_sve_brkbs_p_p_p

inst_sve_brkbs_p_p_p ¶
Source

inst_sve_brkbs_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_brkn ¶
Source

inst_sve_brkn :: inst_sve_brkn_p_p_p_p

inst_sve_brkn_p_p_p_p ¶
Source

inst_sve_brkn_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_brkpa ¶
Source

inst_sve_brkpa :: inst_sve_brkpa_p_p_p_p

inst_sve_brkpa_p_p_p_p ¶
Source

inst_sve_brkpa_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_brkpb ¶
Source

inst_sve_brkpb :: inst_sve_brkpb_p_p_p_p

inst_sve_brkpb_p_p_p_p ¶
Source

inst_sve_brkpb_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bsl ¶
Source

inst_sve_bsl :: inst_sve_bsl_z_z_z_z

inst_sve_bsl1n ¶
Source

inst_sve_bsl1n :: inst_sve_bsl1n_z_z_z_z

inst_sve_bsl1n_z_z_z_z ¶
Source

inst_sve_bsl1n_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bsl2n ¶
Source

inst_sve_bsl2n :: inst_sve_bsl2n_z_z_z_z

inst_sve_bsl2n_z_z_z_z ¶
Source

inst_sve_bsl2n_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_bsl_z_z_z_z ¶
Source

inst_sve_bsl_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_cls_pred ¶
Source

inst_sve_cls_pred :: inst_sve_cls_pred_z_p_z

inst_sve_cls_pred_z_p_z ¶
Source

inst_sve_cls_pred_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_clz_pred ¶
Source

inst_sve_clz_pred :: inst_sve_clz_pred_z_p_z

inst_sve_clz_pred_z_p_z ¶
Source

inst_sve_clz_pred_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_cmpeq ¶
Source

inst_sve_cmpeq :: inst_sve_cmpeq_p_p_z_z

inst_sve_cmpeq_p_p_z_z ¶
Source

inst_sve_cmpeq_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_cmpge ¶
Source

inst_sve_cmpge :: inst_sve_cmpge_p_p_z_z

inst_sve_cmpge_p_p_z_z ¶
Source

inst_sve_cmpge_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_cmpgt ¶
Source

inst_sve_cmpgt :: inst_sve_cmpgt_p_p_z_z

inst_sve_cmpgt_p_p_z_z ¶
Source

inst_sve_cmpgt_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_cmphi ¶
Source

inst_sve_cmphi :: inst_sve_cmphi_p_p_z_z

inst_sve_cmphi_p_p_z_z ¶
Source

inst_sve_cmphi_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_cmphs ¶
Source

inst_sve_cmphs :: inst_sve_cmphs_p_p_z_z

inst_sve_cmphs_p_p_z_z ¶
Source

inst_sve_cmphs_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_cmple ¶
Source

inst_sve_cmple :: inst_sve_cmple_p_p_z_z

inst_sve_cmple_p_p_z_z ¶
Source

inst_sve_cmple_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_cmplo ¶
Source

inst_sve_cmplo :: inst_sve_cmplo_p_p_z_z

inst_sve_cmplo_p_p_z_z ¶
Source

inst_sve_cmplo_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_cmpls ¶
Source

inst_sve_cmpls :: inst_sve_cmpls_p_p_z_z

inst_sve_cmpls_p_p_z_z ¶
Source

inst_sve_cmpls_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_cmplt ¶
Source

inst_sve_cmplt :: inst_sve_cmplt_p_p_z_z

inst_sve_cmplt_p_p_z_z ¶
Source

inst_sve_cmplt_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_cmpne ¶
Source

inst_sve_cmpne :: inst_sve_cmpne_p_p_z_z

inst_sve_cmpne_p_p_z_z ¶
Source

inst_sve_cmpne_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_cnt_pred ¶
Source

inst_sve_cnt_pred :: inst_sve_cnt_pred_z_p_z

inst_sve_cnt_pred_z_p_z ¶
Source

inst_sve_cnt_pred_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_compact ¶
Source

inst_sve_compact :: inst_sve_compact_z_p_z

inst_sve_compact_z_p_z ¶
Source

inst_sve_compact_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_cpy_z ¶
Source

inst_sve_cpy_z :: inst_sve_cpy_z_z_p_r

inst_sve_cpy_z_z_p_r ¶
Source

inst_sve_cpy_z_z_p_r :: proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction {…}

inst_sve_dup_z ¶
Source

inst_sve_dup_z :: inst_sve_dup_z_z_r

inst_sve_dup_z_z_r ¶
Source

inst_sve_dup_z_z_r :: proc "contextless" (rz: u8, src: Register) -> Instruction {…}

inst_sve_eor3_z ¶
Source

inst_sve_eor3_z :: inst_sve_eor3_z_z_z_z_z

inst_sve_eor3_z_z_z_z_z ¶
Source

inst_sve_eor3_z_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_eor_p ¶
Source

inst_sve_eor_p :: inst_sve_eor_p_p_p_p_p

inst_sve_eor_p_p_p_p_p ¶
Source

inst_sve_eor_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_eor_pred ¶
Source

inst_sve_eor_pred :: inst_sve_eor_pred_z_p_z_z

inst_sve_eor_pred_z_p_z_z ¶
Source

inst_sve_eor_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_eors_p ¶
Source

inst_sve_eors_p :: inst_sve_eors_p_p_p_p_p

inst_sve_eors_p_p_p_p_p ¶
Source

inst_sve_eors_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_ext ¶
Source

inst_sve_ext :: inst_sve_ext_z_z_z_i

inst_sve_ext_z ¶
Source

inst_sve_ext_z :: inst_sve_ext_z_z_z_z_i

inst_sve_ext_z_z_z_i ¶
Source

inst_sve_ext_z_z_z_i :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction {…}

inst_sve_ext_z_z_z_z_i ¶
Source

inst_sve_ext_z_z_z_z_i :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction {…}

inst_sve_fabs_z ¶
Source

inst_sve_fabs_z :: inst_sve_fabs_z_z_p_z

inst_sve_fabs_z_z_p_z ¶
Source

inst_sve_fabs_z_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_fadd_pred ¶
Source

inst_sve_fadd_pred :: inst_sve_fadd_pred_z_p_z_z

inst_sve_fadd_pred_z_p_z_z ¶
Source

inst_sve_fadd_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fadd_z ¶
Source

inst_sve_fadd_z :: inst_sve_fadd_z_z_z_z

inst_sve_fadd_z_z_z_z ¶
Source

inst_sve_fadd_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_fcmeq ¶
Source

inst_sve_fcmeq :: inst_sve_fcmeq_p_p_z_z

inst_sve_fcmeq_p_p_z_z ¶
Source

inst_sve_fcmeq_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fcmge ¶
Source

inst_sve_fcmge :: inst_sve_fcmge_p_p_z_z

inst_sve_fcmge_p_p_z_z ¶
Source

inst_sve_fcmge_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fcmgt ¶
Source

inst_sve_fcmgt :: inst_sve_fcmgt_p_p_z_z

inst_sve_fcmgt_p_p_z_z ¶
Source

inst_sve_fcmgt_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fcmle ¶
Source

inst_sve_fcmle :: inst_sve_fcmle_p_p_z

inst_sve_fcmle_p_p_z ¶
Source

inst_sve_fcmle_p_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_fcmlt ¶
Source

inst_sve_fcmlt :: inst_sve_fcmlt_p_p_z

inst_sve_fcmlt_p_p_z ¶
Source

inst_sve_fcmlt_p_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_fcmne ¶
Source

inst_sve_fcmne :: inst_sve_fcmne_p_p_z_z

inst_sve_fcmne_p_p_z_z ¶
Source

inst_sve_fcmne_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fcmuo ¶
Source

inst_sve_fcmuo :: inst_sve_fcmuo_p_p_z_z

inst_sve_fcmuo_p_p_z_z ¶
Source

inst_sve_fcmuo_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fdiv_pred ¶
Source

inst_sve_fdiv_pred :: inst_sve_fdiv_pred_z_p_z_z

inst_sve_fdiv_pred_z_p_z_z ¶
Source

inst_sve_fdiv_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fdivr_pred ¶
Source

inst_sve_fdivr_pred :: inst_sve_fdivr_pred_z_p_z_z

inst_sve_fdivr_pred_z_p_z_z ¶
Source

inst_sve_fdivr_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fmax_pred ¶
Source

inst_sve_fmax_pred :: inst_sve_fmax_pred_z_p_z_z

inst_sve_fmax_pred_z_p_z_z ¶
Source

inst_sve_fmax_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fmaxnm_pred ¶
Source

inst_sve_fmaxnm_pred :: inst_sve_fmaxnm_pred_z_p_z_z

inst_sve_fmaxnm_pred_z_p_z_z ¶
Source

inst_sve_fmaxnm_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fmin_pred ¶
Source

inst_sve_fmin_pred :: inst_sve_fmin_pred_z_p_z_z

inst_sve_fmin_pred_z_p_z_z ¶
Source

inst_sve_fmin_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fminnm_pred ¶
Source

inst_sve_fminnm_pred :: inst_sve_fminnm_pred_z_p_z_z

inst_sve_fminnm_pred_z_p_z_z ¶
Source

inst_sve_fminnm_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fmla ¶
Source

inst_sve_fmla :: inst_sve_fmla_z_p_z_z

inst_sve_fmla_idx_d ¶
Source

inst_sve_fmla_idx_d :: inst_sve_fmla_idx_d_z_z_z_i

inst_sve_fmla_idx_d_z_z_z_i ¶
Source

inst_sve_fmla_idx_d_z_z_z_i :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction {…}

inst_sve_fmla_idx_h ¶
Source

inst_sve_fmla_idx_h :: inst_sve_fmla_idx_h_z_z_z_i

inst_sve_fmla_idx_h_z_z_z_i ¶
Source

inst_sve_fmla_idx_h_z_z_z_i :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction {…}

inst_sve_fmla_idx_s ¶
Source

inst_sve_fmla_idx_s :: inst_sve_fmla_idx_s_z_z_z_i

inst_sve_fmla_idx_s_z_z_z_i ¶
Source

inst_sve_fmla_idx_s_z_z_z_i :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction {…}

inst_sve_fmla_z_p_z_z ¶
Source

inst_sve_fmla_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fmls ¶
Source

inst_sve_fmls :: inst_sve_fmls_z_p_z_z

inst_sve_fmls_idx_d ¶
Source

inst_sve_fmls_idx_d :: inst_sve_fmls_idx_d_z_z_z_i

inst_sve_fmls_idx_d_z_z_z_i ¶
Source

inst_sve_fmls_idx_d_z_z_z_i :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction {…}

inst_sve_fmls_idx_h ¶
Source

inst_sve_fmls_idx_h :: inst_sve_fmls_idx_h_z_z_z_i

inst_sve_fmls_idx_h_z_z_z_i ¶
Source

inst_sve_fmls_idx_h_z_z_z_i :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction {…}

inst_sve_fmls_idx_s ¶
Source

inst_sve_fmls_idx_s :: inst_sve_fmls_idx_s_z_z_z_i

inst_sve_fmls_idx_s_z_z_z_i ¶
Source

inst_sve_fmls_idx_s_z_z_z_i :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction {…}

inst_sve_fmls_z_p_z_z ¶
Source

inst_sve_fmls_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fmul_pred ¶
Source

inst_sve_fmul_pred :: inst_sve_fmul_pred_z_p_z_z

inst_sve_fmul_pred_z_p_z_z ¶
Source

inst_sve_fmul_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fmul_z ¶
Source

inst_sve_fmul_z :: inst_sve_fmul_z_z_z_z

inst_sve_fmul_z_z_z_z ¶
Source

inst_sve_fmul_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_fneg_z ¶
Source

inst_sve_fneg_z :: inst_sve_fneg_z_z_p_z

inst_sve_fneg_z_z_p_z ¶
Source

inst_sve_fneg_z_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_fnmla ¶
Source

inst_sve_fnmla :: inst_sve_fnmla_z_p_z_z

inst_sve_fnmla_z_p_z_z ¶
Source

inst_sve_fnmla_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fnmls ¶
Source

inst_sve_fnmls :: inst_sve_fnmls_z_p_z_z

inst_sve_fnmls_z_p_z_z ¶
Source

inst_sve_fnmls_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_frecps ¶
Source

inst_sve_frecps :: inst_sve_frecps_z_z_z

inst_sve_frecps_z_z_z ¶
Source

inst_sve_frecps_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_frecpx_z ¶
Source

inst_sve_frecpx_z :: inst_sve_frecpx_z_z_p_z

inst_sve_frecpx_z_z_p_z ¶
Source

inst_sve_frecpx_z_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_frinta ¶
Source

inst_sve_frinta :: inst_sve_frinta_z_p_z

inst_sve_frinta_z_p_z ¶
Source

inst_sve_frinta_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_frinti ¶
Source

inst_sve_frinti :: inst_sve_frinti_z_p_z

inst_sve_frinti_z_p_z ¶
Source

inst_sve_frinti_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_frintm ¶
Source

inst_sve_frintm :: inst_sve_frintm_z_p_z

inst_sve_frintm_z_p_z ¶
Source

inst_sve_frintm_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_frintn ¶
Source

inst_sve_frintn :: inst_sve_frintn_z_p_z

inst_sve_frintn_z_p_z ¶
Source

inst_sve_frintn_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_frintp ¶
Source

inst_sve_frintp :: inst_sve_frintp_z_p_z

inst_sve_frintp_z_p_z ¶
Source

inst_sve_frintp_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_frintx ¶
Source

inst_sve_frintx :: inst_sve_frintx_z_p_z

inst_sve_frintx_z_p_z ¶
Source

inst_sve_frintx_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_frintz ¶
Source

inst_sve_frintz :: inst_sve_frintz_z_p_z

inst_sve_frintz_z_p_z ¶
Source

inst_sve_frintz_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_frsqrts ¶
Source

inst_sve_frsqrts :: inst_sve_frsqrts_z_z_z

inst_sve_frsqrts_z_z_z ¶
Source

inst_sve_frsqrts_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_fsqrt_z ¶
Source

inst_sve_fsqrt_z :: inst_sve_fsqrt_z_z_p_z

inst_sve_fsqrt_z_z_p_z ¶
Source

inst_sve_fsqrt_z_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_fsub_pred ¶
Source

inst_sve_fsub_pred :: inst_sve_fsub_pred_z_p_z_z

inst_sve_fsub_pred_z_p_z_z ¶
Source

inst_sve_fsub_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_fsub_z ¶
Source

inst_sve_fsub_z :: inst_sve_fsub_z_z_z_z

inst_sve_fsub_z_z_z_z ¶
Source

inst_sve_fsub_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_fsubr_pred ¶
Source

inst_sve_fsubr_pred :: inst_sve_fsubr_pred_z_p_z_z

inst_sve_fsubr_pred_z_p_z_z ¶
Source

inst_sve_fsubr_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_ftsmul ¶
Source

inst_sve_ftsmul :: inst_sve_ftsmul_z_z_z

inst_sve_ftsmul_z_z_z ¶
Source

inst_sve_ftsmul_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_histcnt ¶
Source

inst_sve_histcnt :: inst_sve_histcnt_z_p_z_z

inst_sve_histcnt_z_p_z_z ¶
Source

inst_sve_histcnt_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_histseg ¶
Source

inst_sve_histseg :: inst_sve_histseg_z_z_z

inst_sve_histseg_z_z_z ¶
Source

inst_sve_histseg_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_index_ii ¶
Source

inst_sve_index_ii :: inst_sve_index_ii_z_i_i

inst_sve_index_ii_z_i_i ¶
Source

inst_sve_index_ii_z_i_i :: proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction {…}

inst_sve_index_ir ¶
Source

inst_sve_index_ir :: inst_sve_index_ir_z_i_r

inst_sve_index_ir_z_i_r ¶
Source

inst_sve_index_ir_z_i_r :: proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction {…}

inst_sve_index_ri ¶
Source

inst_sve_index_ri :: inst_sve_index_ri_z_r_i

inst_sve_index_ri_z_r_i ¶
Source

inst_sve_index_ri_z_r_i :: proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction {…}

inst_sve_index_rr ¶
Source

inst_sve_index_rr :: inst_sve_index_rr_z_r_r

inst_sve_index_rr_z_r_r ¶
Source

inst_sve_index_rr_z_r_r :: proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction {…}

inst_sve_insr ¶
Source

inst_sve_insr :: inst_sve_insr_z_r

inst_sve_insr_z_r ¶
Source

inst_sve_insr_z_r :: proc "contextless" (rz: u8, src: Register) -> Instruction {…}

inst_sve_ld1b ¶
Source

inst_sve_ld1b :: inst_sve_ld1b_z_p_m

inst_sve_ld1b_gather_d ¶
Source

inst_sve_ld1b_gather_d :: inst_sve_ld1b_gather_d_z_p_m

inst_sve_ld1b_gather_d_z_p_m ¶
Source

inst_sve_ld1b_gather_d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1b_gather_s ¶
Source

inst_sve_ld1b_gather_s :: inst_sve_ld1b_gather_s_z_p_m

inst_sve_ld1b_gather_s_z_p_m ¶
Source

inst_sve_ld1b_gather_s_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1b_z_p_m ¶
Source

inst_sve_ld1b_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1d ¶
Source

inst_sve_ld1d :: inst_sve_ld1d_z_p_m

inst_sve_ld1d_gather_d ¶
Source

inst_sve_ld1d_gather_d :: inst_sve_ld1d_gather_d_z_p_m

inst_sve_ld1d_gather_d_z_p_m ¶
Source

inst_sve_ld1d_gather_d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1d_z_p_m ¶
Source

inst_sve_ld1d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1h ¶
Source

inst_sve_ld1h :: inst_sve_ld1h_z_p_m

inst_sve_ld1h_gather_d ¶
Source

inst_sve_ld1h_gather_d :: inst_sve_ld1h_gather_d_z_p_m

inst_sve_ld1h_gather_d_z_p_m ¶
Source

inst_sve_ld1h_gather_d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1h_gather_s ¶
Source

inst_sve_ld1h_gather_s :: inst_sve_ld1h_gather_s_z_p_m

inst_sve_ld1h_gather_s_z_p_m ¶
Source

inst_sve_ld1h_gather_s_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1h_z_p_m ¶
Source

inst_sve_ld1h_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1sb ¶
Source

inst_sve_ld1sb :: inst_sve_ld1sb_z_p_m

inst_sve_ld1sb_gather_d ¶
Source

inst_sve_ld1sb_gather_d :: inst_sve_ld1sb_gather_d_z_p_m

inst_sve_ld1sb_gather_d_z_p_m ¶
Source

inst_sve_ld1sb_gather_d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1sb_gather_s ¶
Source

inst_sve_ld1sb_gather_s :: inst_sve_ld1sb_gather_s_z_p_m

inst_sve_ld1sb_gather_s_z_p_m ¶
Source

inst_sve_ld1sb_gather_s_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1sb_z_p_m ¶
Source

inst_sve_ld1sb_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1sh ¶
Source

inst_sve_ld1sh :: inst_sve_ld1sh_z_p_m

inst_sve_ld1sh_gather_d ¶
Source

inst_sve_ld1sh_gather_d :: inst_sve_ld1sh_gather_d_z_p_m

inst_sve_ld1sh_gather_d_z_p_m ¶
Source

inst_sve_ld1sh_gather_d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1sh_gather_s ¶
Source

inst_sve_ld1sh_gather_s :: inst_sve_ld1sh_gather_s_z_p_m

inst_sve_ld1sh_gather_s_z_p_m ¶
Source

inst_sve_ld1sh_gather_s_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1sh_z_p_m ¶
Source

inst_sve_ld1sh_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1sw ¶
Source

inst_sve_ld1sw :: inst_sve_ld1sw_z_p_m

inst_sve_ld1sw_gather_d ¶
Source

inst_sve_ld1sw_gather_d :: inst_sve_ld1sw_gather_d_z_p_m

inst_sve_ld1sw_gather_d_z_p_m ¶
Source

inst_sve_ld1sw_gather_d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1sw_z_p_m ¶
Source

inst_sve_ld1sw_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1w ¶
Source

inst_sve_ld1w :: inst_sve_ld1w_z_p_m

inst_sve_ld1w_gather_d ¶
Source

inst_sve_ld1w_gather_d :: inst_sve_ld1w_gather_d_z_p_m

inst_sve_ld1w_gather_d_z_p_m ¶
Source

inst_sve_ld1w_gather_d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1w_gather_s ¶
Source

inst_sve_ld1w_gather_s :: inst_sve_ld1w_gather_s_z_p_m

inst_sve_ld1w_gather_s_z_p_m ¶
Source

inst_sve_ld1w_gather_s_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ld1w_z_p_m ¶
Source

inst_sve_ld1w_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ldff1b ¶
Source

inst_sve_ldff1b :: inst_sve_ldff1b_z_p_m

inst_sve_ldff1b_z_p_m ¶
Source

inst_sve_ldff1b_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ldff1d ¶
Source

inst_sve_ldff1d :: inst_sve_ldff1d_z_p_m

inst_sve_ldff1d_z_p_m ¶
Source

inst_sve_ldff1d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ldff1h ¶
Source

inst_sve_ldff1h :: inst_sve_ldff1h_z_p_m

inst_sve_ldff1h_z_p_m ¶
Source

inst_sve_ldff1h_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ldff1w ¶
Source

inst_sve_ldff1w :: inst_sve_ldff1w_z_p_m

inst_sve_ldff1w_z_p_m ¶
Source

inst_sve_ldff1w_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ldnt1b ¶
Source

inst_sve_ldnt1b :: inst_sve_ldnt1b_z_p_m

inst_sve_ldnt1b_z_p_m ¶
Source

inst_sve_ldnt1b_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ldnt1d ¶
Source

inst_sve_ldnt1d :: inst_sve_ldnt1d_z_p_m

inst_sve_ldnt1d_z_p_m ¶
Source

inst_sve_ldnt1d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ldnt1h ¶
Source

inst_sve_ldnt1h :: inst_sve_ldnt1h_z_p_m

inst_sve_ldnt1h_z_p_m ¶
Source

inst_sve_ldnt1h_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ldnt1w ¶
Source

inst_sve_ldnt1w :: inst_sve_ldnt1w_z_p_m

inst_sve_ldnt1w_z_p_m ¶
Source

inst_sve_ldnt1w_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_ldr_p ¶
Source

inst_sve_ldr_p :: inst_sve_ldr_p_p_m

inst_sve_ldr_p_p_m ¶
Source

inst_sve_ldr_p_p_m :: proc "contextless" (rz: u8, mem: Memory) -> Instruction {…}

inst_sve_ldr_z ¶
Source

inst_sve_ldr_z :: inst_sve_ldr_z_z_m

inst_sve_ldr_z_z_m ¶
Source

inst_sve_ldr_z_z_m :: proc "contextless" (rz: u8, mem: Memory) -> Instruction {…}

inst_sve_lsl_pred ¶
Source

inst_sve_lsl_pred :: inst_sve_lsl_pred_z_p_z_z

inst_sve_lsl_pred_z_p_z_z ¶
Source

inst_sve_lsl_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_lslr_pred ¶
Source

inst_sve_lslr_pred :: inst_sve_lslr_pred_z_p_z_z

inst_sve_lslr_pred_z_p_z_z ¶
Source

inst_sve_lslr_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_lsr_pred ¶
Source

inst_sve_lsr_pred :: inst_sve_lsr_pred_z_p_z_z

inst_sve_lsr_pred_z_p_z_z ¶
Source

inst_sve_lsr_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_lsrr_pred ¶
Source

inst_sve_lsrr_pred :: inst_sve_lsrr_pred_z_p_z_z

inst_sve_lsrr_pred_z_p_z_z ¶
Source

inst_sve_lsrr_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_match ¶
Source

inst_sve_match :: inst_sve_match_p_p_z_z

inst_sve_match_p_p_z_z ¶
Source

inst_sve_match_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_mov_p_p_p ¶
Source

inst_sve_mov_p_p_p :: proc "contextless" (rz: u8, rz2: u8) -> Instruction {…}

Related Procedure Groups

inst_sve_mov_p

inst_sve_mov_p_p_p_p ¶
Source

inst_sve_mov_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

Related Procedure Groups

inst_sve_mov_p

inst_sve_mov_pred ¶
Source

inst_sve_mov_pred :: inst_sve_mov_pred_z_p_z

inst_sve_mov_pred_z_p_z ¶
Source

inst_sve_mov_pred_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_movs_p ¶
Source

inst_sve_movs_p :: inst_sve_movs_p_p_p_p

inst_sve_movs_p_p_p_p ¶
Source

inst_sve_movs_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_mul_pred ¶
Source

inst_sve_mul_pred :: inst_sve_mul_pred_z_p_z_z

inst_sve_mul_pred_z_p_z_z ¶
Source

inst_sve_mul_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_nand_p ¶
Source

inst_sve_nand_p :: inst_sve_nand_p_p_p_p_p

inst_sve_nand_p_p_p_p_p ¶
Source

inst_sve_nand_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_nands_p ¶
Source

inst_sve_nands_p :: inst_sve_nands_p_p_p_p_p

inst_sve_nands_p_p_p_p_p ¶
Source

inst_sve_nands_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_nbsl ¶
Source

inst_sve_nbsl :: inst_sve_nbsl_z_z_z_z

inst_sve_nbsl_z_z_z_z ¶
Source

inst_sve_nbsl_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_neg_pred ¶
Source

inst_sve_neg_pred :: inst_sve_neg_pred_z_p_z

inst_sve_neg_pred_z_p_z ¶
Source

inst_sve_neg_pred_z_p_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_nmatch ¶
Source

inst_sve_nmatch :: inst_sve_nmatch_p_p_z_z

inst_sve_nmatch_p_p_z_z ¶
Source

inst_sve_nmatch_p_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_nor_p ¶
Source

inst_sve_nor_p :: inst_sve_nor_p_p_p_p_p

inst_sve_nor_p_p_p_p_p ¶
Source

inst_sve_nor_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_nors_p ¶
Source

inst_sve_nors_p :: inst_sve_nors_p_p_p_p_p

inst_sve_nors_p_p_p_p_p ¶
Source

inst_sve_nors_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_not_p ¶
Source

inst_sve_not_p :: inst_sve_not_p_p_p_p

inst_sve_not_p_p_p_p ¶
Source

inst_sve_not_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_orn_p ¶
Source

inst_sve_orn_p :: inst_sve_orn_p_p_p_p_p

inst_sve_orn_p_p_p_p_p ¶
Source

inst_sve_orn_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_orns_p ¶
Source

inst_sve_orns_p :: inst_sve_orns_p_p_p_p_p

inst_sve_orns_p_p_p_p_p ¶
Source

inst_sve_orns_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_orr_p ¶
Source

inst_sve_orr_p :: inst_sve_orr_p_p_p_p_p

inst_sve_orr_p_p_p_p_p ¶
Source

inst_sve_orr_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_orr_pred ¶
Source

inst_sve_orr_pred :: inst_sve_orr_pred_z_p_z_z

inst_sve_orr_pred_z_p_z_z ¶
Source

inst_sve_orr_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_orrs_p ¶
Source

inst_sve_orrs_p :: inst_sve_orrs_p_p_p_p_p

inst_sve_orrs_p_p_p_p_p ¶
Source

inst_sve_orrs_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_pfalse ¶
Source

inst_sve_pfalse :: inst_sve_pfalse_p

inst_sve_pfalse_p ¶
Source

inst_sve_pfalse_p :: proc "contextless" (rz: u8) -> Instruction {…}

inst_sve_pfirst ¶
Source

inst_sve_pfirst :: inst_sve_pfirst_p_p_p

inst_sve_pfirst_p_p_p ¶
Source

inst_sve_pfirst_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_pmul_vec ¶
Source

inst_sve_pmul_vec :: inst_sve_pmul_vec_z_z_z

inst_sve_pmul_vec_z_z_z ¶
Source

inst_sve_pmul_vec_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_pmullb ¶
Source

inst_sve_pmullb :: inst_sve_pmullb_z_z_z

inst_sve_pmullb_z_z_z ¶
Source

inst_sve_pmullb_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_pmullt ¶
Source

inst_sve_pmullt :: inst_sve_pmullt_z_z_z

inst_sve_pmullt_z_z_z ¶
Source

inst_sve_pmullt_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_pnext ¶
Source

inst_sve_pnext :: inst_sve_pnext_p_p_p

inst_sve_pnext_p_p_p ¶
Source

inst_sve_pnext_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_prfb ¶
Source

inst_sve_prfb :: inst_sve_prfb_i_p_m

inst_sve_prfb_i_p_m ¶
Source

inst_sve_prfb_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sve_prfd ¶
Source

inst_sve_prfd :: inst_sve_prfd_i_p_m

inst_sve_prfd_i_p_m ¶
Source

inst_sve_prfd_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sve_prfh ¶
Source

inst_sve_prfh :: inst_sve_prfh_i_p_m

inst_sve_prfh_i_p_m ¶
Source

inst_sve_prfh_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sve_prfw ¶
Source

inst_sve_prfw :: inst_sve_prfw_i_p_m

inst_sve_prfw_i_p_m ¶
Source

inst_sve_prfw_i_p_m :: proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction {…}

inst_sve_ptrue ¶
Source

inst_sve_ptrue :: inst_sve_ptrue_p_i

inst_sve_ptrue_p_i ¶
Source

inst_sve_ptrue_p_i :: proc "contextless" (rz: u8, imm: i64) -> Instruction {…}

inst_sve_ptrues ¶
Source

inst_sve_ptrues :: inst_sve_ptrues_p_i

inst_sve_ptrues_p_i ¶
Source

inst_sve_ptrues_p_i :: proc "contextless" (rz: u8, imm: i64) -> Instruction {…}

inst_sve_rdffr ¶
Source

inst_sve_rdffr :: inst_sve_rdffr_p

inst_sve_rdffr_p ¶
Source

inst_sve_rdffr_p :: proc "contextless" (rz: u8) -> Instruction {…}

inst_sve_rev_p ¶
Source

inst_sve_rev_p :: inst_sve_rev_p_p_p

inst_sve_rev_p_p_p ¶
Source

inst_sve_rev_p_p_p :: proc "contextless" (rz: u8, rz2: u8) -> Instruction {…}

inst_sve_rev_z ¶
Source

inst_sve_rev_z :: inst_sve_rev_z_z_z

inst_sve_rev_z_z_z ¶
Source

inst_sve_rev_z_z_z :: proc "contextless" (rz: u8, rz2: u8) -> Instruction {…}

inst_sve_sabd_pred ¶
Source

inst_sve_sabd_pred :: inst_sve_sabd_pred_z_p_z_z

inst_sve_sabd_pred_z_p_z_z ¶
Source

inst_sve_sabd_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_sbclb ¶
Source

inst_sve_sbclb :: inst_sve_sbclb_z_z_z

inst_sve_sbclb_z_z_z ¶
Source

inst_sve_sbclb_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_sbclt ¶
Source

inst_sve_sbclt :: inst_sve_sbclt_z_z_z

inst_sve_sbclt_z_z_z ¶
Source

inst_sve_sbclt_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_sdiv_pred ¶
Source

inst_sve_sdiv_pred :: inst_sve_sdiv_pred_z_p_z_z

inst_sve_sdiv_pred_z_p_z_z ¶
Source

inst_sve_sdiv_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_sel_p ¶
Source

inst_sve_sel_p :: inst_sve_sel_p_p_p_p_p

inst_sve_sel_p_p_p_p_p ¶
Source

inst_sve_sel_p_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_setffr ¶
Source

inst_sve_setffr :: inst_sve_setffr_none

inst_sve_setffr_none ¶
Source

inst_sve_setffr_none :: proc "contextless" () -> Instruction {…}

inst_sve_smax_pred ¶
Source

inst_sve_smax_pred :: inst_sve_smax_pred_z_p_z_z

inst_sve_smax_pred_z_p_z_z ¶
Source

inst_sve_smax_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_smin_pred ¶
Source

inst_sve_smin_pred :: inst_sve_smin_pred_z_p_z_z

inst_sve_smin_pred_z_p_z_z ¶
Source

inst_sve_smin_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_smulh_pred ¶
Source

inst_sve_smulh_pred :: inst_sve_smulh_pred_z_p_z_z

inst_sve_smulh_pred_z_p_z_z ¶
Source

inst_sve_smulh_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_splice ¶
Source

inst_sve_splice :: inst_sve_splice_z_p_z_z

inst_sve_splice_z_p_z_z ¶
Source

inst_sve_splice_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_sqadd_z ¶
Source

inst_sve_sqadd_z :: inst_sve_sqadd_z_z_z_z

inst_sve_sqadd_z_z_z_z ¶
Source

inst_sve_sqadd_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_sqrdmlah ¶
Source

inst_sve_sqrdmlah :: inst_sve_sqrdmlah_z_z_z

inst_sve_sqrdmlah_z_z_z ¶
Source

inst_sve_sqrdmlah_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_sqrdmlsh ¶
Source

inst_sve_sqrdmlsh :: inst_sve_sqrdmlsh_z_z_z

inst_sve_sqrdmlsh_z_z_z ¶
Source

inst_sve_sqrdmlsh_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_sqsub_z ¶
Source

inst_sve_sqsub_z :: inst_sve_sqsub_z_z_z_z

inst_sve_sqsub_z_z_z_z ¶
Source

inst_sve_sqsub_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_st1b ¶
Source

inst_sve_st1b :: inst_sve_st1b_z_p_m

inst_sve_st1b_scatter_d ¶
Source

inst_sve_st1b_scatter_d :: inst_sve_st1b_scatter_d_z_p_m

inst_sve_st1b_scatter_d_z_p_m ¶
Source

inst_sve_st1b_scatter_d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_st1b_scatter_s ¶
Source

inst_sve_st1b_scatter_s :: inst_sve_st1b_scatter_s_z_p_m

inst_sve_st1b_scatter_s_z_p_m ¶
Source

inst_sve_st1b_scatter_s_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_st1b_z_p_m ¶
Source

inst_sve_st1b_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_st1d ¶
Source

inst_sve_st1d :: inst_sve_st1d_z_p_m

inst_sve_st1d_scatter_d ¶
Source

inst_sve_st1d_scatter_d :: inst_sve_st1d_scatter_d_z_p_m

inst_sve_st1d_scatter_d_z_p_m ¶
Source

inst_sve_st1d_scatter_d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_st1d_z_p_m ¶
Source

inst_sve_st1d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_st1h ¶
Source

inst_sve_st1h :: inst_sve_st1h_z_p_m

inst_sve_st1h_scatter_d ¶
Source

inst_sve_st1h_scatter_d :: inst_sve_st1h_scatter_d_z_p_m

inst_sve_st1h_scatter_d_z_p_m ¶
Source

inst_sve_st1h_scatter_d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_st1h_scatter_s ¶
Source

inst_sve_st1h_scatter_s :: inst_sve_st1h_scatter_s_z_p_m

inst_sve_st1h_scatter_s_z_p_m ¶
Source

inst_sve_st1h_scatter_s_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_st1h_z_p_m ¶
Source

inst_sve_st1h_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_st1w ¶
Source

inst_sve_st1w :: inst_sve_st1w_z_p_m

inst_sve_st1w_scatter_d ¶
Source

inst_sve_st1w_scatter_d :: inst_sve_st1w_scatter_d_z_p_m

inst_sve_st1w_scatter_d_z_p_m ¶
Source

inst_sve_st1w_scatter_d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_st1w_scatter_s ¶
Source

inst_sve_st1w_scatter_s :: inst_sve_st1w_scatter_s_z_p_m

inst_sve_st1w_scatter_s_z_p_m ¶
Source

inst_sve_st1w_scatter_s_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_st1w_z_p_m ¶
Source

inst_sve_st1w_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_stnt1b ¶
Source

inst_sve_stnt1b :: inst_sve_stnt1b_z_p_m

inst_sve_stnt1b_z_p_m ¶
Source

inst_sve_stnt1b_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_stnt1d ¶
Source

inst_sve_stnt1d :: inst_sve_stnt1d_z_p_m

inst_sve_stnt1d_z_p_m ¶
Source

inst_sve_stnt1d_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_stnt1h ¶
Source

inst_sve_stnt1h :: inst_sve_stnt1h_z_p_m

inst_sve_stnt1h_z_p_m ¶
Source

inst_sve_stnt1h_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_stnt1w ¶
Source

inst_sve_stnt1w :: inst_sve_stnt1w_z_p_m

inst_sve_stnt1w_z_p_m ¶
Source

inst_sve_stnt1w_z_p_m :: proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction {…}

inst_sve_str_p ¶
Source

inst_sve_str_p :: inst_sve_str_p_p_m

inst_sve_str_p_p_m ¶
Source

inst_sve_str_p_p_m :: proc "contextless" (rz: u8, mem: Memory) -> Instruction {…}

inst_sve_str_z ¶
Source

inst_sve_str_z :: inst_sve_str_z_z_m

inst_sve_str_z_z_m ¶
Source

inst_sve_str_z_z_m :: proc "contextless" (rz: u8, mem: Memory) -> Instruction {…}

inst_sve_sub_pred ¶
Source

inst_sve_sub_pred :: inst_sve_sub_pred_z_p_z_z

inst_sve_sub_pred_z_p_z_z ¶
Source

inst_sve_sub_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_sub_z ¶
Source

inst_sve_sub_z :: inst_sve_sub_z_z_z_z

inst_sve_sub_z_z_z_z ¶
Source

inst_sve_sub_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_subr_pred ¶
Source

inst_sve_subr_pred :: inst_sve_subr_pred_z_p_z_z

inst_sve_subr_pred_z_p_z_z ¶
Source

inst_sve_subr_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_tbl ¶
Source

inst_sve_tbl :: inst_sve_tbl_z_z_z

inst_sve_tbl2 ¶
Source

inst_sve_tbl2 :: inst_sve_tbl2_z_z_z

inst_sve_tbl2_z_z_z ¶
Source

inst_sve_tbl2_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_tbl_z_z_z ¶
Source

inst_sve_tbl_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_tbx ¶
Source

inst_sve_tbx :: inst_sve_tbx_z_z_z

inst_sve_tbx_z_z_z ¶
Source

inst_sve_tbx_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_trn1_p ¶
Source

inst_sve_trn1_p :: inst_sve_trn1_p_p_p_p

inst_sve_trn1_p_p_p_p ¶
Source

inst_sve_trn1_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_trn1_z ¶
Source

inst_sve_trn1_z :: inst_sve_trn1_z_z_z_z

inst_sve_trn1_z_z_z_z ¶
Source

inst_sve_trn1_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_trn2_p ¶
Source

inst_sve_trn2_p :: inst_sve_trn2_p_p_p_p

inst_sve_trn2_p_p_p_p ¶
Source

inst_sve_trn2_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_trn2_z ¶
Source

inst_sve_trn2_z :: inst_sve_trn2_z_z_z_z

inst_sve_trn2_z_z_z_z ¶
Source

inst_sve_trn2_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_uabd_pred ¶
Source

inst_sve_uabd_pred :: inst_sve_uabd_pred_z_p_z_z

inst_sve_uabd_pred_z_p_z_z ¶
Source

inst_sve_uabd_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_udiv_pred ¶
Source

inst_sve_udiv_pred :: inst_sve_udiv_pred_z_p_z_z

inst_sve_udiv_pred_z_p_z_z ¶
Source

inst_sve_udiv_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_umax_pred ¶
Source

inst_sve_umax_pred :: inst_sve_umax_pred_z_p_z_z

inst_sve_umax_pred_z_p_z_z ¶
Source

inst_sve_umax_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_umin_pred ¶
Source

inst_sve_umin_pred :: inst_sve_umin_pred_z_p_z_z

inst_sve_umin_pred_z_p_z_z ¶
Source

inst_sve_umin_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_umulh_pred ¶
Source

inst_sve_umulh_pred :: inst_sve_umulh_pred_z_p_z_z

inst_sve_umulh_pred_z_p_z_z ¶
Source

inst_sve_umulh_pred_z_p_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction {…}

inst_sve_uqadd_z ¶
Source

inst_sve_uqadd_z :: inst_sve_uqadd_z_z_z_z

inst_sve_uqadd_z_z_z_z ¶
Source

inst_sve_uqadd_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_uqsub_z ¶
Source

inst_sve_uqsub_z :: inst_sve_uqsub_z_z_z_z

inst_sve_uqsub_z_z_z_z ¶
Source

inst_sve_uqsub_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_uzp1_p ¶
Source

inst_sve_uzp1_p :: inst_sve_uzp1_p_p_p_p

inst_sve_uzp1_p_p_p_p ¶
Source

inst_sve_uzp1_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_uzp1_z ¶
Source

inst_sve_uzp1_z :: inst_sve_uzp1_z_z_z_z

inst_sve_uzp1_z_z_z_z ¶
Source

inst_sve_uzp1_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_uzp2_p ¶
Source

inst_sve_uzp2_p :: inst_sve_uzp2_p_p_p_p

inst_sve_uzp2_p_p_p_p ¶
Source

inst_sve_uzp2_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_uzp2_z ¶
Source

inst_sve_uzp2_z :: inst_sve_uzp2_z_z_z_z

inst_sve_uzp2_z_z_z_z ¶
Source

inst_sve_uzp2_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_whilege ¶
Source

inst_sve_whilege :: inst_sve_whilege_p_r_r

inst_sve_whilege_p_r_r ¶
Source

inst_sve_whilege_p_r_r :: proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction {…}

inst_sve_whilegt ¶
Source

inst_sve_whilegt :: inst_sve_whilegt_p_r_r

inst_sve_whilegt_p_r_r ¶
Source

inst_sve_whilegt_p_r_r :: proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction {…}

inst_sve_whilehi ¶
Source

inst_sve_whilehi :: inst_sve_whilehi_p_r_r

inst_sve_whilehi_p_r_r ¶
Source

inst_sve_whilehi_p_r_r :: proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction {…}

inst_sve_whilehs ¶
Source

inst_sve_whilehs :: inst_sve_whilehs_p_r_r

inst_sve_whilehs_p_r_r ¶
Source

inst_sve_whilehs_p_r_r :: proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction {…}

inst_sve_whilele ¶
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inst_sve_whilele :: inst_sve_whilele_p_r_r

inst_sve_whilele_p_r_r ¶
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inst_sve_whilele_p_r_r :: proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction {…}

inst_sve_whilelo ¶
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inst_sve_whilelo :: inst_sve_whilelo_p_r_r

inst_sve_whilelo_p_r_r ¶
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inst_sve_whilelo_p_r_r :: proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction {…}

inst_sve_whilels ¶
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inst_sve_whilels :: inst_sve_whilels_p_r_r

inst_sve_whilels_p_r_r ¶
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inst_sve_whilels_p_r_r :: proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction {…}

inst_sve_whilelt ¶
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inst_sve_whilelt :: inst_sve_whilelt_p_r_r

inst_sve_whilelt_p_r_r ¶
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inst_sve_whilelt_p_r_r :: proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction {…}

inst_sve_wrffr ¶
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inst_sve_wrffr :: inst_sve_wrffr_p

inst_sve_wrffr_p ¶
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inst_sve_wrffr_p :: proc "contextless" (rz: u8) -> Instruction {…}

inst_sve_xar_z ¶
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inst_sve_xar_z :: inst_sve_xar_z_z_z_z_i

inst_sve_xar_z_z_z_z_i ¶
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inst_sve_xar_z_z_z_z_i :: proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction {…}

inst_sve_zip1_p ¶
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inst_sve_zip1_p :: inst_sve_zip1_p_p_p_p

inst_sve_zip1_p_p_p_p ¶
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inst_sve_zip1_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_zip1_z ¶
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inst_sve_zip1_z :: inst_sve_zip1_z_z_z_z

inst_sve_zip1_z_z_z_z ¶
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inst_sve_zip1_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_zip2_p ¶
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inst_sve_zip2_p :: inst_sve_zip2_p_p_p_p

inst_sve_zip2_p_p_p_p ¶
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inst_sve_zip2_p_p_p_p :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_sve_zip2_z ¶
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inst_sve_zip2_z :: inst_sve_zip2_z_z_z_z

inst_sve_zip2_z_z_z_z ¶
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inst_sve_zip2_z_z_z_z :: proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction {…}

inst_swp ¶
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inst_swp :: inst_swp_r_r_m

inst_swp_r_r_m ¶
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inst_swp_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_swpa ¶
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inst_swpa :: inst_swpa_r_r_m

inst_swpa_r_r_m ¶
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inst_swpa_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_swpal ¶
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inst_swpal :: inst_swpal_r_r_m

inst_swpal_r_r_m ¶
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inst_swpal_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_swpl ¶
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inst_swpl :: inst_swpl_r_r_m

inst_swpl_r_r_m ¶
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inst_swpl_r_r_m :: proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction {…}

inst_sxtb ¶
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inst_sxtb :: inst_sxtb_r_r

inst_sxtb_r_r ¶
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inst_sxtb_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sxth ¶
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inst_sxth :: inst_sxth_r_r

inst_sxth_r_r ¶
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inst_sxth_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sxtl ¶
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inst_sxtl :: inst_sxtl_r_r

inst_sxtl2 ¶
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inst_sxtl2 :: inst_sxtl2_r_r

inst_sxtl2_r_r ¶
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inst_sxtl2_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sxtl_r_r ¶
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inst_sxtl_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_sxtw ¶
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inst_sxtw :: inst_sxtw_r_r

inst_sxtw_r_r ¶
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inst_sxtw_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_tbl ¶
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inst_tbl :: inst_tbl_r_r_r

inst_tbl_r_r_r ¶
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inst_tbl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_tbnz ¶
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inst_tbnz :: inst_tbnz_r_i_l

inst_tbnz_r_i_l ¶
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inst_tbnz_r_i_l :: proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction {…}

inst_tbx ¶
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inst_tbx :: inst_tbx_r_r_r

inst_tbx_r_r_r ¶
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inst_tbx_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_tbz ¶
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inst_tbz :: inst_tbz_r_i_l

inst_tbz_r_i_l ¶
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inst_tbz_r_i_l :: proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction {…}

inst_tcancel ¶
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inst_tcancel :: inst_tcancel_i

inst_tcancel_i ¶
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inst_tcancel_i :: proc "contextless" (imm: i64) -> Instruction {…}

inst_tcommit ¶
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inst_tcommit :: inst_tcommit_none

inst_tcommit_none ¶
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inst_tcommit_none :: proc "contextless" () -> Instruction {…}

inst_tlbi_alle1 ¶
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inst_tlbi_alle1 :: inst_tlbi_alle1_none

inst_tlbi_alle1_none ¶
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inst_tlbi_alle1_none :: proc "contextless" () -> Instruction {…}

inst_tlbi_alle1is ¶
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inst_tlbi_alle1is :: inst_tlbi_alle1is_none

inst_tlbi_alle1is_none ¶
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inst_tlbi_alle1is_none :: proc "contextless" () -> Instruction {…}

inst_tlbi_alle2 ¶
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inst_tlbi_alle2 :: inst_tlbi_alle2_none

inst_tlbi_alle2_none ¶
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inst_tlbi_alle2_none :: proc "contextless" () -> Instruction {…}

inst_tlbi_alle2is ¶
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inst_tlbi_alle2is :: inst_tlbi_alle2is_none

inst_tlbi_alle2is_none ¶
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inst_tlbi_alle2is_none :: proc "contextless" () -> Instruction {…}

inst_tlbi_alle3 ¶
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inst_tlbi_alle3 :: inst_tlbi_alle3_none

inst_tlbi_alle3_none ¶
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inst_tlbi_alle3_none :: proc "contextless" () -> Instruction {…}

inst_tlbi_alle3is ¶
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inst_tlbi_alle3is :: inst_tlbi_alle3is_none

inst_tlbi_alle3is_none ¶
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inst_tlbi_alle3is_none :: proc "contextless" () -> Instruction {…}

inst_tlbi_aside1 ¶
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inst_tlbi_aside1 :: inst_tlbi_aside1_r

inst_tlbi_aside1_r ¶
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inst_tlbi_aside1_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_aside1is ¶
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inst_tlbi_aside1is :: inst_tlbi_aside1is_r

inst_tlbi_aside1is_r ¶
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inst_tlbi_aside1is_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_paall ¶
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inst_tlbi_paall :: inst_tlbi_paall_none

inst_tlbi_paall_none ¶
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inst_tlbi_paall_none :: proc "contextless" () -> Instruction {…}

inst_tlbi_paallos ¶
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inst_tlbi_paallos :: inst_tlbi_paallos_none

inst_tlbi_paallos_none ¶
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inst_tlbi_paallos_none :: proc "contextless" () -> Instruction {…}

inst_tlbi_rpalos ¶
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inst_tlbi_rpalos :: inst_tlbi_rpalos_r

inst_tlbi_rpalos_r ¶
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inst_tlbi_rpalos_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_rpaos ¶
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inst_tlbi_rpaos :: inst_tlbi_rpaos_r

inst_tlbi_rpaos_r ¶
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inst_tlbi_rpaos_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_vaae1 ¶
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inst_tlbi_vaae1 :: inst_tlbi_vaae1_r

inst_tlbi_vaae1_r ¶
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inst_tlbi_vaae1_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_vaae1is ¶
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inst_tlbi_vaae1is :: inst_tlbi_vaae1is_r

inst_tlbi_vaae1is_r ¶
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inst_tlbi_vaae1is_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_vaale1 ¶
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inst_tlbi_vaale1 :: inst_tlbi_vaale1_r

inst_tlbi_vaale1_r ¶
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inst_tlbi_vaale1_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_vaale1is ¶
Source

inst_tlbi_vaale1is :: inst_tlbi_vaale1is_r

inst_tlbi_vaale1is_r ¶
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inst_tlbi_vaale1is_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_vae1 ¶
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inst_tlbi_vae1 :: inst_tlbi_vae1_r

inst_tlbi_vae1_r ¶
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inst_tlbi_vae1_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_vae1is ¶
Source

inst_tlbi_vae1is :: inst_tlbi_vae1is_r

inst_tlbi_vae1is_r ¶
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inst_tlbi_vae1is_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_vale1 ¶
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inst_tlbi_vale1 :: inst_tlbi_vale1_r

inst_tlbi_vale1_r ¶
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inst_tlbi_vale1_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_vale1is ¶
Source

inst_tlbi_vale1is :: inst_tlbi_vale1is_r

inst_tlbi_vale1is_r ¶
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inst_tlbi_vale1is_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_tlbi_vmalle1 ¶
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inst_tlbi_vmalle1 :: inst_tlbi_vmalle1_none

inst_tlbi_vmalle1_none ¶
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inst_tlbi_vmalle1_none :: proc "contextless" () -> Instruction {…}

inst_tlbi_vmalle1is ¶
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inst_tlbi_vmalle1is :: inst_tlbi_vmalle1is_none

inst_tlbi_vmalle1is_none ¶
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inst_tlbi_vmalle1is_none :: proc "contextless" () -> Instruction {…}

inst_trn1 ¶
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inst_trn1 :: inst_trn1_r_r_r

inst_trn1_r_r_r ¶
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inst_trn1_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_trn2 ¶
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inst_trn2 :: inst_trn2_r_r_r

inst_trn2_r_r_r ¶
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inst_trn2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_tsb_csync ¶
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inst_tsb_csync :: inst_tsb_csync_none

inst_tsb_csync_none ¶
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inst_tsb_csync_none :: proc "contextless" () -> Instruction {…}

inst_tst_imm ¶
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inst_tst_imm :: inst_tst_imm_r_i

inst_tst_imm_r_i ¶
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inst_tst_imm_r_i :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

inst_tst_sr ¶
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inst_tst_sr :: inst_tst_sr_r_sh

inst_tst_sr_r_sh ¶
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inst_tst_sr_r_sh :: proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction {…}

inst_tstart ¶
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inst_tstart :: inst_tstart_r

inst_tstart_r ¶
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inst_tstart_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_ttest ¶
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inst_ttest :: inst_ttest_r

inst_ttest_r ¶
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inst_ttest_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_uaba ¶
Source

inst_uaba :: inst_uaba_r_r_r

inst_uaba_r_r_r ¶
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inst_uaba_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uabd ¶
Source

inst_uabd :: inst_uabd_r_r_r

inst_uabd_r_r_r ¶
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inst_uabd_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uadalp ¶
Source

inst_uadalp :: inst_uadalp_r_r

inst_uadalp_r_r ¶
Source

inst_uadalp_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_uaddl ¶
Source

inst_uaddl :: inst_uaddl_r_r_r

inst_uaddl2 ¶
Source

inst_uaddl2 :: inst_uaddl2_r_r_r

inst_uaddl2_r_r_r ¶
Source

inst_uaddl2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uaddl_r_r_r ¶
Source

inst_uaddl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uaddlp ¶
Source

inst_uaddlp :: inst_uaddlp_r_r

inst_uaddlp_r_r ¶
Source

inst_uaddlp_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_uaddlv ¶
Source

inst_uaddlv :: inst_uaddlv_r_r

inst_uaddlv_r_r ¶
Source

inst_uaddlv_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_uaddw ¶
Source

inst_uaddw :: inst_uaddw_r_r_r

inst_uaddw2 ¶
Source

inst_uaddw2 :: inst_uaddw2_r_r_r

inst_uaddw2_r_r_r ¶
Source

inst_uaddw2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uaddw_r_r_r ¶
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inst_uaddw_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_ucvtf ¶
Source

inst_ucvtf :: inst_ucvtf_r_r

inst_ucvtf_h ¶
Source

inst_ucvtf_h :: inst_ucvtf_h_r_r

inst_ucvtf_h_r_r ¶
Source

inst_ucvtf_h_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_ucvtf_r_r ¶
Source

inst_ucvtf_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_ucvtf_v ¶
Source

inst_ucvtf_v :: inst_ucvtf_v_r_r

inst_ucvtf_v_r_r ¶
Source

inst_ucvtf_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_udiv ¶
Source

inst_udiv :: inst_udiv_r_r_r

inst_udiv_r_r_r ¶
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inst_udiv_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_udot ¶
Source

inst_udot :: inst_udot_r_r_r

inst_udot_r_r_r ¶
Source

inst_udot_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uhadd ¶
Source

inst_uhadd :: inst_uhadd_r_r_r

inst_uhadd_r_r_r ¶
Source

inst_uhadd_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uhsub ¶
Source

inst_uhsub :: inst_uhsub_r_r_r

inst_uhsub_r_r_r ¶
Source

inst_uhsub_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_umaddl ¶
Source

inst_umaddl :: inst_umaddl_r_r_r_r

inst_umaddl_r_r_r_r ¶
Source

inst_umaddl_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_umax ¶
Source

inst_umax :: inst_umax_r_r_r

inst_umax_r_r_r ¶
Source

inst_umax_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_umaxp ¶
Source

inst_umaxp :: inst_umaxp_r_r_r

inst_umaxp_r_r_r ¶
Source

inst_umaxp_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_umaxv ¶
Source

inst_umaxv :: inst_umaxv_r_r

inst_umaxv_r_r ¶
Source

inst_umaxv_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_umin ¶
Source

inst_umin :: inst_umin_r_r_r

inst_umin_r_r_r ¶
Source

inst_umin_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uminp ¶
Source

inst_uminp :: inst_uminp_r_r_r

inst_uminp_r_r_r ¶
Source

inst_uminp_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uminv ¶
Source

inst_uminv :: inst_uminv_r_r

inst_uminv_r_r ¶
Source

inst_uminv_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_umlal ¶
Source

inst_umlal :: inst_umlal_r_r_r

inst_umlal2 ¶
Source

inst_umlal2 :: inst_umlal2_r_r_r

inst_umlal2_r_r_r ¶
Source

inst_umlal2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_umlal_r_r_r ¶
Source

inst_umlal_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_umlsl ¶
Source

inst_umlsl :: inst_umlsl_r_r_r

inst_umlsl2 ¶
Source

inst_umlsl2 :: inst_umlsl2_r_r_r

inst_umlsl2_r_r_r ¶
Source

inst_umlsl2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_umlsl_r_r_r ¶
Source

inst_umlsl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_umsubl ¶
Source

inst_umsubl :: inst_umsubl_r_r_r_r

inst_umsubl_r_r_r_r ¶
Source

inst_umsubl_r_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction {…}

inst_umulh ¶
Source

inst_umulh :: inst_umulh_r_r_r

inst_umulh_r_r_r ¶
Source

inst_umulh_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_umull2_v ¶
Source

inst_umull2_v :: inst_umull2_v_r_r_r

inst_umull2_v_r_r_r ¶
Source

inst_umull2_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_umull_v ¶
Source

inst_umull_v :: inst_umull_v_r_r_r

inst_umull_v_r_r_r ¶
Source

inst_umull_v_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uqadd ¶
Source

inst_uqadd :: inst_uqadd_r_r_r

inst_uqadd_r_r_r ¶
Source

inst_uqadd_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uqrshrn ¶
Source

inst_uqrshrn :: inst_uqrshrn_r_r_i

inst_uqrshrn2 ¶
Source

inst_uqrshrn2 :: inst_uqrshrn2_r_r_i

inst_uqrshrn2_r_r_i ¶
Source

inst_uqrshrn2_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_uqrshrn_r_r_i ¶
Source

inst_uqrshrn_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_uqshrn ¶
Source

inst_uqshrn :: inst_uqshrn_r_r_i

inst_uqshrn2 ¶
Source

inst_uqshrn2 :: inst_uqshrn2_r_r_i

inst_uqshrn2_r_r_i ¶
Source

inst_uqshrn2_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_uqshrn_r_r_i ¶
Source

inst_uqshrn_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_uqsub ¶
Source

inst_uqsub :: inst_uqsub_r_r_r

inst_uqsub_r_r_r ¶
Source

inst_uqsub_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uqxtn ¶
Source

inst_uqxtn :: inst_uqxtn_r_r

inst_uqxtn2 ¶
Source

inst_uqxtn2 :: inst_uqxtn2_r_r

inst_uqxtn2_r_r ¶
Source

inst_uqxtn2_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_uqxtn_r_r ¶
Source

inst_uqxtn_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_urecpe_v ¶
Source

inst_urecpe_v :: inst_urecpe_v_r_r

inst_urecpe_v_r_r ¶
Source

inst_urecpe_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_urhadd ¶
Source

inst_urhadd :: inst_urhadd_r_r_r

inst_urhadd_r_r_r ¶
Source

inst_urhadd_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_urshl ¶
Source

inst_urshl :: inst_urshl_r_r_r

inst_urshl_r_r_r ¶
Source

inst_urshl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_urshr ¶
Source

inst_urshr :: inst_urshr_r_r_i

inst_urshr_r_r_i ¶
Source

inst_urshr_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_ursqrte_v ¶
Source

inst_ursqrte_v :: inst_ursqrte_v_r_r

inst_ursqrte_v_r_r ¶
Source

inst_ursqrte_v_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_ursra ¶
Source

inst_ursra :: inst_ursra_r_r_i

inst_ursra_r_r_i ¶
Source

inst_ursra_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_usdot ¶
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inst_usdot :: inst_usdot_r_r_r

inst_usdot_r_r_r ¶
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inst_usdot_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_ushl ¶
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inst_ushl :: inst_ushl_r_r_r

inst_ushl_r_r_r ¶
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inst_ushl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_ushll ¶
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inst_ushll :: inst_ushll_r_r_i

inst_ushll2 ¶
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inst_ushll2 :: inst_ushll2_r_r_i

inst_ushll2_r_r_i ¶
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inst_ushll2_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_ushll_r_r_i ¶
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inst_ushll_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_ushr ¶
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inst_ushr :: inst_ushr_r_r_i

inst_ushr_r_r_i ¶
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inst_ushr_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_usra ¶
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inst_usra :: inst_usra_r_r_i

inst_usra_r_r_i ¶
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inst_usra_r_r_i :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

inst_usubl ¶
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inst_usubl :: inst_usubl_r_r_r

inst_usubl2 ¶
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inst_usubl2 :: inst_usubl2_r_r_r

inst_usubl2_r_r_r ¶
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inst_usubl2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_usubl_r_r_r ¶
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inst_usubl_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_usubw ¶
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inst_usubw :: inst_usubw_r_r_r

inst_usubw2 ¶
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inst_usubw2 :: inst_usubw2_r_r_r

inst_usubw2_r_r_r ¶
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inst_usubw2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_usubw_r_r_r ¶
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inst_usubw_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uxtb ¶
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inst_uxtb :: inst_uxtb_r_r

inst_uxtb_r_r ¶
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inst_uxtb_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_uxth ¶
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inst_uxth :: inst_uxth_r_r

inst_uxth_r_r ¶
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inst_uxth_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_uxtl ¶
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inst_uxtl :: inst_uxtl_r_r

inst_uxtl2 ¶
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inst_uxtl2 :: inst_uxtl2_r_r

inst_uxtl2_r_r ¶
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inst_uxtl2_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_uxtl_r_r ¶
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inst_uxtl_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_uxtw ¶
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inst_uxtw :: inst_uxtw_r_r

inst_uxtw_r_r ¶
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inst_uxtw_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_uzp1 ¶
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inst_uzp1 :: inst_uzp1_r_r_r

inst_uzp1_r_r_r ¶
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inst_uzp1_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_uzp2 ¶
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inst_uzp2 :: inst_uzp2_r_r_r

inst_uzp2_r_r_r ¶
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inst_uzp2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_wfe ¶
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inst_wfe :: inst_wfe_none

inst_wfe_none ¶
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inst_wfe_none :: proc "contextless" () -> Instruction {…}

inst_wfet ¶
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inst_wfet :: inst_wfet_r

inst_wfet_r ¶
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inst_wfet_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_wfi ¶
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inst_wfi :: inst_wfi_none

inst_wfi_none ¶
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inst_wfi_none :: proc "contextless" () -> Instruction {…}

inst_wfit ¶
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inst_wfit :: inst_wfit_r

inst_wfit_r ¶
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inst_wfit_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_xar ¶
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inst_xar :: inst_xar_r_r_r_i

inst_xar_r_r_r_i ¶
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inst_xar_r_r_r_i :: proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction {…}

inst_xpacd ¶
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inst_xpacd :: inst_xpacd_r

inst_xpacd_r ¶
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inst_xpacd_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_xpaci ¶
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inst_xpaci :: inst_xpaci_r

inst_xpaci_r ¶
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inst_xpaci_r :: proc "contextless" (dst: Register) -> Instruction {…}

inst_xpaclri ¶
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inst_xpaclri :: inst_xpaclri_none

inst_xpaclri_none ¶
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inst_xpaclri_none :: proc "contextless" () -> Instruction {…}

inst_xtn ¶
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inst_xtn :: inst_xtn_r_r

inst_xtn2 ¶
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inst_xtn2 :: inst_xtn2_r_r

inst_xtn2_r_r ¶
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inst_xtn2_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_xtn_r_r ¶
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inst_xtn_r_r :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

inst_yield ¶
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inst_yield :: inst_yield_none

inst_yield_none ¶
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inst_yield_none :: proc "contextless" () -> Instruction {…}

inst_zip1 ¶
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inst_zip1 :: inst_zip1_r_r_r

inst_zip1_r_r_r ¶
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inst_zip1_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

inst_zip2 ¶
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inst_zip2 :: inst_zip2_r_r_r

inst_zip2_r_r_r ¶
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inst_zip2_r_r_r :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

is_valid_bitmask_imm ¶
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is_valid_bitmask_imm :: proc "contextless" (value: u64, is_64: bool) -> bool {…}

is_valid_bitmask_imm returns true if value is a valid AArch64 logical- immediate when interpreted at the given width.

mem_ext ¶
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mem_ext :: proc "contextless" (base, index: Register, ext: Extend, shift_amount: u8 = 0) -> Memory {…}

mem_offset ¶
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mem_offset :: proc "contextless" (base: Register, disp: i32 = 0) -> Memory {…}

mem_post ¶
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mem_post :: proc "contextless" (base: Register, disp: i32) -> Memory {…}

mem_pre ¶
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mem_pre :: proc "contextless" (base: Register, disp: i32) -> Memory {…}

mem_reg ¶
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mem_reg :: proc "contextless" (base, index: Register, shift_amount: u8 = 0) -> Memory {…}

mnemonic_to_string ¶
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mnemonic_to_string :: proc(m: Mnemonic, lowercase: bool = true, allocator := context.temp_allocator) -> string {…}

op_cond ¶
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op_cond :: proc "contextless" (c: Cond) -> Operand {…}

op_extended ¶
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op_extended :: proc "contextless" (r: Register, ext: Extend, amount: u8) -> Operand {…}

op_imm ¶
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op_imm :: proc "contextless" (v: i64, size: u8 = 4) -> Operand {…}

op_label ¶
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op_label :: proc "contextless" (label_id: u32, size: u8 = 4) -> Operand {…}

op_mem ¶
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op_mem :: proc "contextless" (m: Memory) -> Operand {…}

op_reg ¶
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op_reg :: proc "contextless" (r: Register) -> Operand {…}

op_rel_offset ¶
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op_rel_offset :: proc "contextless" (off: i64) -> Operand {…}

op_shifted ¶
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op_shifted :: proc "contextless" (r: Register, type: Shift_Type, amount: u8) -> Operand {…}

op_v_16b ¶
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op_v_16b :: proc "contextless" (n: u8) -> Operand {…}

op_v_1d ¶
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op_v_1d :: proc "contextless" (n: u8) -> Operand {…}

op_v_2d ¶
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op_v_2d :: proc "contextless" (n: u8) -> Operand {…}

op_v_2s ¶
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op_v_2s :: proc "contextless" (n: u8) -> Operand {…}

op_v_4h ¶
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op_v_4h :: proc "contextless" (n: u8) -> Operand {…}

op_v_4s ¶
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op_v_4s :: proc "contextless" (n: u8) -> Operand {…}

op_v_8b ¶
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op_v_8b :: proc "contextless" (n: u8) -> Operand {…}

op_v_8h ¶
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op_v_8h :: proc "contextless" (n: u8) -> Operand {…}

op_v_elem_b ¶
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op_v_elem_b :: proc "contextless" (n: u8) -> Operand {…}

Element-indexed V views (V0.B[i]/.H[i]/.S[i]/.D[i]). The element size rides in op.size (1/2/4/8) so the matcher can disambiguate DUP/INS forms; the lane index is a separate immediate operand.

op_v_elem_d ¶
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op_v_elem_d :: proc "contextless" (n: u8) -> Operand {…}

op_v_elem_h ¶
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op_v_elem_h :: proc "contextless" (n: u8) -> Operand {…}

op_v_elem_s ¶
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op_v_elem_s :: proc "contextless" (n: u8) -> Operand {…}

op_z_b ¶
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op_z_b :: proc "contextless" (n: u8) -> Operand {…}

op_z_d ¶
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op_z_d :: proc "contextless" (n: u8) -> Operand {…}

op_z_h ¶
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op_z_h :: proc "contextless" (n: u8) -> Operand {…}

op_z_s ¶
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op_z_s :: proc "contextless" (n: u8) -> Operand {…}

pack_bitmask_fields ¶
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pack_bitmask_fields :: proc "contextless" (n, immr, imms: u8) -> i64 {…}

pack_bitmask_fields packs N:immr:imms into the 13-bit BITMASK_FIELD operand-immediate format consumed by the encoder packer.

pack_operand_inline ¶
Source

pack_operand_inline :: proc(
	op:       ^Operand, 
	enc:      Operand_Encoding, 
	form:     ^Encoding, 
	pc:       u32, 
	inst_idx: u16, 
	relocs:   ^[dynamic]Relocation, 
) -> u32 {…}

print ¶
Source

print :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

println ¶
Source

println :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

q_reg ¶
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q_reg :: proc "contextless" (n: u8) -> Register {…}

reg_class ¶
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reg_class :: proc "contextless" (r: Register) -> u16 {…}

reg_hw ¶
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reg_hw :: proc "contextless" (r: Register) -> u8 {…}

reg_is_w ¶
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reg_is_w :: proc "contextless" (r: Register) -> bool {…}

reg_is_wsp ¶
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reg_is_wsp :: proc "contextless" (r: Register) -> bool {…}

reg_is_x ¶
Source

reg_is_x :: proc "contextless" (r: Register) -> bool {…}

reg_is_xsp ¶
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reg_is_xsp :: proc "contextless" (r: Register) -> bool {…}

register_name ¶
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register_name :: proc(r: Register, lowercase: bool = true, allocator := context.temp_allocator) -> string {…}

s_reg ¶
Source

s_reg :: proc "contextless" (n: u8) -> Register {…}

sbprint ¶
Source

sbprint :: proc(
	sb:           ^strings.Builder, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

sbprintln ¶
Source

sbprintln :: proc(
	sb:           ^strings.Builder, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

sysreg_debug_breakpoint_control ¶
Source

sysreg_debug_breakpoint_control :: proc "contextless" (n: u32) -> i64 {…}

sysreg_debug_breakpoint_value ¶
Source

sysreg_debug_breakpoint_value :: proc "contextless" (n: u32) -> i64 {…}

sysreg_debug_watchpoint_control ¶
Source

sysreg_debug_watchpoint_control :: proc "contextless" (n: u32) -> i64 {…}

sysreg_debug_watchpoint_value ¶
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sysreg_debug_watchpoint_value :: proc "contextless" (n: u32) -> i64 {…}

sysreg_field ¶
Source

sysreg_field :: proc "contextless" (op0, op1, CRn, CRm, op2: u32) -> i64 {…}

sysreg_ich_ap0r ¶
Source

sysreg_ich_ap0r :: proc "contextless" (n: u32) -> i64 {…}

ICH_AP0Rn_EL2 (n=0..3) and ICH_AP1Rn_EL2 (n=0..3)

sysreg_ich_ap1r ¶
Source

sysreg_ich_ap1r :: proc "contextless" (n: u32) -> i64 {…}

sysreg_ich_lr ¶
Source

sysreg_ich_lr :: proc "contextless" (n: u32) -> i64 {…}

ICH_LR0_EL2 .. ICH_LR15_EL2 = sysreg(3, 4, 12, 12+(n>>3), n & 7)

sysreg_pmu_event_counter ¶
Source

sysreg_pmu_event_counter :: proc "contextless" (n: u32) -> i64 {…}

sysreg_pmu_event_typer ¶
Source

sysreg_pmu_event_typer :: proc "contextless" (n: u32) -> i64 {…}

tprint ¶
Source

tprint :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

tprintln ¶
Source

tprintln :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

unpack_bitmask_fields ¶
Source

unpack_bitmask_fields :: proc "contextless" (v: i64) -> (n, immr, imms: u8) {…}

unpack_bitmask_fields inverts pack_bitmask_fields.

v_reg ¶
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v_reg :: proc "contextless" (n: u8) -> Register {…}

w_reg ¶
Source

w_reg :: proc "contextless" (n: u8) -> Register {…}

wprint ¶
Source

wprint :: proc(
	w:            io.Stream, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

wprintln ¶
Source

wprintln :: proc(
	w:            io.Stream, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

x_reg ¶
Source

x_reg :: proc "contextless" (n: u8) -> Register {…}

Procedure Groups

emit_dup_v ¶
Source

emit_dup_v :: proc{
	emit_dup_v_r_r_i,
	emit_dup_v_r_r,
}

emit_ins ¶
Source

emit_ins :: proc{
	emit_ins_r_i_r_i,
	emit_ins_r_i_r,
}

emit_ret ¶
Source

emit_ret :: proc{
	emit_ret_r,
	emit_ret_none,
}

emit_sve_mov_p ¶
Source

emit_sve_mov_p :: proc{
	emit_sve_mov_p_p_p_p,
	emit_sve_mov_p_p_p,
}

inst_dup_v ¶
Source

inst_dup_v :: proc{
	inst_dup_v_r_r_i,
	inst_dup_v_r_r,
}

inst_ins ¶
Source

inst_ins :: proc{
	inst_ins_r_i_r_i,
	inst_ins_r_i_r,
}

inst_ret ¶
Source

inst_ret :: proc{
	inst_ret_r,
	inst_ret_none,
}

inst_sve_mov_p ¶
Source

inst_sve_mov_p :: proc{
	inst_sve_mov_p_p_p_p,
	inst_sve_mov_p_p_p,
}

Source Files

Generation Information

Generated with odin version dev-2026-07 (vendor "odin") Windows_amd64 @ 2026-07-20 21:55:32.451913700 +0000 UTC

package core:rexcode/isa/arm64Source

Overview

Index

Types

Related Procedures With Parameters

Related Constants

Related Procedures With Parameters

Related Procedures With Parameters

Related Procedures With Parameters

Related Procedures With Returns

Related Constants

Related Procedures With Parameters

Related Procedures With Returns

Related Procedures With Parameters

Related Procedures With Parameters

Related Procedures With Returns

Related Procedures With Parameters

Related Procedures With Parameters

Related Constants

Related Procedures With Parameters

Related Procedures With Returns

Related Constants

Related Procedures With Parameters

Constants

package core:rexcode/isa/arm64
Source