package core:rexcode/isa/mos65816

Source

Address_Mode :: enum u8 {
	DP, 
	DP_X, 
	DP_Y, 
	DP_IND, 
	DP_IND_X, 
	DP_IND_Y, 
	DP_IND_LONG, 
	DP_IND_LONG_Y, 
	ABS, 
	ABS_X, 
	ABS_Y, 
	ABS_IND, 
	ABS_IND_LONG, 
	ABS_IND_X, 
	LONG, 
	LONG_X, 
	SR, 
	SR_IND_Y, 
}

Assumed_State :: struct {
	m: bool,
	// M=1 (8-bit A/memory)         M=0 (16-bit A/memory)
	x: bool,
	// X=1 (8-bit X/Y)              X=0 (16-bit X/Y)
	e: bool,
}

Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [2]Operand_Type,
	// 2
	enc:      [2]Operand_Encoding,
	// 2
	opcode:   u8,
	// 1
	length:   u8,
	// 1
	flags:    Encoding_Flags,
}

Decode_Index :: struct #packed {
	start: u16,
	count: u16,
}

Encode_Run :: struct {
	start: u32,
	count: u32,
}

Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	opcode:   u8,
	// 1
	length:   u8,
	// 1
	flags:    Encoding_Flags,
}

Encoding_Flags :: distinct bit_field u8 {
	branch:      bool | 1,
	cond_branch: bool | 1,
	page_cross:  bool | 1,
	_:           u8 | 5,
}

Error :: rexcode_isa.Error

Error_Code :: rexcode_isa.Error_Code

GP :: enum u8 {
	A = 0, 
	X = 1, 
	Y = 2, 
	S = 3, 
	D = 4, 
}

Instruction :: struct #packed {
	ops:           [2]Operand `fmt:"v,operand_count"`,
	// 20 bytes (only MVN/MVP use 2; rest use 0 or 1)
	mnemonic:      Mnemonic,
	// 2
	operand_count: u8,
	// 1
	flags:         Instruction_Flags,
	// 1
	length:        u8,
	// 1
	_:             [7]u8,
}

Instruction_Flags :: distinct bit_field u8 {
	_: u8 | 8,
}

Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}

Label_Definition :: rexcode_isa.Label_Definition

Label_Map :: rexcode_isa.Label_Map

Label_Names :: map[rexcode_isa.Label_Offset]string

Label_Offset :: rexcode_isa.Label_Offset

Memory :: distinct bit_field u32 {
	address: u32 | 24,
	mode:    Address_Mode | 8,
}

Mnemonic :: enum u16 {
	INVALID = 0, 
	// 6502 core
	ADC, 
	AND, 
	ASL, 
	BIT, 
	CMP, 
	CPX, 
	CPY, 
	DEC, 
	DEX, 
	DEY, 
	EOR, 
	INC, 
	INX, 
	INY, 
	LSR, 
	ORA, 
	ROL, 
	ROR, 
	SBC, 
	LDA, 
	LDX, 
	LDY, 
	STA, 
	STX, 
	STY, 
	TAX, 
	TAY, 
	TSX, 
	TXA, 
	TXS, 
	TYA, 
	PHA, 
	PHP, 
	PLA, 
	PLP, 
	JMP, 
	JSR, 
	RTI, 
	RTS, 
	BRK, 
	NOP, 
	// Branches
	BCC, 
	BCS, 
	BEQ, 
	BMI, 
	BNE, 
	BPL, 
	BVC, 
	BVS, 
	// Flags
	CLC, 
	CLD, 
	CLI, 
	CLV, 
	SEC, 
	SED, 
	SEI, 
	// 65C02 additions (carry over to 65816)
	BRA, 
	STZ, 
	TRB, 
	TSB, 
	PHX, 
	PHY, 
	PLX, 
	PLY, 
	STP, 
	WAI, 
	// 65816 new
	BRL,         // 16-bit relative branch
	COP,         // co-processor enable (interrupt)
	JML,         // jump long (24-bit)
	JSL,         // jump-to-subroutine long (24-bit)
	MVN, 
	MVP,         // block move negative / positive
	PEA,         // push effective absolute address
	PEI,         // push effective indirect address
	PER,         // push effective PC-relative
	PHB, 
	PHD, 
	PHK,         // push DBR / D / PBR
	PLB, 
	PLD,         // pull  DBR / D
	REP, 
	SEP,         // reset / set status bits (immediate mask)
	RTL,         // return long
	TCD, 
	TDC,         // A <-> D
	TCS, 
	TSC,         // A <-> S
	TXY, 
	TYX,         // X <-> Y
	WDM,         // reserved (assembles as 2-byte no-op)
	XBA,         // exchange A halves (B <-> A)
	XCE,         // exchange Carry and Emulation flags
}

Operand :: struct #packed {
	using _: struct #raw_union {
		reg:       Register,
		mem:       Memory,
		immediate: i64,
		relative:  i64,
	},
	kind: Operand_Kind,
	size: u8,
}

Operand_Encoding :: enum u8 {
	NONE, 
	IMPL, 
	BYTE_1_IMM,  // 8-bit at offset 1
	WORD_1_IMM,  // 16-bit LE at offset 1
	BYTE_1_ADDR, // 8-bit zero/direct page address at offset 1
	WORD_1_ADDR, // 16-bit LE absolute at offset 1
	LONG_1_ADDR, // 24-bit LE long at offset 1
	BYTE_1_REL,  // signed 8-bit PC-rel at offset 1
	WORD_1_REL,  // signed 16-bit PC-rel at offset 1
	BYTE_1_BANK, // dst bank byte at offset 1 (MVN/MVP)
	BYTE_2_BANK, // src bank byte at offset 2 (MVN/MVP)
}

Operand_Kind :: enum u8 {
	NONE, 
	REGISTER,  // mostly used for `A` in `ROL A` (implicit; rarely needed)
	IMMEDIATE, 
	MEMORY, 
	RELATIVE,  // PC-relative target (label or raw byte offset)
}

Operand_Type :: enum u8 {
	NONE, 
	A_IMPL,            // accumulator -- no operand bytes
	// Immediates
	IMM_8,             // always 8-bit (COP, REP, SEP, WDM, BRK signature, ...)
	IMM_M8,            // 8-bit when M=1
	IMM_M16,           // 16-bit when M=0
	IMM_X8,            // 8-bit when X=1
	IMM_X16,           // 16-bit when X=0
	// Branches
	REL,               // signed 8-bit PC-rel
	REL_LONG,          // signed 16-bit PC-rel (BRL, PER)
	// Memory (one per addressing mode)
	MEM_DP, 
	MEM_DP_X, 
	MEM_DP_Y, 
	MEM_DP_IND, 
	MEM_DP_IND_X, 
	MEM_DP_IND_Y, 
	MEM_DP_IND_LONG, 
	MEM_DP_IND_LONG_Y, 
	MEM_ABS, 
	MEM_ABS_X, 
	MEM_ABS_Y, 
	MEM_ABS_IND, 
	MEM_ABS_IND_LONG, 
	MEM_ABS_IND_X, 
	MEM_LONG, 
	MEM_LONG_X, 
	MEM_SR, 
	MEM_SR_IND_Y, 
	// Block move: two 8-bit bank operands. Source order in the syntax
	// (MVN src, dst) is the REVERSE of the byte order in the encoding.
	BANK_SRC, 
	BANK_DST, 
}

Print_Options :: rexcode_isa.Print_Options

Print_Result :: rexcode_isa.Print_Result

Register :: distinct u16

Relocation :: struct #packed {
	offset:   u32,
	label_id: u32,
	addend:   i32,
	type:     Relocation_Type,
	size:     u8,
	inst_idx: u16,
}

Relocation_Type :: enum u8 {
	NONE  = 0, 
	ABS16, 
	ABS24, 
	REL8, 
	REL16, 
}

Token :: rexcode_isa.Token

Token_Kind :: rexcode_isa.Token_Kind

@(rodata)
DECODE_ENTRIES: []Decode_Entry = …

@(rodata)
DECODE_INDEX_OPCODE: []Decode_Index = …

@(rodata)
ENCODE_FORMS: []Encoding = …

@(rodata)
ENCODE_RUNS: []Encode_Run = …