package core:rexcode/isa/mips
Source

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    Overview

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    Index

    Procedures (4176)
    Procedure Groups (0)

    This section is empty.

    Types

    CP0_Reg ¶
    Source

    CP0_Reg :: enum u8 {
	INDEX    = 0, 
	RANDOM   = 1, 
	ENTRYLO0 = 2, 
	ENTRYLO1 = 3, 
	CONTEXT  = 4, 
	PAGEMASK = 5, 
	WIRED    = 6, 
	HWRENA   = 7, 
	BADVADDR = 8, 
	COUNT    = 9, 
	ENTRYHI  = 10, 
	COMPARE  = 11, 
	STATUS   = 12, 
	CAUSE    = 13, 
	EPC      = 14, 
	PRID     = 15, 
	CONFIG   = 16, 
	LLADDR   = 17, 
	WATCHLO  = 18, 
	WATCHHI  = 19, 
	XCONTEXT = 20, 
	DEBUG    = 23, 
	DEPC     = 24, 
	PERFCNT  = 25, 
	ERRCTL   = 26, 
	CACHEERR = 27, 
	TAGLO    = 28, 
	TAGHI    = 29, 
	ERROREPC = 30, 
	DESAVE   = 31, 
}
    Related Procedures With Parameters

    Decode_Entry ¶
    Source

    Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2 bytes
	ops:      [4]Operand_Type,
	// 4 bytes
	enc:      [4]Operand_Encoding,
	// 4 bytes
	bits:     u32,
	// 4 bytes — static bit pattern
	mask:     u32,
	// 4 bytes — which bits are static
	feature:  Feature,
	// 1 byte  — metadata
	flags:    Encoding_Flags,
}

    Decode_Index ¶
    Source

    Decode_Index :: struct #packed {
	start: u16,
	count: u16,
}

    Encode_Run ¶
    Source

    Encode_Run :: struct {
	start: u32,
	count: u32,
}
     

    Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS.

    Encoding ¶
    Source

    Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2 bytes
	ops:      [4]Operand_Type,
	// 4 bytes
	enc:      [4]Operand_Encoding,
	// 4 bytes
	bits:     u32,
	// 4 bytes — static bit pattern
	mask:     u32,
	// 4 bytes — which bits are static
	feature:  Feature,
	// 1 byte  — metadata
	flags:    Encoding_Flags,
}
     

    A single instruction encoding. bits holds the static pattern; mask marks which bits are static (so operand-derived bits OR in over zeros). Together they form a complete bit-level description.

    Encoding_Flags ¶
    Source

    Encoding_Flags :: distinct bit_field u8 {
	delay_slot:  bool | 1,
	likely:      bool | 1,
	only_64:     bool | 1,
	writes_hilo: bool | 1,
	compact:     bool | 1,
	_:           u8 | 3,
}

    Endianness ¶
    Source

    Endianness :: enum u8 {
	LITTLE = 0, 
	BIG    = 1, 
}
     

    Endianness flag (controls how the encoder serialises 32-bit words to bytes). Console targets: PS1, PS2, PSP = LITTLE; N64 = BIG; "MIPS canonical" = BIG.

    Related Procedures With Parameters

    Error ¶
    Source

    Error :: rexcode_isa.Error
     

    Re-exports from isa.

    Error_Code ¶
    Source

    Error_Code :: rexcode_isa.Error_Code

    FPR ¶
    Source

    FPR :: enum u8 {
	F0  = 0, 
	F1  = 1, 
	F2  = 2, 
	F3  = 3, 
	F4  = 4, 
	F5  = 5, 
	F6  = 6, 
	F7  = 7, 
	F8  = 8, 
	F9  = 9, 
	F10 = 10, 
	F11 = 11, 
	F12 = 12, 
	F13 = 13, 
	F14 = 14, 
	F15 = 15, 
	F16 = 16, 
	F17 = 17, 
	F18 = 18, 
	F19 = 19, 
	F20 = 20, 
	F21 = 21, 
	F22 = 22, 
	F23 = 23, 
	F24 = 24, 
	F25 = 25, 
	F26 = 26, 
	F27 = 27, 
	F28 = 28, 
	F29 = 29, 
	F30 = 30, 
	F31 = 31, 
}
    Related Procedures With Parameters

    Feature ¶
    Source

    Feature :: enum u8 {
	MIPS_I, 
	MIPS_II, 
	MIPS_III, 
	MIPS_IV, 
	MIPS_V, 
	MIPS32_R1, 
	MIPS32_R2, 
	MIPS32_R5, 
	MIPS32_R6, 
	MIPS64_R1, 
	MIPS64_R2, 
	MIPS64_R5, 
	MIPS64_R6, 
	COP0,      // system control coprocessor
	FPU,       // COP1 (any MIPS with FPU)
	DSP_R1, 
	DSP_R2, 
	MSA,       // MIPS SIMD
	GTE_PS1,   // PS1 R3000A Geometry Transformation Engine (COP2)
	MMI_PS2,   // PS2 R5900 Multimedia Instructions
	VU_PS2,    // PS2 VU0 macro-mode COP2 ops
	VFPU_PSP,  // PSP Allegrex Vector FPU
}
     

    ISA version + extension classification. Metadata: the matcher can optionally restrict picks to a chosen ISA level, and the printer can label disassembly with the introducing extension.

    GPR ¶
    Source

    GPR :: enum u8 {
	ZERO = 0, 
	AT   = 1, 
	V0   = 2, 
	V1   = 3, 
	A0   = 4, 
	A1   = 5, 
	A2   = 6, 
	A3   = 7, 
	T0   = 8, 
	T1   = 9, 
	T2   = 10, 
	T3   = 11, 
	T4   = 12, 
	T5   = 13, 
	T6   = 14, 
	T7   = 15, 
	S0   = 16, 
	S1   = 17, 
	S2   = 18, 
	S3   = 19, 
	S4   = 20, 
	S5   = 21, 
	S6   = 22, 
	S7   = 23, 
	T8   = 24, 
	T9   = 25, 
	K0   = 26, 
	K1   = 27, 
	GP   = 28, 
	SP   = 29, 
	FP   = 30, 
	RA   = 31, 
}
    Related Procedures With Parameters

    GTE_CtrlReg ¶
    Source

    GTE_CtrlReg :: enum u8 {
	R11R12 = 0, 
	R13R21 = 1, 
	R22R23 = 2, 
	R31R32 = 3, 
	R33    = 4, 
	TRX    = 5, 
	TRY    = 6, 
	TRZ    = 7, 
	L11L12 = 8, 
	L13L21 = 9, 
	L22L23 = 10, 
	L31L32 = 11, 
	L33    = 12, 
	RBK    = 13, 
	GBK    = 14, 
	BBK    = 15, 
	LR1LR2 = 16, 
	LR3LG1 = 17, 
	LG2LG3 = 18, 
	LB1LB2 = 19, 
	LB3    = 20, 
	RFC    = 21, 
	GFC    = 22, 
	BFC    = 23, 
	OFX    = 24, 
	OFY    = 25, 
	H      = 26, 
	DQA    = 27, 
	DQB    = 28, 
	ZSF3   = 29, 
	ZSF4   = 30, 
	FLAG   = 31, 
}
     

    PS1 GTE control registers (CFC2/CTC2).

    Related Procedures With Parameters

    GTE_DataReg ¶
    Source

    GTE_DataReg :: enum u8 {
	VXY0 = 0, 
	VZ0  = 1, 
	VXY1 = 2, 
	VZ1  = 3, 
	VXY2 = 4, 
	VZ2  = 5, 
	RGBC = 6, 
	OTZ  = 7, 
	IR0  = 8, 
	IR1  = 9, 
	IR2  = 10, 
	IR3  = 11, 
	SXY0 = 12, 
	SXY1 = 13, 
	SXY2 = 14, 
	SXYP = 15, 
	SZ0  = 16, 
	SZ1  = 17, 
	SZ2  = 18, 
	SZ3  = 19, 
	RGB0 = 20, 
	RGB1 = 21, 
	RGB2 = 22, 
	RES1 = 23, 
	MAC0 = 24, 
	MAC1 = 25, 
	MAC2 = 26, 
	MAC3 = 27, 
	IRGB = 28, 
	ORGB = 29, 
	LZCS = 30, 
	LZCR = 31, 
}
    Related Procedures With Parameters

    Instruction ¶
    Source

    Instruction :: struct #packed {
	ops:           [4]Operand `fmt:"v,operand_count"`,
	// 64 bytes
	mnemonic:      Mnemonic,
	//  2 bytes
	operand_count: u8,
	//  1 byte
	flags:         Instruction_Flags,
	//  1 byte
	length:        u8,
	//  1 byte — always 4 for now; will be 2 for future μMIPS / MIPS16e
	_:             [3]u8,
}
    Related Procedures With Returns

    Instruction_Flags ¶
    Source

    Instruction_Flags :: distinct bit_field u8 {
	_: u8 | 8,
}

    Instruction_Info ¶
    Source

    Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}
     

    ----------------------------------------------------------------------------- Per-decoded-instruction metadata (parallel to []Instruction). -----------------------------------------------------------------------------

    offset -- byte offset within data where this instruction starts. decode_entry -- index into DECODE_ENTRIES of the matched form; lets a printer query the Feature tag / flags without re-scanning.

    Label_Definition ¶
    Source

    Label_Definition :: rexcode_isa.Label_Definition
    Related Constants

    Label_Map ¶
    Source

    Label_Map :: rexcode_isa.Label_Map

    Memory ¶
    Source

    Memory :: struct #packed {
	base: Register,
	// 2 bytes
	_:    u16,
	// 2 bytes pad (keeps the struct power-of-two)
	disp: i32,
}
     

    Memory operand: GPR base + signed 16-bit displacement. Stored with a 32-bit disp slot to make the type comfortable to construct, even though only -32768..32767 actually encode.

    Related Procedures With Parameters
    Related Procedures With Returns

    Mnemonic ¶
    Source

    Mnemonic :: enum u16 {
	INVALID         = 0, 
	// R-type arithmetic
	ADD, 
	ADDU, 
	SUB, 
	SUBU, 
	MULT, 
	MULTU, 
	DIV, 
	DIVU, 
	MFHI, 
	MFLO, 
	MTHI, 
	MTLO, 
	AND, 
	OR, 
	XOR, 
	NOR, 
	SLT, 
	SLTU, 
	// R-type shifts
	SLL, 
	SRL, 
	SRA, 
	SLLV, 
	SRLV, 
	SRAV, 
	// I-type arithmetic
	ADDI, 
	ADDIU, 
	SLTI, 
	SLTIU, 
	ANDI, 
	ORI, 
	XORI, 
	LUI, 
	// I-type branches
	BEQ, 
	BNE, 
	BLEZ, 
	BGTZ, 
	// REGIMM branches
	BLTZ, 
	BGEZ, 
	BLTZAL, 
	BGEZAL, 
	// J-type
	J, 
	JAL, 
	// R-type jumps
	JR, 
	JALR, 
	// Loads
	LB, 
	LH, 
	LW, 
	LBU, 
	LHU, 
	LWL, 
	LWR, 
	// Stores
	SB, 
	SH, 
	SW, 
	SWL, 
	SWR, 
	// System
	SYSCALL, 
	BREAK, 
	NOP, 
	// Atomic
	LL, 
	SC, 
	// Synchronization
	SYNC, 
	// Traps (immediate and register variants)
	TGEI, 
	TGEIU, 
	TLTI, 
	TLTIU, 
	TEQI, 
	TNEI, 
	TGE, 
	TGEU, 
	TLT, 
	TLTU, 
	TEQ, 
	TNE, 
	// Branch-likely (skip delay slot if not taken)
	BEQL, 
	BNEL, 
	BLEZL, 
	BGTZL, 
	BLTZL, 
	BGEZL, 
	BLTZALL, 
	BGEZALL, 
	DADD, 
	DADDU, 
	DSUB, 
	DSUBU, 
	DADDI, 
	DADDIU, 
	DMULT, 
	DMULTU, 
	DDIV, 
	DDIVU, 
	DSLL, 
	DSRL, 
	DSRA, 
	DSLLV, 
	DSRLV, 
	DSRAV, 
	DSLL32, 
	DSRL32, 
	DSRA32, 
	LD, 
	LDL, 
	LDR, 
	LWU, 
	SD, 
	SDL, 
	SDR, 
	LLD, 
	SCD, 
	MOVN, 
	MOVZ, 
	MOVF, 
	MOVT,                // FP-condition-based GPR move
	PREF, 
	PREFX, 
	LWXC1, 
	SWXC1, 
	LDXC1, 
	SDXC1,               // indexed FP load/store
	CLZ, 
	CLO, 
	DCLZ, 
	DCLO, 
	MUL,                 // SPECIAL2 multiply-to-rd (doesn't touch HI/LO)
	MADD, 
	MADDU, 
	MSUB, 
	MSUBU, 
	SDBBP, 
	SSNOP, 
	EHB, 
	PAUSE, 
	// R2 bitfield + shuffle
	EXT, 
	INS, 
	DEXT, 
	DEXTM, 
	DEXTU, 
	DINS, 
	DINSM, 
	DINSU, 
	ROTR, 
	ROTRV, 
	DROTR, 
	DROTRV, 
	DROTR32, 
	WSBH, 
	DSBH, 
	DSHD, 
	SEB, 
	SEH, 
	// R2 misc
	RDHWR, 
	RDPGPR, 
	WRPGPR, 
	DI, 
	EI, 
	ERET, 
	DERET, 
	WAIT, 
	// Compact (no delay slot)
	BC, 
	BALC,                // 26-bit
	BEQC, 
	BNEC, 
	BLTC, 
	BGEC, 
	BLTUC, 
	BGEUC, 
	BLEZC, 
	BGEZC, 
	BGTZC, 
	BLTZC, 
	BEQZC, 
	BNEZC, 
	BC1EQZ, 
	BC1NEZ, 
	BC2EQZ, 
	BC2NEZ, 
	JIC, 
	JIALC, 
	// R6 mul/div (replaces MULT/MULTU/DIV/DIVU; results in single GPR)
	MUH, 
	MULU, 
	MUHU, 
	MOD, 
	MODU, 
	DMUL_R6, 
	DMUH, 
	DMULU, 
	DMUHU, 
	DDIV_R6, 
	DMOD, 
	DDIVU_R6, 
	DMODU, 
	// R6 PC-relative immediates
	AUI, 
	AUIPC, 
	ALUIPC, 
	DAUI, 
	DAHI, 
	DATI, 
	// R6 misc
	ALIGN, 
	DALIGN, 
	BITSWAP, 
	DBITSWAP, 
	LSA, 
	DLSA, 
	LWPC, 
	LWUPC, 
	LDPC, 
	SELEQZ, 
	SELNEZ, 
	// R6 CRC32 (optional in MIPS32 R6)
	CRC32B, 
	CRC32H, 
	CRC32W, 
	CRC32D, 
	CRC32CB, 
	CRC32CH, 
	CRC32CW, 
	CRC32CD, 
	SIGRIE,              // signal reserved instruction exception
	MFC1, 
	MTC1, 
	DMFC1, 
	DMTC1, 
	CFC1, 
	CTC1, 
	MFHC1, 
	MTHC1,               // R2: high word of paired single
	LWC1, 
	SWC1, 
	LDC1, 
	SDC1, 
	ADD_S, 
	ADD_D, 
	ADD_PS, 
	SUB_S, 
	SUB_D, 
	SUB_PS, 
	MUL_S, 
	MUL_D, 
	MUL_PS, 
	DIV_S, 
	DIV_D, 
	SQRT_S, 
	SQRT_D, 
	ABS_S, 
	ABS_D, 
	ABS_PS, 
	NEG_S, 
	NEG_D, 
	NEG_PS, 
	MOV_S, 
	MOV_D, 
	MOV_PS, 
	RECIP_S, 
	RECIP_D, 
	RSQRT_S, 
	RSQRT_D, 
	// FMA family (MIPS IV+)
	MADD_S, 
	MADD_D, 
	MADD_PS, 
	MSUB_S, 
	MSUB_D, 
	MSUB_PS, 
	NMADD_S, 
	NMADD_D, 
	NMADD_PS, 
	NMSUB_S, 
	NMSUB_D, 
	NMSUB_PS, 
	// Conditional move (FPR by GPR / FCC)
	MOVN_S, 
	MOVN_D, 
	MOVN_PS, 
	MOVZ_S, 
	MOVZ_D, 
	MOVZ_PS, 
	MOVF_S, 
	MOVF_D, 
	MOVF_PS, 
	MOVT_S, 
	MOVT_D, 
	MOVT_PS, 
	CVT_S_D, 
	CVT_S_W, 
	CVT_S_L, 
	CVT_D_S, 
	CVT_D_W, 
	CVT_D_L, 
	CVT_W_S, 
	CVT_W_D, 
	CVT_L_S, 
	CVT_L_D, 
	CVT_PS_S, 
	CVT_S_PU, 
	CVT_S_PL, 
	PLL_PS, 
	PLU_PS, 
	PUL_PS, 
	PUU_PS, 
	// FPU round-to-fixed-point
	ROUND_W_S, 
	ROUND_W_D, 
	ROUND_L_S, 
	ROUND_L_D, 
	TRUNC_W_S, 
	TRUNC_W_D, 
	TRUNC_L_S, 
	TRUNC_L_D, 
	CEIL_W_S, 
	CEIL_W_D, 
	CEIL_L_S, 
	CEIL_L_D, 
	FLOOR_W_S, 
	FLOOR_W_D, 
	FLOOR_L_S, 
	FLOOR_L_D, 
	C_F_S, 
	C_F_D, 
	C_F_PS, 
	C_UN_S, 
	C_UN_D, 
	C_UN_PS, 
	C_EQ_S, 
	C_EQ_D, 
	C_EQ_PS, 
	C_UEQ_S, 
	C_UEQ_D, 
	C_UEQ_PS, 
	C_OLT_S, 
	C_OLT_D, 
	C_OLT_PS, 
	C_ULT_S, 
	C_ULT_D, 
	C_ULT_PS, 
	C_OLE_S, 
	C_OLE_D, 
	C_OLE_PS, 
	C_ULE_S, 
	C_ULE_D, 
	C_ULE_PS, 
	C_SF_S, 
	C_SF_D, 
	C_SF_PS, 
	C_NGLE_S, 
	C_NGLE_D, 
	C_NGLE_PS, 
	C_SEQ_S, 
	C_SEQ_D, 
	C_SEQ_PS, 
	C_NGL_S, 
	C_NGL_D, 
	C_NGL_PS, 
	C_LT_S, 
	C_LT_D, 
	C_LT_PS, 
	C_NGE_S, 
	C_NGE_D, 
	C_NGE_PS, 
	C_LE_S, 
	C_LE_D, 
	C_LE_PS, 
	C_NGT_S, 
	C_NGT_D, 
	C_NGT_PS, 
	// FPU branches
	BC1F, 
	BC1T, 
	BC1FL, 
	BC1TL, 
	MFC0, 
	MTC0, 
	DMFC0, 
	DMTC0, 
	MFHC0, 
	MTHC0,               // R5+ high half of 64-bit registers
	TLBP, 
	TLBR, 
	TLBWI, 
	TLBWR, 
	CACHE, 
	// Standard COP2 moves (GTE registers via these)
	MFC2, 
	MTC2, 
	CFC2, 
	CTC2, 
	LWC2, 
	SWC2, 
	LDC2, 
	SDC2,                // LDC2/SDC2 exist on MIPS II+; PS1 R3000A does not implement
	// GTE ops (cofun-encoded, no GPR operands)
	RTPS, 
	RTPT, 
	DPCS, 
	DPCT, 
	INTPL, 
	MVMVA, 
	NCDS, 
	NCDT, 
	NCCS, 
	NCCT, 
	NCS, 
	NCT, 
	CDP, 
	CC, 
	NCLIP, 
	AVSZ3, 
	AVSZ4, 
	OP_GTE,              // "OP" (cross product) — disambiguated from MIPS R6 OP
	GPF, 
	GPL, 
	SQR_GTE,             // "SQR" — disambiguated from generic
	DCPL,                // depth-cue per light
	// 128-bit GPR load/store
	LQ, 
	SQ, 
	// VU0 macro-mode 128-bit COP2 moves
	LQC2, 
	SQC2, 
	// Second HI/LO pair (R5900 dual MAC)
	MFHI1, 
	MFLO1, 
	MTHI1, 
	MTLO1, 
	MULT1, 
	MULTU1, 
	DIV1, 
	DIVU1, 
	MADD_EE, 
	MADDU_EE, 
	MSUB_EE, 
	MSUBU_EE, 
	MADD1, 
	MADDU1, 
	MSUB1, 
	MSUBU1, 
	// Packed pack/unpack HI:LO
	PMFHL_LW, 
	PMFHL_UW, 
	PMFHL_LH, 
	PMFHL_SH, 
	PMFHL_SLW, 
	PMTHL_LW, 
	// Parallel arithmetic (byte/halfword/word lanes)
	PADDB, 
	PADDH, 
	PADDW, 
	PADDSB, 
	PADDSH, 
	PADDSW, 
	PADDUB, 
	PADDUH, 
	PADDUW, 
	PSUBB, 
	PSUBH, 
	PSUBW, 
	PSUBSB, 
	PSUBSH, 
	PSUBSW, 
	PSUBUB, 
	PSUBUH, 
	PSUBUW, 
	// Parallel shifts
	PSLLH, 
	PSRLH, 
	PSRAH, 
	PSLLW, 
	PSRLW, 
	PSRAW, 
	PSLLVW, 
	PSRLVW, 
	PSRAVW, 
	QFSRV,               // quad funnel shift right (across 128 bits)
	// Parallel logical
	PAND, 
	POR, 
	PXOR, 
	PNOR, 
	// Parallel compare
	PCEQB, 
	PCEQH, 
	PCEQW, 
	PCGTB, 
	PCGTH, 
	PCGTW, 
	// Parallel multiply / divide
	PMULTW, 
	PMULTUW, 
	PMULTH, 
	PMADDW, 
	PMADDUW, 
	PMADDH, 
	PMSUBW, 
	PMSUBH, 
	PHMADH, 
	PHMSBH, 
	PDIVW, 
	PDIVUW, 
	PDIVBW, 
	// Pack / rearrange
	PCPYLD, 
	PCPYUD, 
	PCPYH, 
	PINTH, 
	PINTOH, 
	PEXEH, 
	PEXEW, 
	PEXCH, 
	PEXCW, 
	PROT3W, 
	PPACB, 
	PPACH, 
	PPACW, 
	PPAC5, 
	PEXT5, 
	PEXTLB, 
	PEXTLH, 
	PEXTLW, 
	PEXTUB, 
	PEXTUH, 
	PEXTUW, 
	// MMI HI/LO helpers
	PMFHI, 
	PMFLO, 
	PMTHI, 
	PMTLO, 
	// Misc MMI
	PLZCW, 
	PABSH, 
	PABSW, 
	PMAXH, 
	PMAXW, 
	PMINH, 
	PMINW, 
	// Shift-amount register
	MFSA, 
	MTSA, 
	MTSAB, 
	MTSAH, 
	// Packed add/sub (saturating)
	ADDQ_PH, 
	ADDQ_S_PH, 
	ADDQ_S_W, 
	SUBQ_PH, 
	SUBQ_S_PH, 
	SUBQ_S_W, 
	ADDU_QB, 
	ADDU_S_QB, 
	ADDU_PH, 
	ADDU_S_PH, 
	SUBU_QB, 
	SUBU_S_QB, 
	SUBU_PH, 
	SUBU_S_PH, 
	ADDSC, 
	ADDWC,               // 32-bit + carry/borrow
	// Packed multiply / dot-product / accumulate
	MULEU_S_PH_QBL, 
	MULEU_S_PH_QBR, 
	MULEQ_S_W_PHL, 
	MULEQ_S_W_PHR, 
	MULQ_RS_PH, 
	MULQ_S_PH, 
	MULSAQ_S_W_PH, 
	DPAQ_S_W_PH, 
	DPSQ_S_W_PH, 
	DPAQ_SA_L_W, 
	DPSQ_SA_L_W, 
	DPAU_H_QBL, 
	DPAU_H_QBR, 
	DPSU_H_QBL, 
	DPSU_H_QBR, 
	DPA_W_PH, 
	DPS_W_PH,            // R2
	DPAX_W_PH, 
	DPSX_W_PH,           // R2
	MAQ_S_W_PHL, 
	MAQ_S_W_PHR, 
	MAQ_SA_W_PHL, 
	MAQ_SA_W_PHR, 
	// Extract / position / accumulator helpers
	EXTR_W, 
	EXTR_R_W, 
	EXTR_RS_W, 
	EXTR_S_H, 
	EXTRV_W, 
	EXTRV_R_W, 
	EXTRV_RS_W, 
	EXTRV_S_H, 
	EXTP, 
	EXTPV, 
	EXTPDP, 
	EXTPDPV, 
	SHILO, 
	SHILOV, 
	MTHLIP, 
	WRDSP, 
	RDDSP, 
	// Pack / unpack
	PRECRQ_QB_PH, 
	PRECRQ_PH_W, 
	PRECRQU_S_QB_PH, 
	PRECEQ_W_PHL, 
	PRECEQ_W_PHR, 
	PRECEQU_PH_QBL, 
	PRECEQU_PH_QBR, 
	PRECEQU_PH_QBLA, 
	PRECEQU_PH_QBRA, 
	PRECEU_PH_QBL, 
	PRECEU_PH_QBR, 
	PRECEU_PH_QBLA, 
	PRECEU_PH_QBRA, 
	PRECRQ_RS_PH_W, 
	// Compare / pick
	CMPU_EQ_QB, 
	CMPU_LT_QB, 
	CMPU_LE_QB, 
	CMP_EQ_PH, 
	CMP_LT_PH, 
	CMP_LE_PH, 
	CMPGU_EQ_QB, 
	CMPGU_LT_QB, 
	CMPGU_LE_QB, 
	PICK_QB, 
	PICK_PH, 
	// Shift
	SHLL_QB, 
	SHLL_PH, 
	SHLL_S_PH, 
	SHLL_S_W, 
	SHLLV_QB, 
	SHLLV_PH, 
	SHLLV_S_PH, 
	SHLLV_S_W, 
	SHRL_QB, 
	SHRL_PH, 
	SHRLV_QB, 
	SHRLV_PH, 
	SHRA_QB, 
	SHRA_R_QB, 
	SHRA_PH, 
	SHRA_R_PH, 
	SHRA_R_W, 
	SHRAV_QB, 
	SHRAV_R_QB, 
	SHRAV_PH, 
	SHRAV_R_PH, 
	SHRAV_R_W, 
	// Indexed loads (rs+rt addressing) — register-register addressing.
	LBUX, 
	LHX, 
	LWX, 
	// DSP control / branch
	BPOSGE32,            // branch if DSPControl.pos >= 32
	INSV,                // insert variable position
	BITREV,              // R2 bit reversal
	ABSQ_S_PH, 
	ABSQ_S_W, 
	REPL_PH, 
	REPLV_PH, 
	REPL_QB, 
	REPLV_QB, 
	// Vector register-register integer arithmetic (.B/.H/.W/.D lane width)
	ADDV_B, 
	ADDV_H, 
	ADDV_W, 
	ADDV_D, 
	SUBV_B, 
	SUBV_H, 
	SUBV_W, 
	SUBV_D, 
	ADDS_S_B, 
	ADDS_S_H, 
	ADDS_S_W, 
	ADDS_S_D, 
	ADDS_U_B, 
	ADDS_U_H, 
	ADDS_U_W, 
	ADDS_U_D, 
	SUBS_S_B, 
	SUBS_S_H, 
	SUBS_S_W, 
	SUBS_S_D, 
	SUBS_U_B, 
	SUBS_U_H, 
	SUBS_U_W, 
	SUBS_U_D, 
	MULV_B, 
	MULV_H, 
	MULV_W, 
	MULV_D, 
	DIV_S_B, 
	DIV_S_H, 
	DIV_S_W, 
	DIV_S_D, 
	DIV_U_B, 
	DIV_U_H, 
	DIV_U_W, 
	DIV_U_D, 
	MOD_S_B, 
	MOD_S_H, 
	MOD_S_W, 
	MOD_S_D, 
	MOD_U_B, 
	MOD_U_H, 
	MOD_U_W, 
	MOD_U_D, 
	MADDV_B, 
	MADDV_H, 
	MADDV_W, 
	MADDV_D, 
	MSUBV_B, 
	MSUBV_H, 
	MSUBV_W, 
	MSUBV_D, 
	DOTP_S_H, 
	DOTP_S_W, 
	DOTP_S_D, 
	DOTP_U_H, 
	DOTP_U_W, 
	DOTP_U_D, 
	// Vector logical
	AND_V, 
	OR_V, 
	NOR_V, 
	XOR_V, 
	ANDI_B, 
	ORI_B, 
	NORI_B, 
	XORI_B, 
	BSEL_V, 
	BSELI_B, 
	BMNZ_V, 
	BMNZI_B, 
	BMZ_V, 
	BMZI_B, 
	// Vector compare
	CEQ_B, 
	CEQ_H, 
	CEQ_W, 
	CEQ_D, 
	CLT_S_B, 
	CLT_S_H, 
	CLT_S_W, 
	CLT_S_D, 
	CLT_U_B, 
	CLT_U_H, 
	CLT_U_W, 
	CLT_U_D, 
	CLE_S_B, 
	CLE_S_H, 
	CLE_S_W, 
	CLE_S_D, 
	CLE_U_B, 
	CLE_U_H, 
	CLE_U_W, 
	CLE_U_D, 
	// Vector min/max
	MIN_S_B, 
	MIN_S_H, 
	MIN_S_W, 
	MIN_S_D, 
	MIN_U_B, 
	MIN_U_H, 
	MIN_U_W, 
	MIN_U_D, 
	MAX_S_B, 
	MAX_S_H, 
	MAX_S_W, 
	MAX_S_D, 
	MAX_U_B, 
	MAX_U_H, 
	MAX_U_W, 
	MAX_U_D, 
	// Vector shifts
	SLL_B, 
	SLL_H, 
	SLL_W, 
	SLL_D, 
	SRL_B, 
	SRL_H, 
	SRL_W, 
	SRL_D, 
	SRA_B, 
	SRA_H, 
	SRA_W, 
	SRA_D, 
	SLLI_B, 
	SLLI_H, 
	SLLI_W, 
	SLLI_D, 
	SRLI_B, 
	SRLI_H, 
	SRLI_W, 
	SRLI_D, 
	SRAI_B, 
	SRAI_H, 
	SRAI_W, 
	SRAI_D, 
	// Vector FP arithmetic
	FADD_W, 
	FADD_D, 
	FSUB_W, 
	FSUB_D, 
	FMUL_W, 
	FMUL_D, 
	FDIV_W, 
	FDIV_D, 
	FSQRT_W, 
	FSQRT_D, 
	FRSQRT_W, 
	FRSQRT_D, 
	FRCP_W, 
	FRCP_D, 
	FRINT_W, 
	FRINT_D, 
	FMAX_W, 
	FMAX_D, 
	FMIN_W, 
	FMIN_D, 
	FCEQ_W, 
	FCEQ_D, 
	FCNE_W, 
	FCNE_D, 
	FCLT_W, 
	FCLT_D, 
	FCLE_W, 
	FCLE_D, 
	// Vector conversion
	FFINT_S_W, 
	FFINT_S_D, 
	FFINT_U_W, 
	FFINT_U_D, 
	FTRUNC_S_W, 
	FTRUNC_S_D, 
	FTRUNC_U_W, 
	FTRUNC_U_D, 
	FCVT_S_W, 
	FCVT_S_D, 
	FCVT_D_W, 
	// Vector load/store + immediate
	LD_B, 
	LD_H, 
	LD_W, 
	LD_D, 
	ST_B, 
	ST_H, 
	ST_W, 
	ST_D, 
	LDI_B, 
	LDI_H, 
	LDI_W, 
	LDI_D, 
	// Vector shuffle / copy / insert
	COPY_S_B, 
	COPY_S_H, 
	COPY_S_W, 
	COPY_U_B, 
	COPY_U_H, 
	COPY_U_W, 
	INSERT_B, 
	INSERT_H, 
	INSERT_W, 
	INSERT_D, 
	INSVE_B, 
	INSVE_H, 
	INSVE_W, 
	INSVE_D, 
	SHF_B, 
	SHF_H, 
	SHF_W, 
	VSHF_B, 
	VSHF_H, 
	VSHF_W, 
	VSHF_D, 
	SLD_B, 
	SLD_H, 
	SLD_W, 
	SLD_D, 
	SLDI_B, 
	SLDI_H, 
	SLDI_W, 
	SLDI_D, 
	SPLAT_B, 
	SPLAT_H, 
	SPLAT_W, 
	SPLAT_D, 
	SPLATI_B, 
	SPLATI_H, 
	SPLATI_W, 
	SPLATI_D, 
	// MSA branches (vector all-zero / any-non-zero across all lanes / per-lane)
	BZ_V, 
	BNZ_V, 
	BZ_B, 
	BZ_H, 
	BZ_W, 
	BZ_D, 
	BNZ_B, 
	BNZ_H, 
	BNZ_W, 
	BNZ_D, 
	// Element-permute / count / bit-ops
	NLOC_B, 
	NLOC_H, 
	NLOC_W, 
	NLOC_D, 
	NLZC_B, 
	NLZC_H, 
	NLZC_W, 
	NLZC_D, 
	PCNT_B, 
	PCNT_H, 
	PCNT_W, 
	PCNT_D, 
	// Move / load / store / immediates
	VMOV_S, 
	VMOV_P, 
	VMOV_T, 
	VMOV_Q, 
	LV_S, 
	LV_Q, 
	SV_S, 
	SV_Q, 
	LVL_Q, 
	LVR_Q, 
	SVL_Q, 
	SVR_Q, 
	VIIM_S, 
	VFIM_S, 
	// Arithmetic
	VADD_S, 
	VADD_P, 
	VADD_T, 
	VADD_Q, 
	VSUB_S, 
	VSUB_P, 
	VSUB_T, 
	VSUB_Q, 
	VMUL_S, 
	VMUL_P, 
	VMUL_T, 
	VMUL_Q, 
	VDIV_S, 
	VDIV_P, 
	VDIV_T, 
	VDIV_Q, 
	VABS_S, 
	VABS_P, 
	VABS_T, 
	VABS_Q, 
	VNEG_S, 
	VNEG_P, 
	VNEG_T, 
	VNEG_Q, 
	VSQRT_S, 
	VRCP_S, 
	VRCP_P, 
	VRCP_T, 
	VRCP_Q, 
	VRSQ_S, 
	VRSQ_P, 
	VRSQ_T, 
	VRSQ_Q, 
	// Reductions / dot / scale
	VDOT_P, 
	VDOT_T, 
	VDOT_Q, 
	VSCL_P, 
	VSCL_T, 
	VSCL_Q, 
	VHDP_P, 
	VHDP_T, 
	VHDP_Q, 
	VAVG_P, 
	VAVG_T, 
	VAVG_Q, 
	VFAD_P, 
	VFAD_T, 
	VFAD_Q, 
	// Matrix ops
	VMMUL_P, 
	VMMUL_T, 
	VMMUL_Q, 
	VTFM2_P, 
	VTFM3_T, 
	VTFM4_Q, 
	VHTFM2_P, 
	VHTFM3_T, 
	VHTFM4_Q, 
	VMSCL_P, 
	VMSCL_T, 
	VMSCL_Q, 
	VMMOV_P, 
	VMMOV_T, 
	VMMOV_Q, 
	VMIDT_P, 
	VMIDT_T, 
	VMIDT_Q, 
	VMZERO_P, 
	VMZERO_T, 
	VMZERO_Q, 
	VMONE_P, 
	VMONE_T, 
	VMONE_Q, 
	// Cross / quaternion
	VCRS_T, 
	VCRSP_T, 
	VQMUL_Q, 
	// Compares & sel
	VCMP_S, 
	VCMP_P, 
	VCMP_T, 
	VCMP_Q, 
	VMIN_S, 
	VMIN_P, 
	VMIN_T, 
	VMIN_Q, 
	VMAX_S, 
	VMAX_P, 
	VMAX_T, 
	VMAX_Q, 
	// Transcendentals
	VSIN_S, 
	VCOS_S, 
	VEXP2_S, 
	VLOG2_S, 
	VASIN_S, 
	VNRCP_S, 
	VNSIN_S, 
	VREXP2_S, 
	VSGN_S, 
	// Conversion
	VI2F_S, 
	VI2F_P, 
	VI2F_T, 
	VI2F_Q, 
	VF2IN_S, 
	VF2IN_P, 
	VF2IN_T, 
	VF2IN_Q, 
	VF2IZ_S, 
	VF2IZ_P, 
	VF2IZ_T, 
	VF2IZ_Q, 
	VF2IU_S, 
	VF2IU_P, 
	VF2IU_T, 
	VF2IU_Q, 
	VF2ID_S, 
	VF2ID_P, 
	VF2ID_T, 
	VF2ID_Q, 
	VF2H_P, 
	VH2F_S, 
	// Control / move-between
	VFLUSH, 
	VSYNC, 
	VNOP, 
	VPFXS, 
	VPFXT, 
	VPFXD, 
	VCST_S, 
	VCST_P, 
	VCST_T, 
	VCST_Q, 
	MFV, 
	MTV, 
	MFVC, 
	MTVC, 
	BVF, 
	BVT, 
	BVFL, 
	BVTL, 
}
    Related Procedures With Parameters

    Operand ¶
    Source

    Operand :: struct #packed {
	using _: struct #raw_union {
		reg:       Register,
		// 2 bytes
		mem:       Memory,
		// 8 bytes
		immediate: i64,
		// 8 bytes
		relative:  i64,
	},
	kind: Operand_Kind,
	// 1 byte
	size: u8,
}
     

    Operand: kind-tagged union, 16 bytes.

    Related Procedures With Returns

    Operand_Encoding ¶
    Source

    Operand_Encoding :: enum u8 {
	NONE, 
	// Standard MIPS field placements (R/I-type)
	RS,                // bits 25-21
	RT,                // bits 20-16
	RD,                // bits 15-11
	SHAMT,             // bits 10-6
	// FP register placements (FR-format; overlap RS/RT/RD/SHAMT positions)
	FT,                // bits 20-16
	FS,                // bits 15-11
	FD,                // bits 10-6
	// Immediates
	IMM_16,            // bits 15-0
	IMM_5,             // bits 10-6 (same slot as SHAMT)
	IMM_20,            // bits 25-6 (SYSCALL/BREAK code)
	IMM_26,            // bits 25-0 (J-type target word)
	// Memory: implicit RS + IMM_16
	OFFSET_BASE, 
	// PC-relative
	BRANCH_16,         // bits 15-0 as PC-relative word offset (delay-slot adjusted)
	BRANCH_21,         // R6 compact branch: bits 20-0
	BRANCH_26,         // R6 compact branch: bits 25-0
	BRANCH_19,         // R6 PC-relative load: bits 18-0 (LWPC/LWUPC)
	BRANCH_18,         // R6 PC-relative load: bits 17-0 (LDPC)
	// FP condition code
	FCC_BC,            // bits 20-18 (FP branches, MOVF/MOVT)
	FCC_CC,            // bits 10-8 (C.cond compare results)
	// CP0 selector
	SEL,               // bits 2-0
	// Implicit (operand exists in the asm syntax but is not encoded;
	// e.g. $zero in branch-likely synthetic forms).
	IMPL, 
	// GTE cofun selectors (bit positions within the 25-bit cofun field)
	GTE_SF_BIT,        // bit 19
	GTE_MX_BITS,       // bits 18-17
	GTE_V_BITS,        // bits 16-15
	GTE_CV_BITS,       // bits 14-13
	GTE_LM_BIT,        // bit 10
	// ---- PSP VFPU register slots ------------------------------------------
	// 
	// VFPU registers use 7-bit IDs (0..127). The standard 3-operand layout:
	//   bits 22:16 = vt   (7-bit register ID)
	//   bits 14:8  = vs   (7-bit register ID)
	//   bits  6:0  = vd   (7-bit register ID)
	// The width-modifier bits (bit 15 + bit 7) are NOT operand-driven --
	// they're baked into the form's static `bits` per the .s/.p/.t/.q
	// mnemonic suffix, so:
	//   .s = bit15=0, bit7=0
	//   .p = bit15=0, bit7=1
	//   .t = bit15=1, bit7=0
	//   .q = bit15=1, bit7=1
	VFPU_VD, 
	VFPU_VS, 
	VFPU_VT, 
	// VFPU register for memory ops where the 7-bit ID is SPLIT:
	//   bits 20:16 = vt[6:2]   (top 5 bits at the rt position)
	//   bits  1:0  = vt[1:0]   (bottom 2 bits at the very low position)
	// Used by LV.S / SV.S / LV.Q / SV.Q.
	VFPU_VT_MEM, 
	// VFPU SP-style memory operand: base GPR at bits 25:21 + signed-16
	// displacement at bits 15:2 (low 2 bits forced 0 = multiple of 4 for S,
	// multiple of 16 for Q -- user responsible for alignment).
	VFPU_OFFSET_BASE, 
	// VFPU prefix immediate: 20-bit prefix mask at bits 19:0 (VPFXS/T/D).
	VFPU_PFX, 
	// VFPU constant selector / 5-bit immediate at bits 20:16 (VCST, VF2I*).
	VFPU_CONST, 
	// VFPU 4-bit condition code at bits 3:0 (VCMP).
	VFPU_COND4, 
	// VFPU 3-bit VCC selector at bits 18:16 (BVF / BVT / BVFL / BVTL).
	VFPU_CC3, 
	// MSA 3R-format register slots:
	//   wd at bits 10:6 (alias of RD/SHAMT bit positions)
	//   ws at bits 15:11 (alias of RD)
	//   wt at bits 20:16 (alias of RT)
	WD, 
	WS, 
	WT, 
	// MSA element-index / immediate fields used by some forms (ELM/I5/BIT)
	MSA_I5,            // 5-bit immediate at bits 20:16 (LDI/I5 forms)
	MSA_S10,           // signed 10-bit displacement at bits 25:16 (MI10 load/store)
	MSA_BIT5,          // bit position (5-bit) at bits 16:11 (BIT form)
	// The shift amount / element index sits at bits 22:16 / 21:16 with the data
	// format encoded by the high (marker) bits; the operand drives the low bits
	// (the marker is fixed in the entry `bits`). Decode infers df from the marker.
	MSA_BIT_SHIFT,     // BIT-format shift amount (.B m=0x70|sh, .H 0x60|sh, .W 0x40|sh, .D sh)
	MSA_ELM_IDX,       // ELM-format element index (.B n, .H 0x20|n, .W 0x30|n, .D 0x38|n)
	MSA_I8,            // 8-bit immediate at bits 23:16 (I8 forms: ANDI.B/SHF/...)
	FR,                // FP register at bits 25:21 (COP1X 4-register FMA: fr)
	GPR_AT_6,          // GPR at bits 10:6 (MSA COPY destination)
	GPR_AT_11,         // GPR at bits 15:11 (MSA INSERT source)
	DSP_SA,            // DSP shift amount at bits 24:21 (.PH 4-bit, .QB 3-bit)
	RS_RT,             // same GPR in both rs (25:21) and rt (20:16) (R6 BGEZC/BLTZC)
	AC_NUM,            // DSP accumulator number ac0..ac3 at bits 12:11 (immediate)
	SHILO_IMM,         // DSP SHILO signed 6-bit shift at bits 25:20
	EXT_SIZE,          // DSP EXTPDP extract size, 5-bit immediate at bits 25:21
	// MSA memory operand: base GPR at bits 15:11 + signed 10-bit disp at 25:16,
	// scaled by element size (1/2/4/8 for B/H/W/D).
	MSA_OFFSET_BASE_B, 
	MSA_OFFSET_BASE_H, 
	MSA_OFFSET_BASE_W, 
	MSA_OFFSET_BASE_D, 
}
     

    Operand ENCODING — where each operand's bits go in the instruction word.

    Operand_Kind ¶
    Source

    Operand_Kind :: enum u8 {
	NONE, 
	REGISTER, 
	MEMORY, 
	IMMEDIATE, 
	RELATIVE,  // PC-relative target (label or raw offset)
}

    Operand_Type ¶
    Source

    Operand_Type :: enum u8 {
	NONE, 
	// Integer registers
	GPR, 
	GPR_ZERO, // implicit $zero (rare; for disambiguation)
	// FP register, format-tagged
	FPR_S, 
	FPR_D, 
	FPR_W, 
	FPR_L, 
	FPR_PS, 
	FCR,      // FP control reg ($fcr0/$fccr/$fexr/$fenr/$fcsr)
	// Coprocessor registers
	CP0_REG,  // CP0 register (0-31), with optional sel
	CP2_REG,  // COP2 data register (GTE V*/MAC*/SXY*; VU vf*)
	CP2_CTRL, // COP2 control register
	// VFPU registers (PSP) — single, pair, triple, quad
	VFPU_S, 
	VFPU_P, 
	VFPU_T, 
	VFPU_Q, 
	VFPU_M_P, 
	VFPU_M_T, 
	VFPU_M_Q, // matrix forms
	// MSA vector register (W0..W31). Format suffix (.B/.H/.W/.D) is baked
	// into the mnemonic, so a single operand-type is enough at match time.
	MSA_VEC, 
	// Immediates
	IMM5,     // 5-bit shift amount or small literal
	IMM16S,   // signed 16-bit
	IMM16U,   // unsigned (zero-extended) 16-bit
	IMM20,    // 20-bit SYSCALL/BREAK/SDBBP code
	IMM26,    // 26-bit J-type target word
	SEL,      // CP0 selector (3 bits, R2+)
	// PC-relative branch targets
	REL16,    // 16-bit signed offset (<<2), I-type branches
	REL_J26,  // 26-bit region jump (J / JAL)
	REL21,    // R6 21-bit compact branch (BC1EQZ/NEZ)
	REL26,    // R6 26-bit compact branch (BC/BALC)
	REL19,    // R6 PC-relative load (LWPC/LWUPC, 19-bit << 2)
	REL18,    // R6 PC-relative load (LDPC, 18-bit << 3)
	// Memory: base GPR + 16-bit signed displacement
	MEM, 
	// Condition codes / cofun selectors
	FCC,      // FP condition-code field (3 bits)
	// GTE-specific cofun selectors (the few that are user-visible)
	GTE_SF, 
	GTE_MX, 
	GTE_V, 
	GTE_CV, 
	GTE_LM, 
}
     

    Operand TYPES — what the user passes in.

    Print_Options :: rexcode_isa.Print_Options
    Related Procedures With Parameters
    Related Constants
    Print_Result :: rexcode_isa.Print_Result

    Register ¶
    Source

    Register :: distinct u16
    Related Procedures With Parameters
    Related Procedures With Returns
    Related Constants

    Relocation ¶
    Source

    Relocation :: struct #packed {
	offset:   u32,
	label_id: u32,
	addend:   i32,
	type:     Relocation_Type,
	size:     u8,
	inst_idx: u16,
}

    Relocation_Type ¶
    Source

    Relocation_Type :: enum u8 {
	NONE     = 0, 
	REL16,        // 16-bit signed PC-rel branch offset (BEQ/BNE/BLEZ/BGTZ/...)
	REL21,        // 21-bit signed PC-rel compact branch (R6 BEQZC/BNEZC)
	REL26,        // 26-bit signed PC-rel compact branch (R6 BC/BALC)
	REL_PC19,     // 19-bit R6 PC-relative load offset ((target - PC) >> 2)  (LWPC/LWUPC)
	REL_PC18,     // 18-bit R6 PC-relative load offset ((target - (PC & ~7)) >> 3)  (LDPC)
	J26,          // 26-bit J-type region target ((target_addr >> 2) & 0x3FFFFFF)
	HI16,         // upper 16 of 32-bit absolute (LUI rt, %hi(sym)+0x8000 if LO16 paired)
	LO16,         // lower 16 of 32-bit absolute (ADDIU rt, rt, %lo(sym))
}

    Token ¶
    Source

    Token :: rexcode_isa.Token
     

    Re-exports.

    Token_Kind ¶
    Source

    Token_Kind :: rexcode_isa.Token_Kind

    Constants

    A0 ¶
    Source

    A0 :: Register(REG_GPR | 4)

    A1 ¶
    Source

    A1 :: Register(REG_GPR | 5)

    A2 ¶
    Source

    A2 :: Register(REG_GPR | 6)

    A3 ¶
    Source

    A3 :: Register(REG_GPR | 7)

    AT ¶
    Source

    AT :: Register(REG_GPR | 1)

    DEFAULT_PRINT_OPTIONS ¶
    Source

    DEFAULT_PRINT_OPTIONS: rexcode_isa.Print_Options : isa.DEFAULT_PRINT_OPTIONS

    F0 ¶
    Source

    F0 :: Register(REG_FPR | 0)

    F1 ¶
    Source

    F1 :: Register(REG_FPR | 1)

    F10 ¶
    Source

    F10 :: Register(REG_FPR | 10)

    F11 ¶
    Source

    F11 :: Register(REG_FPR | 11)

    F12 ¶
    Source

    F12 :: Register(REG_FPR | 12)

    F13 ¶
    Source

    F13 :: Register(REG_FPR | 13)

    F14 ¶
    Source

    F14 :: Register(REG_FPR | 14)

    F15 ¶
    Source

    F15 :: Register(REG_FPR | 15)

    F16 ¶
    Source

    F16 :: Register(REG_FPR | 16)

    F17 ¶
    Source

    F17 :: Register(REG_FPR | 17)

    F18 ¶
    Source

    F18 :: Register(REG_FPR | 18)

    F19 ¶
    Source

    F19 :: Register(REG_FPR | 19)

    F2 ¶
    Source

    F2 :: Register(REG_FPR | 2)

    F20 ¶
    Source

    F20 :: Register(REG_FPR | 20)

    F21 ¶
    Source

    F21 :: Register(REG_FPR | 21)

    F22 ¶
    Source

    F22 :: Register(REG_FPR | 22)

    F23 ¶
    Source

    F23 :: Register(REG_FPR | 23)

    F24 ¶
    Source

    F24 :: Register(REG_FPR | 24)

    F25 ¶
    Source

    F25 :: Register(REG_FPR | 25)

    F26 ¶
    Source

    F26 :: Register(REG_FPR | 26)

    F27 ¶
    Source

    F27 :: Register(REG_FPR | 27)

    F28 ¶
    Source

    F28 :: Register(REG_FPR | 28)

    F29 ¶
    Source

    F29 :: Register(REG_FPR | 29)

    F3 ¶
    Source

    F3 :: Register(REG_FPR | 3)

    F30 ¶
    Source

    F30 :: Register(REG_FPR | 30)

    F31 ¶
    Source

    F31 :: Register(REG_FPR | 31)

    F4 ¶
    Source

    F4 :: Register(REG_FPR | 4)

    F5 ¶
    Source

    F5 :: Register(REG_FPR | 5)

    F6 ¶
    Source

    F6 :: Register(REG_FPR | 6)

    F7 ¶
    Source

    F7 :: Register(REG_FPR | 7)

    F8 ¶
    Source

    F8 :: Register(REG_FPR | 8)

    F9 ¶
    Source

    F9 :: Register(REG_FPR | 9)

    FCR0 ¶
    Source

    FCR0 :: Register(REG_FCR | 0)
     

    FIR (FP implementation/revision)

    FCR25 ¶
    Source

    FCR25 :: Register(REG_FCR | 25)
     

    FCCR (FP condition codes, R2+)

    FCR26 ¶
    Source

    FCR26 :: Register(REG_FCR | 26)
     

    FEXR (FP exceptions, R2+)

    FCR28 ¶
    Source

    FCR28 :: Register(REG_FCR | 28)
     

    FENR (FP enables, R2+)

    FCR31 ¶
    Source

    FCR31 :: Register(REG_FCR | 31)
     

    FCSR (FP control/status)

    FP ¶
    Source

    FP :: Register(REG_GPR | 30)

    GP ¶
    Source

    GP :: Register(REG_GPR | 28)

    HI ¶
    Source

    HI :: Register(REG_HILO | 0)

    HI1 ¶
    Source

    HI1 :: Register(REG_HILO | 2)
     

    PS2 second hi/lo pair (R5900 has two MAC units).

    K0 ¶
    Source

    K0 :: Register(REG_GPR | 26)

    K1 ¶
    Source

    K1 :: Register(REG_GPR | 27)

    LABEL_UNDEFINED ¶
    Source

    LABEL_UNDEFINED: rexcode_isa.Label_Definition : isa.LABEL_UNDEFINED

    LO ¶
    Source

    LO :: Register(REG_HILO | 1)

    LO1 ¶
    Source

    LO1 :: Register(REG_HILO | 3)

    MASK_COP_RS ¶
    Source

    MASK_COP_RS: u32 : MASK_OPCODE | MASK_RS
     

    COP0/1/2 with fixed rs (rs selects the operation).

    MASK_FCC_BC ¶
    Source

    MASK_FCC_BC :: u32(0x001C0000)
     

    bits 20-18

    MASK_FCC_CC ¶
    Source

    MASK_FCC_CC :: u32(0x00000700)
     

    bits 10-8

    MASK_FI ¶
    Source

    MASK_FI: u32 : MASK_OPCODE | MASK_RS | u32(0x00030000)
     

    COP1 FI-format (BC1*): opcode + rs(=0x08) + tf/nd fixed bits (17-16).

    MASK_FR ¶
    Source

    MASK_FR: u32 : MASK_OPCODE | MASK_RS | MASK_FUNCT
     

    COP1 FR-format: opcode + fmt(rs) + funct.

    MASK_FUNCT ¶
    Source

    MASK_FUNCT :: u32(0x0000003F)
     

    bits 5-0

    MASK_I ¶
    Source

    MASK_I: u32 : MASK_OPCODE
     

    I-type fixed bits = opcode only.

    MASK_IMM16 ¶
    Source

    MASK_IMM16 :: u32(0x0000FFFF)
     

    bits 15-0

    MASK_IMM26 ¶
    Source

    MASK_IMM26 :: u32(0x03FFFFFF)
     

    bits 25-0

    MASK_J ¶
    Source

    MASK_J: u32 : MASK_OPCODE
     

    J-type fixed bits = opcode only.

    MASK_OPCODE ¶
    Source

    MASK_OPCODE :: u32(0xFC000000)
     

    Field masks (operand-bit positions, kept here so the future encoder can use them by name).

    MASK_R ¶
    Source

    MASK_R: u32 : MASK_OPCODE | MASK_FUNCT
     

    Static masks for common pattern combinations. R-type fixed bits = opcode (6) + funct (6).

    MASK_RD ¶
    Source

    MASK_RD :: u32(0x0000F800)
     

    bits 15-11

    MASK_REGIMM ¶
    Source

    MASK_REGIMM: u32 : MASK_OPCODE | MASK_RT
     

    REGIMM fixed bits = opcode + rt (the funct field for REGIMM).

    MASK_RS ¶
    Source

    MASK_RS :: u32(0x03E00000)
     

    bits 25-21

    MASK_RT ¶
    Source

    MASK_RT :: u32(0x001F0000)
     

    bits 20-16

    MASK_R_NOSH ¶
    Source

    MASK_R_NOSH: u32 : MASK_R | MASK_SHAMT
     

    R-type with fixed shamt=0 (most ADD/AND/etc.).

    MASK_SEL ¶
    Source

    MASK_SEL :: u32(0x00000007)
     

    bits 2-0

    MASK_SHAMT ¶
    Source

    MASK_SHAMT :: u32(0x000007C0)
     

    bits 10-6

    MAX_INST_SIZE ¶
    Source

    MAX_INST_SIZE :: 4
     

    Largest instruction we ever emit (MIPS is fixed at 4).

    NONE ¶
    Source

    NONE :: Register(0xFFFF)

    RA ¶
    Source

    RA :: Register(REG_GPR | 31)

    REG_CP0 ¶
    Source

    REG_CP0 :: 0x0400
     

    system control coprocessor 0 registers

    REG_CP2C ¶
    Source

    REG_CP2C :: 0x0600
     

    COP2 control register

    REG_CP2D ¶
    Source

    REG_CP2D :: 0x0500
     

    COP2 data register (GTE V/MAC/SXY; VU vf)

    REG_FCR ¶
    Source

    REG_FCR :: 0x0300
     

    FP control ($fcr0..$fcr31)

    REG_FPR ¶
    Source

    REG_FPR :: 0x0200
     

    $f0-$f31 floating-point

    REG_GPR ¶
    Source

    REG_GPR :: 0x0100
     

    $0-$31 general-purpose

    REG_HILO ¶
    Source

    REG_HILO :: 0x0700
     

    HI / LO multiply-divide accumulators

    REG_MSA ¶
    Source

    REG_MSA :: 0x0900
     

    MIPS SIMD Architecture $w0-$w31 (128-bit vectors)

    REG_NONE ¶
    Source

    REG_NONE :: 0x0000

    REG_VFPU ¶
    Source

    REG_VFPU :: 0x0800
     

    PSP Allegrex VFPU (matrix-organised)

    S0 ¶
    Source

    S0 :: Register(REG_GPR | 16)

    S1 ¶
    Source

    S1 :: Register(REG_GPR | 17)

    S2 ¶
    Source

    S2 :: Register(REG_GPR | 18)

    S3 ¶
    Source

    S3 :: Register(REG_GPR | 19)

    S4 ¶
    Source

    S4 :: Register(REG_GPR | 20)

    S5 ¶
    Source

    S5 :: Register(REG_GPR | 21)

    S6 ¶
    Source

    S6 :: Register(REG_GPR | 22)

    S7 ¶
    Source

    S7 :: Register(REG_GPR | 23)

    S8 ¶
    Source

    S8 :: Register(REG_GPR | 30)
     

    alias of FP per the canonical o32/n32 ABIs

    SP ¶
    Source

    SP :: Register(REG_GPR | 29)

    T0 ¶
    Source

    T0 :: Register(REG_GPR | 8)

    T1 ¶
    Source

    T1 :: Register(REG_GPR | 9)

    T2 ¶
    Source

    T2 :: Register(REG_GPR | 10)

    T3 ¶
    Source

    T3 :: Register(REG_GPR | 11)

    T4 ¶
    Source

    T4 :: Register(REG_GPR | 12)

    T5 ¶
    Source

    T5 :: Register(REG_GPR | 13)

    T6 ¶
    Source

    T6 :: Register(REG_GPR | 14)

    T7 ¶
    Source

    T7 :: Register(REG_GPR | 15)

    T8 ¶
    Source

    T8 :: Register(REG_GPR | 24)

    T9 ¶
    Source

    T9 :: Register(REG_GPR | 25)

    V0 ¶
    Source

    V0 :: Register(REG_GPR | 2)

    V1 ¶
    Source

    V1 :: Register(REG_GPR | 3)

    W0 ¶
    Source

    W0 :: Register(REG_MSA | 0)
     

    MSA $w0..$w31 constants for ergonomic use.

    W1 ¶
    Source

    W1 :: Register(REG_MSA | 1)

    W10 ¶
    Source

    W10 :: Register(REG_MSA | 10)

    W11 ¶
    Source

    W11 :: Register(REG_MSA | 11)

    W12 ¶
    Source

    W12 :: Register(REG_MSA | 12)

    W13 ¶
    Source

    W13 :: Register(REG_MSA | 13)

    W14 ¶
    Source

    W14 :: Register(REG_MSA | 14)

    W15 ¶
    Source

    W15 :: Register(REG_MSA | 15)

    W16 ¶
    Source

    W16 :: Register(REG_MSA | 16)

    W17 ¶
    Source

    W17 :: Register(REG_MSA | 17)

    W18 ¶
    Source

    W18 :: Register(REG_MSA | 18)

    W19 ¶
    Source

    W19 :: Register(REG_MSA | 19)

    W2 ¶
    Source

    W2 :: Register(REG_MSA | 2)

    W20 ¶
    Source

    W20 :: Register(REG_MSA | 20)

    W21 ¶
    Source

    W21 :: Register(REG_MSA | 21)

    W22 ¶
    Source

    W22 :: Register(REG_MSA | 22)

    W23 ¶
    Source

    W23 :: Register(REG_MSA | 23)

    W24 ¶
    Source

    W24 :: Register(REG_MSA | 24)

    W25 ¶
    Source

    W25 :: Register(REG_MSA | 25)

    W26 ¶
    Source

    W26 :: Register(REG_MSA | 26)

    W27 ¶
    Source

    W27 :: Register(REG_MSA | 27)

    W28 ¶
    Source

    W28 :: Register(REG_MSA | 28)

    W29 ¶
    Source

    W29 :: Register(REG_MSA | 29)

    W3 ¶
    Source

    W3 :: Register(REG_MSA | 3)

    W30 ¶
    Source

    W30 :: Register(REG_MSA | 30)

    W31 ¶
    Source

    W31 :: Register(REG_MSA | 31)

    W4 ¶
    Source

    W4 :: Register(REG_MSA | 4)

    W5 ¶
    Source

    W5 :: Register(REG_MSA | 5)

    W6 ¶
    Source

    W6 :: Register(REG_MSA | 6)

    W7 ¶
    Source

    W7 :: Register(REG_MSA | 7)

    W8 ¶
    Source

    W8 :: Register(REG_MSA | 8)

    W9 ¶
    Source

    W9 :: Register(REG_MSA | 9)

    ZERO ¶
    Source

    ZERO :: Register(REG_GPR | 0)

    Variables

    DECODE_ENTRIES ¶
    Source

    @(rodata)
DECODE_ENTRIES: []Decode_Entry = …

    DECODE_INDEX_COP1 ¶
    Source

    @(rodata)
DECODE_INDEX_COP1: []Decode_Index = …

    DECODE_INDEX_PRIMARY ¶
    Source

    @(rodata)
DECODE_INDEX_PRIMARY: []Decode_Index = …

    DECODE_INDEX_REGIMM ¶
    Source

    @(rodata)
DECODE_INDEX_REGIMM: []Decode_Index = …

    DECODE_INDEX_SPECIAL ¶
    Source

    @(rodata)
DECODE_INDEX_SPECIAL: []Decode_Index = …

    DECODE_INDEX_SPECIAL2 ¶
    Source

    @(rodata)
DECODE_INDEX_SPECIAL2: []Decode_Index = …

    DECODE_INDEX_SPECIAL3 ¶
    Source

    @(rodata)
DECODE_INDEX_SPECIAL3: []Decode_Index = …

    ENCODE_FORMS ¶
    Source

    @(rodata)
ENCODE_FORMS: []Encoding = …

    ENCODE_RUNS ¶
    Source

    @(rodata)
ENCODE_RUNS: []Encode_Run = …

    Procedures

    aprint ¶
    Source

    aprint :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
	allocator := context.allocator, 
) -> string {…}

    aprintln ¶
    Source

    aprintln :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
	allocator := context.allocator, 
) -> string {…}

    bprint ¶
    Source

    bprint :: proc(
	buf:          []u8, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

    bprintln ¶
    Source

    bprintln :: proc(
	buf:          []u8, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

    cp0_from_num ¶
    Source

    cp0_from_num :: proc "contextless" (num: u8) -> Register {…}

    cp2c_from_num ¶
    Source

    cp2c_from_num :: proc "contextless" (num: u8) -> Register {…}

    cp2d_from_num ¶
    Source

    cp2d_from_num :: proc "contextless" (num: u8) -> Register {…}

    decode ¶
    Source

    decode :: proc(
	data:         []u8, 
	relocs:       []Relocation, 
	instructions: ^[dynamic]Instruction, 
	inst_info:    ^[dynamic]Instruction_Info, 
	label_defs:   ^[dynamic]rexcode_isa.Label_Definition, 
	errors:       ^[dynamic]rexcode_isa.Error, 
	endianness:   Endianness = .BIG, 
) -> (byte_count: u32, ok: bool) {…}

    decode_estimate_instruction_count ¶
    Source

    decode_estimate_instruction_count :: proc "contextless" (data: []u8) -> int {…}
     

    Typical-case estimate of the instruction count for data.

    decode_max_instruction_count ¶
    Source

    decode_max_instruction_count :: proc "contextless" (data: []u8) -> int {…}
     

    Instruction-count ceiling for data (MIPS instructions are 4 bytes).

    decode_reserve ¶
    Source

    decode_reserve :: proc(instructions: ^[dynamic]Instruction, inst_info: ^[dynamic]Instruction_Info, label_defs: ^[dynamic]rexcode_isa.Label_Definition, data: []u8, exact: bool = false) {…}
     

    Pre-size the caller's decode output arrays for data (reserves on top of any existing elements; nil to skip; exact=true for the ceiling, else the estimate).

    emit_abs_d ¶
    Source

    emit_abs_d :: emit_abs_d_f_f

    emit_abs_d_f_f ¶
    Source

    emit_abs_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_abs_ps ¶
    Source

    emit_abs_ps :: emit_abs_ps_f_f

    emit_abs_ps_f_f ¶
    Source

    emit_abs_ps_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_abs_s ¶
    Source

    emit_abs_s :: emit_abs_s_f_f

    emit_abs_s_f_f ¶
    Source

    emit_abs_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_absq_s_ph ¶
    Source

    emit_absq_s_ph :: emit_absq_s_ph_r_r

    emit_absq_s_ph_r_r ¶
    Source

    emit_absq_s_ph_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_absq_s_w ¶
    Source

    emit_absq_s_w :: emit_absq_s_w_r_r

    emit_absq_s_w_r_r ¶
    Source

    emit_absq_s_w_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_add ¶
    Source

    emit_add :: emit_add_r_r_r

    emit_add_d ¶
    Source

    emit_add_d :: emit_add_d_f_f_f

    emit_add_d_f_f_f ¶
    Source

    emit_add_d_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_add_ps ¶
    Source

    emit_add_ps :: emit_add_ps_f_f_f

    emit_add_ps_f_f_f ¶
    Source

    emit_add_ps_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_add_r_r_r ¶
    Source

    emit_add_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_add_s ¶
    Source

    emit_add_s :: emit_add_s_f_f_f

    emit_add_s_f_f_f ¶
    Source

    emit_add_s_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_addi ¶
    Source

    emit_addi :: emit_addi_r_r_i16

    emit_addi_r_r_i16 ¶
    Source

    emit_addi_r_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_addiu ¶
    Source

    emit_addiu :: emit_addiu_r_r_i16

    emit_addiu_r_r_i16 ¶
    Source

    emit_addiu_r_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_addq_ph ¶
    Source

    emit_addq_ph :: emit_addq_ph_r_r_r

    emit_addq_ph_r_r_r ¶
    Source

    emit_addq_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_addq_s_ph ¶
    Source

    emit_addq_s_ph :: emit_addq_s_ph_r_r_r

    emit_addq_s_ph_r_r_r ¶
    Source

    emit_addq_s_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_addq_s_w ¶
    Source

    emit_addq_s_w :: emit_addq_s_w_r_r_r

    emit_addq_s_w_r_r_r ¶
    Source

    emit_addq_s_w_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_adds_s_b ¶
    Source

    emit_adds_s_b :: emit_adds_s_b_w_w_w

    emit_adds_s_b_w_w_w ¶
    Source

    emit_adds_s_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_adds_s_d ¶
    Source

    emit_adds_s_d :: emit_adds_s_d_w_w_w

    emit_adds_s_d_w_w_w ¶
    Source

    emit_adds_s_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_adds_s_h ¶
    Source

    emit_adds_s_h :: emit_adds_s_h_w_w_w

    emit_adds_s_h_w_w_w ¶
    Source

    emit_adds_s_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_adds_s_w ¶
    Source

    emit_adds_s_w :: emit_adds_s_w_w_w_w

    emit_adds_s_w_w_w_w ¶
    Source

    emit_adds_s_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_adds_u_b ¶
    Source

    emit_adds_u_b :: emit_adds_u_b_w_w_w

    emit_adds_u_b_w_w_w ¶
    Source

    emit_adds_u_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_adds_u_d ¶
    Source

    emit_adds_u_d :: emit_adds_u_d_w_w_w

    emit_adds_u_d_w_w_w ¶
    Source

    emit_adds_u_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_adds_u_h ¶
    Source

    emit_adds_u_h :: emit_adds_u_h_w_w_w

    emit_adds_u_h_w_w_w ¶
    Source

    emit_adds_u_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_adds_u_w ¶
    Source

    emit_adds_u_w :: emit_adds_u_w_w_w_w

    emit_adds_u_w_w_w_w ¶
    Source

    emit_adds_u_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_addsc ¶
    Source

    emit_addsc :: emit_addsc_r_r_r

    emit_addsc_r_r_r ¶
    Source

    emit_addsc_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_addu ¶
    Source

    emit_addu :: emit_addu_r_r_r

    emit_addu_ph ¶
    Source

    emit_addu_ph :: emit_addu_ph_r_r_r

    emit_addu_ph_r_r_r ¶
    Source

    emit_addu_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_addu_qb ¶
    Source

    emit_addu_qb :: emit_addu_qb_r_r_r

    emit_addu_qb_r_r_r ¶
    Source

    emit_addu_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_addu_r_r_r ¶
    Source

    emit_addu_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_addu_s_ph ¶
    Source

    emit_addu_s_ph :: emit_addu_s_ph_r_r_r

    emit_addu_s_ph_r_r_r ¶
    Source

    emit_addu_s_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_addu_s_qb ¶
    Source

    emit_addu_s_qb :: emit_addu_s_qb_r_r_r

    emit_addu_s_qb_r_r_r ¶
    Source

    emit_addu_s_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_addv_b ¶
    Source

    emit_addv_b :: emit_addv_b_w_w_w

    emit_addv_b_w_w_w ¶
    Source

    emit_addv_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_addv_d ¶
    Source

    emit_addv_d :: emit_addv_d_w_w_w

    emit_addv_d_w_w_w ¶
    Source

    emit_addv_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_addv_h ¶
    Source

    emit_addv_h :: emit_addv_h_w_w_w

    emit_addv_h_w_w_w ¶
    Source

    emit_addv_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_addv_w ¶
    Source

    emit_addv_w :: emit_addv_w_w_w_w

    emit_addv_w_w_w_w ¶
    Source

    emit_addv_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_addwc ¶
    Source

    emit_addwc :: emit_addwc_r_r_r

    emit_addwc_r_r_r ¶
    Source

    emit_addwc_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_align ¶
    Source

    emit_align :: emit_align_r_r_r_i5

    emit_align_r_r_r_i5 ¶
    Source

    emit_align_r_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR, imm: i64) {…}

    emit_aluipc ¶
    Source

    emit_aluipc :: emit_aluipc_r_i16

    emit_aluipc_r_i16 ¶
    Source

    emit_aluipc_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_and ¶
    Source

    emit_and :: emit_and_r_r_r

    emit_and_r_r_r ¶
    Source

    emit_and_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_and_v ¶
    Source

    emit_and_v :: emit_and_v_w_w_w

    emit_and_v_w_w_w ¶
    Source

    emit_and_v_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_andi ¶
    Source

    emit_andi :: emit_andi_r_r_u16

    emit_andi_b ¶
    Source

    emit_andi_b :: emit_andi_b_w_w_i5

    emit_andi_b_w_w_i5 ¶
    Source

    emit_andi_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_andi_r_r_u16 ¶
    Source

    emit_andi_r_r_u16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_aui ¶
    Source

    emit_aui :: emit_aui_r_r_u16

    emit_aui_r_r_u16 ¶
    Source

    emit_aui_r_r_u16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_auipc ¶
    Source

    emit_auipc :: emit_auipc_r_i16

    emit_auipc_r_i16 ¶
    Source

    emit_auipc_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_avsz3 ¶
    Source

    emit_avsz3 :: emit_avsz3_none

    emit_avsz3_none ¶
    Source

    emit_avsz3_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_avsz4 ¶
    Source

    emit_avsz4 :: emit_avsz4_none

    emit_avsz4_none ¶
    Source

    emit_avsz4_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_balc ¶
    Source

    emit_balc :: emit_balc_rel26

    emit_balc_rel26 ¶
    Source

    emit_balc_rel26 :: proc(instructions: ^[dynamic]Instruction, target: u32) {…}

    emit_bc ¶
    Source

    emit_bc :: emit_bc_rel26

    emit_bc1eqz ¶
    Source

    emit_bc1eqz :: emit_bc1eqz_f_rel

    emit_bc1eqz_f_rel ¶
    Source

    emit_bc1eqz_f_rel :: proc(instructions: ^[dynamic]Instruction, dst: FPR, target: u32) {…}

    emit_bc1f ¶
    Source

    emit_bc1f :: emit_bc1f_cc_rel

    emit_bc1f_cc_rel ¶
    Source

    emit_bc1f_cc_rel :: proc(instructions: ^[dynamic]Instruction, imm: i64, target: u32) {…}

    emit_bc1fl ¶
    Source

    emit_bc1fl :: emit_bc1fl_cc_rel

    emit_bc1fl_cc_rel ¶
    Source

    emit_bc1fl_cc_rel :: proc(instructions: ^[dynamic]Instruction, imm: i64, target: u32) {…}

    emit_bc1nez ¶
    Source

    emit_bc1nez :: emit_bc1nez_f_rel

    emit_bc1nez_f_rel ¶
    Source

    emit_bc1nez_f_rel :: proc(instructions: ^[dynamic]Instruction, dst: FPR, target: u32) {…}

    emit_bc1t ¶
    Source

    emit_bc1t :: emit_bc1t_cc_rel

    emit_bc1t_cc_rel ¶
    Source

    emit_bc1t_cc_rel :: proc(instructions: ^[dynamic]Instruction, imm: i64, target: u32) {…}

    emit_bc1tl ¶
    Source

    emit_bc1tl :: emit_bc1tl_cc_rel

    emit_bc1tl_cc_rel ¶
    Source

    emit_bc1tl_cc_rel :: proc(instructions: ^[dynamic]Instruction, imm: i64, target: u32) {…}

    emit_bc2eqz ¶
    Source

    emit_bc2eqz :: emit_bc2eqz_c2_rel

    emit_bc2eqz_c2_rel ¶
    Source

    emit_bc2eqz_c2_rel :: proc(instructions: ^[dynamic]Instruction, dst: GTE_DataReg, target: u32) {…}

    emit_bc2nez ¶
    Source

    emit_bc2nez :: emit_bc2nez_c2_rel

    emit_bc2nez_c2_rel ¶
    Source

    emit_bc2nez_c2_rel :: proc(instructions: ^[dynamic]Instruction, dst: GTE_DataReg, target: u32) {…}

    emit_bc_rel26 ¶
    Source

    emit_bc_rel26 :: proc(instructions: ^[dynamic]Instruction, target: u32) {…}

    emit_beq ¶
    Source

    emit_beq :: emit_beq_r_r_rel

    emit_beq_r_r_rel ¶
    Source

    emit_beq_r_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, target: u32) {…}

    emit_beqc ¶
    Source

    emit_beqc :: emit_beqc_r_r_rel

    emit_beqc_r_r_rel ¶
    Source

    emit_beqc_r_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, target: u32) {…}

    emit_beql ¶
    Source

    emit_beql :: emit_beql_r_r_rel

    emit_beql_r_r_rel ¶
    Source

    emit_beql_r_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, target: u32) {…}

    emit_beqzc ¶
    Source

    emit_beqzc :: emit_beqzc_r_rel21

    emit_beqzc_r_rel21 ¶
    Source

    emit_beqzc_r_rel21 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bgec ¶
    Source

    emit_bgec :: emit_bgec_r_r_rel

    emit_bgec_r_r_rel ¶
    Source

    emit_bgec_r_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, target: u32) {…}

    emit_bgeuc ¶
    Source

    emit_bgeuc :: emit_bgeuc_r_r_rel

    emit_bgeuc_r_r_rel ¶
    Source

    emit_bgeuc_r_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, target: u32) {…}

    emit_bgez ¶
    Source

    emit_bgez :: emit_bgez_r_rel

    emit_bgez_r_rel ¶
    Source

    emit_bgez_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bgezal ¶
    Source

    emit_bgezal :: emit_bgezal_r_rel

    emit_bgezal_r_rel ¶
    Source

    emit_bgezal_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bgezall ¶
    Source

    emit_bgezall :: emit_bgezall_r_rel

    emit_bgezall_r_rel ¶
    Source

    emit_bgezall_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bgezc ¶
    Source

    emit_bgezc :: emit_bgezc_r_rel

    emit_bgezc_r_rel ¶
    Source

    emit_bgezc_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bgezl ¶
    Source

    emit_bgezl :: emit_bgezl_r_rel

    emit_bgezl_r_rel ¶
    Source

    emit_bgezl_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bgtz ¶
    Source

    emit_bgtz :: emit_bgtz_r_rel

    emit_bgtz_r_rel ¶
    Source

    emit_bgtz_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bgtzc ¶
    Source

    emit_bgtzc :: emit_bgtzc_r_rel

    emit_bgtzc_r_rel ¶
    Source

    emit_bgtzc_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bgtzl ¶
    Source

    emit_bgtzl :: emit_bgtzl_r_rel

    emit_bgtzl_r_rel ¶
    Source

    emit_bgtzl_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bitrev ¶
    Source

    emit_bitrev :: emit_bitrev_r_r

    emit_bitrev_r_r ¶
    Source

    emit_bitrev_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_bitswap ¶
    Source

    emit_bitswap :: emit_bitswap_r_r

    emit_bitswap_r_r ¶
    Source

    emit_bitswap_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_blez ¶
    Source

    emit_blez :: emit_blez_r_rel

    emit_blez_r_rel ¶
    Source

    emit_blez_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_blezc ¶
    Source

    emit_blezc :: emit_blezc_r_rel

    emit_blezc_r_rel ¶
    Source

    emit_blezc_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_blezl ¶
    Source

    emit_blezl :: emit_blezl_r_rel

    emit_blezl_r_rel ¶
    Source

    emit_blezl_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bltc ¶
    Source

    emit_bltc :: emit_bltc_r_r_rel

    emit_bltc_r_r_rel ¶
    Source

    emit_bltc_r_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, target: u32) {…}

    emit_bltuc ¶
    Source

    emit_bltuc :: emit_bltuc_r_r_rel

    emit_bltuc_r_r_rel ¶
    Source

    emit_bltuc_r_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, target: u32) {…}

    emit_bltz ¶
    Source

    emit_bltz :: emit_bltz_r_rel

    emit_bltz_r_rel ¶
    Source

    emit_bltz_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bltzal ¶
    Source

    emit_bltzal :: emit_bltzal_r_rel

    emit_bltzal_r_rel ¶
    Source

    emit_bltzal_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bltzall ¶
    Source

    emit_bltzall :: emit_bltzall_r_rel

    emit_bltzall_r_rel ¶
    Source

    emit_bltzall_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bltzc ¶
    Source

    emit_bltzc :: emit_bltzc_r_rel

    emit_bltzc_r_rel ¶
    Source

    emit_bltzc_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bltzl ¶
    Source

    emit_bltzl :: emit_bltzl_r_rel

    emit_bltzl_r_rel ¶
    Source

    emit_bltzl_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bmnz_v ¶
    Source

    emit_bmnz_v :: emit_bmnz_v_w_w_w

    emit_bmnz_v_w_w_w ¶
    Source

    emit_bmnz_v_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_bmnzi_b ¶
    Source

    emit_bmnzi_b :: emit_bmnzi_b_w_w_i5

    emit_bmnzi_b_w_w_i5 ¶
    Source

    emit_bmnzi_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_bmz_v ¶
    Source

    emit_bmz_v :: emit_bmz_v_w_w_w

    emit_bmz_v_w_w_w ¶
    Source

    emit_bmz_v_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_bmzi_b ¶
    Source

    emit_bmzi_b :: emit_bmzi_b_w_w_i5

    emit_bmzi_b_w_w_i5 ¶
    Source

    emit_bmzi_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_bne ¶
    Source

    emit_bne :: emit_bne_r_r_rel

    emit_bne_r_r_rel ¶
    Source

    emit_bne_r_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, target: u32) {…}

    emit_bnec ¶
    Source

    emit_bnec :: emit_bnec_r_r_rel

    emit_bnec_r_r_rel ¶
    Source

    emit_bnec_r_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, target: u32) {…}

    emit_bnel ¶
    Source

    emit_bnel :: emit_bnel_r_r_rel

    emit_bnel_r_r_rel ¶
    Source

    emit_bnel_r_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, target: u32) {…}

    emit_bnezc ¶
    Source

    emit_bnezc :: emit_bnezc_r_rel21

    emit_bnezc_r_rel21 ¶
    Source

    emit_bnezc_r_rel21 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_bnz_b ¶
    Source

    emit_bnz_b :: emit_bnz_b_w_rel

    emit_bnz_b_w_rel ¶
    Source

    emit_bnz_b_w_rel :: proc(instructions: ^[dynamic]Instruction, dst: Register, target: u32) {…}

    emit_bnz_d ¶
    Source

    emit_bnz_d :: emit_bnz_d_w_rel

    emit_bnz_d_w_rel ¶
    Source

    emit_bnz_d_w_rel :: proc(instructions: ^[dynamic]Instruction, dst: Register, target: u32) {…}

    emit_bnz_h ¶
    Source

    emit_bnz_h :: emit_bnz_h_w_rel

    emit_bnz_h_w_rel ¶
    Source

    emit_bnz_h_w_rel :: proc(instructions: ^[dynamic]Instruction, dst: Register, target: u32) {…}

    emit_bnz_v ¶
    Source

    emit_bnz_v :: emit_bnz_v_w_rel

    emit_bnz_v_w_rel ¶
    Source

    emit_bnz_v_w_rel :: proc(instructions: ^[dynamic]Instruction, dst: Register, target: u32) {…}

    emit_bnz_w ¶
    Source

    emit_bnz_w :: emit_bnz_w_w_rel

    emit_bnz_w_w_rel ¶
    Source

    emit_bnz_w_w_rel :: proc(instructions: ^[dynamic]Instruction, dst: Register, target: u32) {…}

    emit_bposge32 ¶
    Source

    emit_bposge32 :: emit_bposge32_rel

    emit_bposge32_rel ¶
    Source

    emit_bposge32_rel :: proc(instructions: ^[dynamic]Instruction, target: u32) {…}

    emit_break ¶
    Source

    emit_break :: emit_break_i20

    emit_break_i20 ¶
    Source

    emit_break_i20 :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

    emit_bsel_v ¶
    Source

    emit_bsel_v :: emit_bsel_v_w_w_w

    emit_bsel_v_w_w_w ¶
    Source

    emit_bsel_v_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_bseli_b ¶
    Source

    emit_bseli_b :: emit_bseli_b_w_w_i5

    emit_bseli_b_w_w_i5 ¶
    Source

    emit_bseli_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_bvf ¶
    Source

    emit_bvf :: emit_bvf_i5_rel

    emit_bvf_i5_rel ¶
    Source

    emit_bvf_i5_rel :: proc(instructions: ^[dynamic]Instruction, imm: i64, target: u32) {…}

    emit_bvfl ¶
    Source

    emit_bvfl :: emit_bvfl_i5_rel

    emit_bvfl_i5_rel ¶
    Source

    emit_bvfl_i5_rel :: proc(instructions: ^[dynamic]Instruction, imm: i64, target: u32) {…}

    emit_bvt ¶
    Source

    emit_bvt :: emit_bvt_i5_rel

    emit_bvt_i5_rel ¶
    Source

    emit_bvt_i5_rel :: proc(instructions: ^[dynamic]Instruction, imm: i64, target: u32) {…}

    emit_bvtl ¶
    Source

    emit_bvtl :: emit_bvtl_i5_rel

    emit_bvtl_i5_rel ¶
    Source

    emit_bvtl_i5_rel :: proc(instructions: ^[dynamic]Instruction, imm: i64, target: u32) {…}

    emit_bz_b ¶
    Source

    emit_bz_b :: emit_bz_b_w_rel

    emit_bz_b_w_rel ¶
    Source

    emit_bz_b_w_rel :: proc(instructions: ^[dynamic]Instruction, dst: Register, target: u32) {…}

    emit_bz_d ¶
    Source

    emit_bz_d :: emit_bz_d_w_rel

    emit_bz_d_w_rel ¶
    Source

    emit_bz_d_w_rel :: proc(instructions: ^[dynamic]Instruction, dst: Register, target: u32) {…}

    emit_bz_h ¶
    Source

    emit_bz_h :: emit_bz_h_w_rel

    emit_bz_h_w_rel ¶
    Source

    emit_bz_h_w_rel :: proc(instructions: ^[dynamic]Instruction, dst: Register, target: u32) {…}

    emit_bz_v ¶
    Source

    emit_bz_v :: emit_bz_v_w_rel

    emit_bz_v_w_rel ¶
    Source

    emit_bz_v_w_rel :: proc(instructions: ^[dynamic]Instruction, dst: Register, target: u32) {…}

    emit_bz_w ¶
    Source

    emit_bz_w :: emit_bz_w_w_rel

    emit_bz_w_w_rel ¶
    Source

    emit_bz_w_w_rel :: proc(instructions: ^[dynamic]Instruction, dst: Register, target: u32) {…}

    emit_c_eq_d ¶
    Source

    emit_c_eq_d :: emit_c_eq_d_f_f_cc

    emit_c_eq_d_f_f_cc ¶
    Source

    emit_c_eq_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_eq_ps ¶
    Source

    emit_c_eq_ps :: emit_c_eq_ps_f_f_cc

    emit_c_eq_ps_f_f_cc ¶
    Source

    emit_c_eq_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_eq_s ¶
    Source

    emit_c_eq_s :: emit_c_eq_s_f_f_cc

    emit_c_eq_s_f_f_cc ¶
    Source

    emit_c_eq_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_f_d ¶
    Source

    emit_c_f_d :: emit_c_f_d_f_f_cc

    emit_c_f_d_f_f_cc ¶
    Source

    emit_c_f_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_f_ps ¶
    Source

    emit_c_f_ps :: emit_c_f_ps_f_f_cc

    emit_c_f_ps_f_f_cc ¶
    Source

    emit_c_f_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_f_s ¶
    Source

    emit_c_f_s :: emit_c_f_s_f_f_cc

    emit_c_f_s_f_f_cc ¶
    Source

    emit_c_f_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_le_d ¶
    Source

    emit_c_le_d :: emit_c_le_d_f_f_cc

    emit_c_le_d_f_f_cc ¶
    Source

    emit_c_le_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_le_ps ¶
    Source

    emit_c_le_ps :: emit_c_le_ps_f_f_cc

    emit_c_le_ps_f_f_cc ¶
    Source

    emit_c_le_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_le_s ¶
    Source

    emit_c_le_s :: emit_c_le_s_f_f_cc

    emit_c_le_s_f_f_cc ¶
    Source

    emit_c_le_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_lt_d ¶
    Source

    emit_c_lt_d :: emit_c_lt_d_f_f_cc

    emit_c_lt_d_f_f_cc ¶
    Source

    emit_c_lt_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_lt_ps ¶
    Source

    emit_c_lt_ps :: emit_c_lt_ps_f_f_cc

    emit_c_lt_ps_f_f_cc ¶
    Source

    emit_c_lt_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_lt_s ¶
    Source

    emit_c_lt_s :: emit_c_lt_s_f_f_cc

    emit_c_lt_s_f_f_cc ¶
    Source

    emit_c_lt_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_nge_d ¶
    Source

    emit_c_nge_d :: emit_c_nge_d_f_f_cc

    emit_c_nge_d_f_f_cc ¶
    Source

    emit_c_nge_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_nge_ps ¶
    Source

    emit_c_nge_ps :: emit_c_nge_ps_f_f_cc

    emit_c_nge_ps_f_f_cc ¶
    Source

    emit_c_nge_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_nge_s ¶
    Source

    emit_c_nge_s :: emit_c_nge_s_f_f_cc

    emit_c_nge_s_f_f_cc ¶
    Source

    emit_c_nge_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ngl_d ¶
    Source

    emit_c_ngl_d :: emit_c_ngl_d_f_f_cc

    emit_c_ngl_d_f_f_cc ¶
    Source

    emit_c_ngl_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ngl_ps ¶
    Source

    emit_c_ngl_ps :: emit_c_ngl_ps_f_f_cc

    emit_c_ngl_ps_f_f_cc ¶
    Source

    emit_c_ngl_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ngl_s ¶
    Source

    emit_c_ngl_s :: emit_c_ngl_s_f_f_cc

    emit_c_ngl_s_f_f_cc ¶
    Source

    emit_c_ngl_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ngle_d ¶
    Source

    emit_c_ngle_d :: emit_c_ngle_d_f_f_cc

    emit_c_ngle_d_f_f_cc ¶
    Source

    emit_c_ngle_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ngle_ps ¶
    Source

    emit_c_ngle_ps :: emit_c_ngle_ps_f_f_cc

    emit_c_ngle_ps_f_f_cc ¶
    Source

    emit_c_ngle_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ngle_s ¶
    Source

    emit_c_ngle_s :: emit_c_ngle_s_f_f_cc

    emit_c_ngle_s_f_f_cc ¶
    Source

    emit_c_ngle_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ngt_d ¶
    Source

    emit_c_ngt_d :: emit_c_ngt_d_f_f_cc

    emit_c_ngt_d_f_f_cc ¶
    Source

    emit_c_ngt_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ngt_ps ¶
    Source

    emit_c_ngt_ps :: emit_c_ngt_ps_f_f_cc

    emit_c_ngt_ps_f_f_cc ¶
    Source

    emit_c_ngt_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ngt_s ¶
    Source

    emit_c_ngt_s :: emit_c_ngt_s_f_f_cc

    emit_c_ngt_s_f_f_cc ¶
    Source

    emit_c_ngt_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ole_d ¶
    Source

    emit_c_ole_d :: emit_c_ole_d_f_f_cc

    emit_c_ole_d_f_f_cc ¶
    Source

    emit_c_ole_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ole_ps ¶
    Source

    emit_c_ole_ps :: emit_c_ole_ps_f_f_cc

    emit_c_ole_ps_f_f_cc ¶
    Source

    emit_c_ole_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ole_s ¶
    Source

    emit_c_ole_s :: emit_c_ole_s_f_f_cc

    emit_c_ole_s_f_f_cc ¶
    Source

    emit_c_ole_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_olt_d ¶
    Source

    emit_c_olt_d :: emit_c_olt_d_f_f_cc

    emit_c_olt_d_f_f_cc ¶
    Source

    emit_c_olt_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_olt_ps ¶
    Source

    emit_c_olt_ps :: emit_c_olt_ps_f_f_cc

    emit_c_olt_ps_f_f_cc ¶
    Source

    emit_c_olt_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_olt_s ¶
    Source

    emit_c_olt_s :: emit_c_olt_s_f_f_cc

    emit_c_olt_s_f_f_cc ¶
    Source

    emit_c_olt_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_seq_d ¶
    Source

    emit_c_seq_d :: emit_c_seq_d_f_f_cc

    emit_c_seq_d_f_f_cc ¶
    Source

    emit_c_seq_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_seq_ps ¶
    Source

    emit_c_seq_ps :: emit_c_seq_ps_f_f_cc

    emit_c_seq_ps_f_f_cc ¶
    Source

    emit_c_seq_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_seq_s ¶
    Source

    emit_c_seq_s :: emit_c_seq_s_f_f_cc

    emit_c_seq_s_f_f_cc ¶
    Source

    emit_c_seq_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_sf_d ¶
    Source

    emit_c_sf_d :: emit_c_sf_d_f_f_cc

    emit_c_sf_d_f_f_cc ¶
    Source

    emit_c_sf_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_sf_ps ¶
    Source

    emit_c_sf_ps :: emit_c_sf_ps_f_f_cc

    emit_c_sf_ps_f_f_cc ¶
    Source

    emit_c_sf_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_sf_s ¶
    Source

    emit_c_sf_s :: emit_c_sf_s_f_f_cc

    emit_c_sf_s_f_f_cc ¶
    Source

    emit_c_sf_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ueq_d ¶
    Source

    emit_c_ueq_d :: emit_c_ueq_d_f_f_cc

    emit_c_ueq_d_f_f_cc ¶
    Source

    emit_c_ueq_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ueq_ps ¶
    Source

    emit_c_ueq_ps :: emit_c_ueq_ps_f_f_cc

    emit_c_ueq_ps_f_f_cc ¶
    Source

    emit_c_ueq_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ueq_s ¶
    Source

    emit_c_ueq_s :: emit_c_ueq_s_f_f_cc

    emit_c_ueq_s_f_f_cc ¶
    Source

    emit_c_ueq_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ule_d ¶
    Source

    emit_c_ule_d :: emit_c_ule_d_f_f_cc

    emit_c_ule_d_f_f_cc ¶
    Source

    emit_c_ule_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ule_ps ¶
    Source

    emit_c_ule_ps :: emit_c_ule_ps_f_f_cc

    emit_c_ule_ps_f_f_cc ¶
    Source

    emit_c_ule_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ule_s ¶
    Source

    emit_c_ule_s :: emit_c_ule_s_f_f_cc

    emit_c_ule_s_f_f_cc ¶
    Source

    emit_c_ule_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ult_d ¶
    Source

    emit_c_ult_d :: emit_c_ult_d_f_f_cc

    emit_c_ult_d_f_f_cc ¶
    Source

    emit_c_ult_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ult_ps ¶
    Source

    emit_c_ult_ps :: emit_c_ult_ps_f_f_cc

    emit_c_ult_ps_f_f_cc ¶
    Source

    emit_c_ult_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_ult_s ¶
    Source

    emit_c_ult_s :: emit_c_ult_s_f_f_cc

    emit_c_ult_s_f_f_cc ¶
    Source

    emit_c_ult_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_un_d ¶
    Source

    emit_c_un_d :: emit_c_un_d_f_f_cc

    emit_c_un_d_f_f_cc ¶
    Source

    emit_c_un_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_un_ps ¶
    Source

    emit_c_un_ps :: emit_c_un_ps_f_f_cc

    emit_c_un_ps_f_f_cc ¶
    Source

    emit_c_un_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_c_un_s ¶
    Source

    emit_c_un_s :: emit_c_un_s_f_f_cc

    emit_c_un_s_f_f_cc ¶
    Source

    emit_c_un_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_cache ¶
    Source

    emit_cache :: emit_cache_i5_m

    emit_cache_i5_m ¶
    Source

    emit_cache_i5_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) {…}

    emit_cc ¶
    Source

    emit_cc :: emit_cc_none

    emit_cc_none ¶
    Source

    emit_cc_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_cdp ¶
    Source

    emit_cdp :: emit_cdp_none

    emit_cdp_none ¶
    Source

    emit_cdp_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_ceil_l_d ¶
    Source

    emit_ceil_l_d :: emit_ceil_l_d_f_f

    emit_ceil_l_d_f_f ¶
    Source

    emit_ceil_l_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_ceil_l_s ¶
    Source

    emit_ceil_l_s :: emit_ceil_l_s_f_f

    emit_ceil_l_s_f_f ¶
    Source

    emit_ceil_l_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_ceil_w_d ¶
    Source

    emit_ceil_w_d :: emit_ceil_w_d_f_f

    emit_ceil_w_d_f_f ¶
    Source

    emit_ceil_w_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_ceil_w_s ¶
    Source

    emit_ceil_w_s :: emit_ceil_w_s_f_f

    emit_ceil_w_s_f_f ¶
    Source

    emit_ceil_w_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_ceq_b ¶
    Source

    emit_ceq_b :: emit_ceq_b_w_w_w

    emit_ceq_b_w_w_w ¶
    Source

    emit_ceq_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_ceq_d ¶
    Source

    emit_ceq_d :: emit_ceq_d_w_w_w

    emit_ceq_d_w_w_w ¶
    Source

    emit_ceq_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_ceq_h ¶
    Source

    emit_ceq_h :: emit_ceq_h_w_w_w

    emit_ceq_h_w_w_w ¶
    Source

    emit_ceq_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_ceq_w ¶
    Source

    emit_ceq_w :: emit_ceq_w_w_w_w

    emit_ceq_w_w_w_w ¶
    Source

    emit_ceq_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_cfc1 ¶
    Source

    emit_cfc1 :: emit_cfc1_r_fcr

    emit_cfc1_r_fcr ¶
    Source

    emit_cfc1_r_fcr :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: Register) {…}

    emit_cfc2 ¶
    Source

    emit_cfc2 :: emit_cfc2_r_c2c

    emit_cfc2_r_c2c ¶
    Source

    emit_cfc2_r_c2c :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GTE_CtrlReg) {…}

    emit_cle_s_b ¶
    Source

    emit_cle_s_b :: emit_cle_s_b_w_w_w

    emit_cle_s_b_w_w_w ¶
    Source

    emit_cle_s_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_cle_s_d ¶
    Source

    emit_cle_s_d :: emit_cle_s_d_w_w_w

    emit_cle_s_d_w_w_w ¶
    Source

    emit_cle_s_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_cle_s_h ¶
    Source

    emit_cle_s_h :: emit_cle_s_h_w_w_w

    emit_cle_s_h_w_w_w ¶
    Source

    emit_cle_s_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_cle_s_w ¶
    Source

    emit_cle_s_w :: emit_cle_s_w_w_w_w

    emit_cle_s_w_w_w_w ¶
    Source

    emit_cle_s_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_cle_u_b ¶
    Source

    emit_cle_u_b :: emit_cle_u_b_w_w_w

    emit_cle_u_b_w_w_w ¶
    Source

    emit_cle_u_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_cle_u_d ¶
    Source

    emit_cle_u_d :: emit_cle_u_d_w_w_w

    emit_cle_u_d_w_w_w ¶
    Source

    emit_cle_u_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_cle_u_h ¶
    Source

    emit_cle_u_h :: emit_cle_u_h_w_w_w

    emit_cle_u_h_w_w_w ¶
    Source

    emit_cle_u_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_cle_u_w ¶
    Source

    emit_cle_u_w :: emit_cle_u_w_w_w_w

    emit_cle_u_w_w_w_w ¶
    Source

    emit_cle_u_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_clo ¶
    Source

    emit_clo :: emit_clo_r_r

    emit_clo_r_r ¶
    Source

    emit_clo_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_clt_s_b ¶
    Source

    emit_clt_s_b :: emit_clt_s_b_w_w_w

    emit_clt_s_b_w_w_w ¶
    Source

    emit_clt_s_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_clt_s_d ¶
    Source

    emit_clt_s_d :: emit_clt_s_d_w_w_w

    emit_clt_s_d_w_w_w ¶
    Source

    emit_clt_s_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_clt_s_h ¶
    Source

    emit_clt_s_h :: emit_clt_s_h_w_w_w

    emit_clt_s_h_w_w_w ¶
    Source

    emit_clt_s_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_clt_s_w ¶
    Source

    emit_clt_s_w :: emit_clt_s_w_w_w_w

    emit_clt_s_w_w_w_w ¶
    Source

    emit_clt_s_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_clt_u_b ¶
    Source

    emit_clt_u_b :: emit_clt_u_b_w_w_w

    emit_clt_u_b_w_w_w ¶
    Source

    emit_clt_u_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_clt_u_d ¶
    Source

    emit_clt_u_d :: emit_clt_u_d_w_w_w

    emit_clt_u_d_w_w_w ¶
    Source

    emit_clt_u_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_clt_u_h ¶
    Source

    emit_clt_u_h :: emit_clt_u_h_w_w_w

    emit_clt_u_h_w_w_w ¶
    Source

    emit_clt_u_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_clt_u_w ¶
    Source

    emit_clt_u_w :: emit_clt_u_w_w_w_w

    emit_clt_u_w_w_w_w ¶
    Source

    emit_clt_u_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_clz ¶
    Source

    emit_clz :: emit_clz_r_r

    emit_clz_r_r ¶
    Source

    emit_clz_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_cmp_eq_ph ¶
    Source

    emit_cmp_eq_ph :: emit_cmp_eq_ph_r_r

    emit_cmp_eq_ph_r_r ¶
    Source

    emit_cmp_eq_ph_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_cmp_le_ph ¶
    Source

    emit_cmp_le_ph :: emit_cmp_le_ph_r_r

    emit_cmp_le_ph_r_r ¶
    Source

    emit_cmp_le_ph_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_cmp_lt_ph ¶
    Source

    emit_cmp_lt_ph :: emit_cmp_lt_ph_r_r

    emit_cmp_lt_ph_r_r ¶
    Source

    emit_cmp_lt_ph_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_cmpgu_eq_qb ¶
    Source

    emit_cmpgu_eq_qb :: emit_cmpgu_eq_qb_r_r_r

    emit_cmpgu_eq_qb_r_r_r ¶
    Source

    emit_cmpgu_eq_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_cmpgu_le_qb ¶
    Source

    emit_cmpgu_le_qb :: emit_cmpgu_le_qb_r_r_r

    emit_cmpgu_le_qb_r_r_r ¶
    Source

    emit_cmpgu_le_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_cmpgu_lt_qb ¶
    Source

    emit_cmpgu_lt_qb :: emit_cmpgu_lt_qb_r_r_r

    emit_cmpgu_lt_qb_r_r_r ¶
    Source

    emit_cmpgu_lt_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_cmpu_eq_qb ¶
    Source

    emit_cmpu_eq_qb :: emit_cmpu_eq_qb_r_r

    emit_cmpu_eq_qb_r_r ¶
    Source

    emit_cmpu_eq_qb_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_cmpu_le_qb ¶
    Source

    emit_cmpu_le_qb :: emit_cmpu_le_qb_r_r

    emit_cmpu_le_qb_r_r ¶
    Source

    emit_cmpu_le_qb_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_cmpu_lt_qb ¶
    Source

    emit_cmpu_lt_qb :: emit_cmpu_lt_qb_r_r

    emit_cmpu_lt_qb_r_r ¶
    Source

    emit_cmpu_lt_qb_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_copy_s_b ¶
    Source

    emit_copy_s_b :: emit_copy_s_b_r_w_i5

    emit_copy_s_b_r_w_i5 ¶
    Source

    emit_copy_s_b_r_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: Register, imm: i64) {…}

    emit_copy_s_h ¶
    Source

    emit_copy_s_h :: emit_copy_s_h_r_w_i5

    emit_copy_s_h_r_w_i5 ¶
    Source

    emit_copy_s_h_r_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: Register, imm: i64) {…}

    emit_copy_s_w ¶
    Source

    emit_copy_s_w :: emit_copy_s_w_r_w_i5

    emit_copy_s_w_r_w_i5 ¶
    Source

    emit_copy_s_w_r_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: Register, imm: i64) {…}

    emit_copy_u_b ¶
    Source

    emit_copy_u_b :: emit_copy_u_b_r_w_i5

    emit_copy_u_b_r_w_i5 ¶
    Source

    emit_copy_u_b_r_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: Register, imm: i64) {…}

    emit_copy_u_h ¶
    Source

    emit_copy_u_h :: emit_copy_u_h_r_w_i5

    emit_copy_u_h_r_w_i5 ¶
    Source

    emit_copy_u_h_r_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: Register, imm: i64) {…}

    emit_copy_u_w ¶
    Source

    emit_copy_u_w :: emit_copy_u_w_r_w_i5

    emit_copy_u_w_r_w_i5 ¶
    Source

    emit_copy_u_w_r_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: Register, imm: i64) {…}

    emit_crc32b ¶
    Source

    emit_crc32b :: emit_crc32b_r_r

    emit_crc32b_r_r ¶
    Source

    emit_crc32b_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_crc32cb ¶
    Source

    emit_crc32cb :: emit_crc32cb_r_r

    emit_crc32cb_r_r ¶
    Source

    emit_crc32cb_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_crc32cd ¶
    Source

    emit_crc32cd :: emit_crc32cd_r_r

    emit_crc32cd_r_r ¶
    Source

    emit_crc32cd_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_crc32ch ¶
    Source

    emit_crc32ch :: emit_crc32ch_r_r

    emit_crc32ch_r_r ¶
    Source

    emit_crc32ch_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_crc32cw ¶
    Source

    emit_crc32cw :: emit_crc32cw_r_r

    emit_crc32cw_r_r ¶
    Source

    emit_crc32cw_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_crc32d ¶
    Source

    emit_crc32d :: emit_crc32d_r_r

    emit_crc32d_r_r ¶
    Source

    emit_crc32d_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_crc32h ¶
    Source

    emit_crc32h :: emit_crc32h_r_r

    emit_crc32h_r_r ¶
    Source

    emit_crc32h_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_crc32w ¶
    Source

    emit_crc32w :: emit_crc32w_r_r

    emit_crc32w_r_r ¶
    Source

    emit_crc32w_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_ctc1 ¶
    Source

    emit_ctc1 :: emit_ctc1_r_fcr

    emit_ctc1_r_fcr ¶
    Source

    emit_ctc1_r_fcr :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: Register) {…}

    emit_ctc2 ¶
    Source

    emit_ctc2 :: emit_ctc2_r_c2c

    emit_ctc2_r_c2c ¶
    Source

    emit_ctc2_r_c2c :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GTE_CtrlReg) {…}

    emit_cvt_d_l ¶
    Source

    emit_cvt_d_l :: emit_cvt_d_l_f_f

    emit_cvt_d_l_f_f ¶
    Source

    emit_cvt_d_l_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_cvt_d_s ¶
    Source

    emit_cvt_d_s :: emit_cvt_d_s_f_f

    emit_cvt_d_s_f_f ¶
    Source

    emit_cvt_d_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_cvt_d_w ¶
    Source

    emit_cvt_d_w :: emit_cvt_d_w_f_f

    emit_cvt_d_w_f_f ¶
    Source

    emit_cvt_d_w_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_cvt_l_d ¶
    Source

    emit_cvt_l_d :: emit_cvt_l_d_f_f

    emit_cvt_l_d_f_f ¶
    Source

    emit_cvt_l_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_cvt_l_s ¶
    Source

    emit_cvt_l_s :: emit_cvt_l_s_f_f

    emit_cvt_l_s_f_f ¶
    Source

    emit_cvt_l_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_cvt_ps_s ¶
    Source

    emit_cvt_ps_s :: emit_cvt_ps_s_f_f_f

    emit_cvt_ps_s_f_f_f ¶
    Source

    emit_cvt_ps_s_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_cvt_s_d ¶
    Source

    emit_cvt_s_d :: emit_cvt_s_d_f_f

    emit_cvt_s_d_f_f ¶
    Source

    emit_cvt_s_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_cvt_s_l ¶
    Source

    emit_cvt_s_l :: emit_cvt_s_l_f_f

    emit_cvt_s_l_f_f ¶
    Source

    emit_cvt_s_l_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_cvt_s_pl ¶
    Source

    emit_cvt_s_pl :: emit_cvt_s_pl_f_f

    emit_cvt_s_pl_f_f ¶
    Source

    emit_cvt_s_pl_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_cvt_s_pu ¶
    Source

    emit_cvt_s_pu :: emit_cvt_s_pu_f_f

    emit_cvt_s_pu_f_f ¶
    Source

    emit_cvt_s_pu_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_cvt_s_w ¶
    Source

    emit_cvt_s_w :: emit_cvt_s_w_f_f

    emit_cvt_s_w_f_f ¶
    Source

    emit_cvt_s_w_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_cvt_w_d ¶
    Source

    emit_cvt_w_d :: emit_cvt_w_d_f_f

    emit_cvt_w_d_f_f ¶
    Source

    emit_cvt_w_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_cvt_w_s ¶
    Source

    emit_cvt_w_s :: emit_cvt_w_s_f_f

    emit_cvt_w_s_f_f ¶
    Source

    emit_cvt_w_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_dadd ¶
    Source

    emit_dadd :: emit_dadd_r_r_r

    emit_dadd_r_r_r ¶
    Source

    emit_dadd_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_daddi ¶
    Source

    emit_daddi :: emit_daddi_r_r_i16

    emit_daddi_r_r_i16 ¶
    Source

    emit_daddi_r_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_daddiu ¶
    Source

    emit_daddiu :: emit_daddiu_r_r_i16

    emit_daddiu_r_r_i16 ¶
    Source

    emit_daddiu_r_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_daddu ¶
    Source

    emit_daddu :: emit_daddu_r_r_r

    emit_daddu_r_r_r ¶
    Source

    emit_daddu_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dahi ¶
    Source

    emit_dahi :: emit_dahi_r_u16

    emit_dahi_r_u16 ¶
    Source

    emit_dahi_r_u16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_dalign ¶
    Source

    emit_dalign :: emit_dalign_r_r_r_i5

    emit_dalign_r_r_r_i5 ¶
    Source

    emit_dalign_r_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR, imm: i64) {…}

    emit_dati ¶
    Source

    emit_dati :: emit_dati_r_u16

    emit_dati_r_u16 ¶
    Source

    emit_dati_r_u16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_daui ¶
    Source

    emit_daui :: emit_daui_r_r_u16

    emit_daui_r_r_u16 ¶
    Source

    emit_daui_r_r_u16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_dbitswap ¶
    Source

    emit_dbitswap :: emit_dbitswap_r_r

    emit_dbitswap_r_r ¶
    Source

    emit_dbitswap_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_dclo ¶
    Source

    emit_dclo :: emit_dclo_r_r

    emit_dclo_r_r ¶
    Source

    emit_dclo_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_dclz ¶
    Source

    emit_dclz :: emit_dclz_r_r

    emit_dclz_r_r ¶
    Source

    emit_dclz_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_dcpl ¶
    Source

    emit_dcpl :: emit_dcpl_none

    emit_dcpl_none ¶
    Source

    emit_dcpl_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_ddiv ¶
    Source

    emit_ddiv :: emit_ddiv_r_r

    emit_ddiv_r6 ¶
    Source

    emit_ddiv_r6 :: emit_ddiv_r6_r_r_r

    emit_ddiv_r6_r_r_r ¶
    Source

    emit_ddiv_r6_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_ddiv_r_r ¶
    Source

    emit_ddiv_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_ddivu ¶
    Source

    emit_ddivu :: emit_ddivu_r_r

    emit_ddivu_r6 ¶
    Source

    emit_ddivu_r6 :: emit_ddivu_r6_r_r_r

    emit_ddivu_r6_r_r_r ¶
    Source

    emit_ddivu_r6_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_ddivu_r_r ¶
    Source

    emit_ddivu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_deret ¶
    Source

    emit_deret :: emit_deret_none

    emit_deret_none ¶
    Source

    emit_deret_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_dext ¶
    Source

    emit_dext :: emit_dext_r_r_i5_i5

    emit_dext_r_r_i5_i5 ¶
    Source

    emit_dext_r_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64, imm2: i64) {…}

    emit_dextm ¶
    Source

    emit_dextm :: emit_dextm_r_r_i5_i5

    emit_dextm_r_r_i5_i5 ¶
    Source

    emit_dextm_r_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64, imm2: i64) {…}

    emit_dextu ¶
    Source

    emit_dextu :: emit_dextu_r_r_i5_i5

    emit_dextu_r_r_i5_i5 ¶
    Source

    emit_dextu_r_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64, imm2: i64) {…}

    emit_di ¶
    Source

    emit_di :: emit_di_r

    emit_di_r ¶
    Source

    emit_di_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_dins ¶
    Source

    emit_dins :: emit_dins_r_r_i5_i5

    emit_dins_r_r_i5_i5 ¶
    Source

    emit_dins_r_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64, imm2: i64) {…}

    emit_dinsm ¶
    Source

    emit_dinsm :: emit_dinsm_r_r_i5_i5

    emit_dinsm_r_r_i5_i5 ¶
    Source

    emit_dinsm_r_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64, imm2: i64) {…}

    emit_dinsu ¶
    Source

    emit_dinsu :: emit_dinsu_r_r_i5_i5

    emit_dinsu_r_r_i5_i5 ¶
    Source

    emit_dinsu_r_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64, imm2: i64) {…}

    emit_div ¶
    Source

    emit_div :: emit_div_r_r

    emit_div1 ¶
    Source

    emit_div1 :: emit_div1_r_r

    emit_div1_r_r ¶
    Source

    emit_div1_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_div_d ¶
    Source

    emit_div_d :: emit_div_d_f_f_f

    emit_div_d_f_f_f ¶
    Source

    emit_div_d_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_div_r_r ¶
    Source

    emit_div_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_div_s ¶
    Source

    emit_div_s :: emit_div_s_f_f_f

    emit_div_s_b ¶
    Source

    emit_div_s_b :: emit_div_s_b_w_w_w

    emit_div_s_b_w_w_w ¶
    Source

    emit_div_s_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_div_s_d ¶
    Source

    emit_div_s_d :: emit_div_s_d_w_w_w

    emit_div_s_d_w_w_w ¶
    Source

    emit_div_s_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_div_s_f_f_f ¶
    Source

    emit_div_s_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_div_s_h ¶
    Source

    emit_div_s_h :: emit_div_s_h_w_w_w

    emit_div_s_h_w_w_w ¶
    Source

    emit_div_s_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_div_s_w ¶
    Source

    emit_div_s_w :: emit_div_s_w_w_w_w

    emit_div_s_w_w_w_w ¶
    Source

    emit_div_s_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_div_u_b ¶
    Source

    emit_div_u_b :: emit_div_u_b_w_w_w

    emit_div_u_b_w_w_w ¶
    Source

    emit_div_u_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_div_u_d ¶
    Source

    emit_div_u_d :: emit_div_u_d_w_w_w

    emit_div_u_d_w_w_w ¶
    Source

    emit_div_u_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_div_u_h ¶
    Source

    emit_div_u_h :: emit_div_u_h_w_w_w

    emit_div_u_h_w_w_w ¶
    Source

    emit_div_u_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_div_u_w ¶
    Source

    emit_div_u_w :: emit_div_u_w_w_w_w

    emit_div_u_w_w_w_w ¶
    Source

    emit_div_u_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_divu ¶
    Source

    emit_divu :: emit_divu_r_r

    emit_divu1 ¶
    Source

    emit_divu1 :: emit_divu1_r_r

    emit_divu1_r_r ¶
    Source

    emit_divu1_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_divu_r_r ¶
    Source

    emit_divu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_dlsa ¶
    Source

    emit_dlsa :: emit_dlsa_r_r_r_i5

    emit_dlsa_r_r_r_i5 ¶
    Source

    emit_dlsa_r_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR, imm: i64) {…}

    emit_dmfc0 ¶
    Source

    emit_dmfc0 :: emit_dmfc0_r_c0_sel

    emit_dmfc0_r_c0_sel ¶
    Source

    emit_dmfc0_r_c0_sel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: CP0_Reg, imm: i64) {…}

    emit_dmfc1 ¶
    Source

    emit_dmfc1 :: emit_dmfc1_r_f

    emit_dmfc1_r_f ¶
    Source

    emit_dmfc1_r_f :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: FPR) {…}

    emit_dmod ¶
    Source

    emit_dmod :: emit_dmod_r_r_r

    emit_dmod_r_r_r ¶
    Source

    emit_dmod_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dmodu ¶
    Source

    emit_dmodu :: emit_dmodu_r_r_r

    emit_dmodu_r_r_r ¶
    Source

    emit_dmodu_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dmtc0 ¶
    Source

    emit_dmtc0 :: emit_dmtc0_r_c0_sel

    emit_dmtc0_r_c0_sel ¶
    Source

    emit_dmtc0_r_c0_sel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: CP0_Reg, imm: i64) {…}

    emit_dmtc1 ¶
    Source

    emit_dmtc1 :: emit_dmtc1_r_f

    emit_dmtc1_r_f ¶
    Source

    emit_dmtc1_r_f :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: FPR) {…}

    emit_dmuh ¶
    Source

    emit_dmuh :: emit_dmuh_r_r_r

    emit_dmuh_r_r_r ¶
    Source

    emit_dmuh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dmuhu ¶
    Source

    emit_dmuhu :: emit_dmuhu_r_r_r

    emit_dmuhu_r_r_r ¶
    Source

    emit_dmuhu_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dmul_r6 ¶
    Source

    emit_dmul_r6 :: emit_dmul_r6_r_r_r

    emit_dmul_r6_r_r_r ¶
    Source

    emit_dmul_r6_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dmult ¶
    Source

    emit_dmult :: emit_dmult_r_r

    emit_dmult_r_r ¶
    Source

    emit_dmult_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_dmultu ¶
    Source

    emit_dmultu :: emit_dmultu_r_r

    emit_dmultu_r_r ¶
    Source

    emit_dmultu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_dmulu ¶
    Source

    emit_dmulu :: emit_dmulu_r_r_r

    emit_dmulu_r_r_r ¶
    Source

    emit_dmulu_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dotp_s_d ¶
    Source

    emit_dotp_s_d :: emit_dotp_s_d_w_w_w

    emit_dotp_s_d_w_w_w ¶
    Source

    emit_dotp_s_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_dotp_s_h ¶
    Source

    emit_dotp_s_h :: emit_dotp_s_h_w_w_w

    emit_dotp_s_h_w_w_w ¶
    Source

    emit_dotp_s_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_dotp_s_w ¶
    Source

    emit_dotp_s_w :: emit_dotp_s_w_w_w_w

    emit_dotp_s_w_w_w_w ¶
    Source

    emit_dotp_s_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_dotp_u_d ¶
    Source

    emit_dotp_u_d :: emit_dotp_u_d_w_w_w

    emit_dotp_u_d_w_w_w ¶
    Source

    emit_dotp_u_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_dotp_u_h ¶
    Source

    emit_dotp_u_h :: emit_dotp_u_h_w_w_w

    emit_dotp_u_h_w_w_w ¶
    Source

    emit_dotp_u_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_dotp_u_w ¶
    Source

    emit_dotp_u_w :: emit_dotp_u_w_w_w_w

    emit_dotp_u_w_w_w_w ¶
    Source

    emit_dotp_u_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_dpa_w_ph ¶
    Source

    emit_dpa_w_ph :: emit_dpa_w_ph_i5_r_r

    emit_dpa_w_ph_i5_r_r ¶
    Source

    emit_dpa_w_ph_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_dpaq_s_w_ph ¶
    Source

    emit_dpaq_s_w_ph :: emit_dpaq_s_w_ph_i5_r_r

    emit_dpaq_s_w_ph_i5_r_r ¶
    Source

    emit_dpaq_s_w_ph_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_dpaq_sa_l_w ¶
    Source

    emit_dpaq_sa_l_w :: emit_dpaq_sa_l_w_i5_r_r

    emit_dpaq_sa_l_w_i5_r_r ¶
    Source

    emit_dpaq_sa_l_w_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_dpau_h_qbl ¶
    Source

    emit_dpau_h_qbl :: emit_dpau_h_qbl_i5_r_r

    emit_dpau_h_qbl_i5_r_r ¶
    Source

    emit_dpau_h_qbl_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_dpau_h_qbr ¶
    Source

    emit_dpau_h_qbr :: emit_dpau_h_qbr_i5_r_r

    emit_dpau_h_qbr_i5_r_r ¶
    Source

    emit_dpau_h_qbr_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_dpax_w_ph ¶
    Source

    emit_dpax_w_ph :: emit_dpax_w_ph_i5_r_r

    emit_dpax_w_ph_i5_r_r ¶
    Source

    emit_dpax_w_ph_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_dpcs ¶
    Source

    emit_dpcs :: emit_dpcs_none

    emit_dpcs_none ¶
    Source

    emit_dpcs_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_dpct ¶
    Source

    emit_dpct :: emit_dpct_none

    emit_dpct_none ¶
    Source

    emit_dpct_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_dps_w_ph ¶
    Source

    emit_dps_w_ph :: emit_dps_w_ph_i5_r_r

    emit_dps_w_ph_i5_r_r ¶
    Source

    emit_dps_w_ph_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_dpsq_s_w_ph ¶
    Source

    emit_dpsq_s_w_ph :: emit_dpsq_s_w_ph_i5_r_r

    emit_dpsq_s_w_ph_i5_r_r ¶
    Source

    emit_dpsq_s_w_ph_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_dpsq_sa_l_w ¶
    Source

    emit_dpsq_sa_l_w :: emit_dpsq_sa_l_w_i5_r_r

    emit_dpsq_sa_l_w_i5_r_r ¶
    Source

    emit_dpsq_sa_l_w_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_dpsu_h_qbl ¶
    Source

    emit_dpsu_h_qbl :: emit_dpsu_h_qbl_i5_r_r

    emit_dpsu_h_qbl_i5_r_r ¶
    Source

    emit_dpsu_h_qbl_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_dpsu_h_qbr ¶
    Source

    emit_dpsu_h_qbr :: emit_dpsu_h_qbr_i5_r_r

    emit_dpsu_h_qbr_i5_r_r ¶
    Source

    emit_dpsu_h_qbr_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_dpsx_w_ph ¶
    Source

    emit_dpsx_w_ph :: emit_dpsx_w_ph_i5_r_r

    emit_dpsx_w_ph_i5_r_r ¶
    Source

    emit_dpsx_w_ph_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_drotr ¶
    Source

    emit_drotr :: emit_drotr_r_r_i5

    emit_drotr32 ¶
    Source

    emit_drotr32 :: emit_drotr32_r_r_i5

    emit_drotr32_r_r_i5 ¶
    Source

    emit_drotr32_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_drotr_r_r_i5 ¶
    Source

    emit_drotr_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_drotrv ¶
    Source

    emit_drotrv :: emit_drotrv_r_r_r

    emit_drotrv_r_r_r ¶
    Source

    emit_drotrv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dsbh ¶
    Source

    emit_dsbh :: emit_dsbh_r_r

    emit_dsbh_r_r ¶
    Source

    emit_dsbh_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_dshd ¶
    Source

    emit_dshd :: emit_dshd_r_r

    emit_dshd_r_r ¶
    Source

    emit_dshd_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_dsll ¶
    Source

    emit_dsll :: emit_dsll_r_r_i5

    emit_dsll32 ¶
    Source

    emit_dsll32 :: emit_dsll32_r_r_i5

    emit_dsll32_r_r_i5 ¶
    Source

    emit_dsll32_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_dsll_r_r_i5 ¶
    Source

    emit_dsll_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_dsllv ¶
    Source

    emit_dsllv :: emit_dsllv_r_r_r

    emit_dsllv_r_r_r ¶
    Source

    emit_dsllv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dsra ¶
    Source

    emit_dsra :: emit_dsra_r_r_i5

    emit_dsra32 ¶
    Source

    emit_dsra32 :: emit_dsra32_r_r_i5

    emit_dsra32_r_r_i5 ¶
    Source

    emit_dsra32_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_dsra_r_r_i5 ¶
    Source

    emit_dsra_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_dsrav ¶
    Source

    emit_dsrav :: emit_dsrav_r_r_r

    emit_dsrav_r_r_r ¶
    Source

    emit_dsrav_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dsrl ¶
    Source

    emit_dsrl :: emit_dsrl_r_r_i5

    emit_dsrl32 ¶
    Source

    emit_dsrl32 :: emit_dsrl32_r_r_i5

    emit_dsrl32_r_r_i5 ¶
    Source

    emit_dsrl32_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_dsrl_r_r_i5 ¶
    Source

    emit_dsrl_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_dsrlv ¶
    Source

    emit_dsrlv :: emit_dsrlv_r_r_r

    emit_dsrlv_r_r_r ¶
    Source

    emit_dsrlv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dsub ¶
    Source

    emit_dsub :: emit_dsub_r_r_r

    emit_dsub_r_r_r ¶
    Source

    emit_dsub_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_dsubu ¶
    Source

    emit_dsubu :: emit_dsubu_r_r_r

    emit_dsubu_r_r_r ¶
    Source

    emit_dsubu_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_ehb ¶
    Source

    emit_ehb :: emit_ehb_none

    emit_ehb_none ¶
    Source

    emit_ehb_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_ei ¶
    Source

    emit_ei :: emit_ei_r

    emit_ei_r ¶
    Source

    emit_ei_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_eret ¶
    Source

    emit_eret :: emit_eret_none

    emit_eret_none ¶
    Source

    emit_eret_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_ext ¶
    Source

    emit_ext :: emit_ext_r_r_i5_i5

    emit_ext_r_r_i5_i5 ¶
    Source

    emit_ext_r_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64, imm2: i64) {…}

    emit_extp ¶
    Source

    emit_extp :: emit_extp_r_i5_i5

    emit_extp_r_i5_i5 ¶
    Source

    emit_extp_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, imm2: i64) {…}

    emit_extpdp ¶
    Source

    emit_extpdp :: emit_extpdp_r_i5_i5

    emit_extpdp_r_i5_i5 ¶
    Source

    emit_extpdp_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, imm2: i64) {…}

    emit_extpdpv ¶
    Source

    emit_extpdpv :: emit_extpdpv_r_i5_r

    emit_extpdpv_r_i5_r ¶
    Source

    emit_extpdpv_r_i5_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, src: GPR) {…}

    emit_extpv ¶
    Source

    emit_extpv :: emit_extpv_r_i5_r

    emit_extpv_r_i5_r ¶
    Source

    emit_extpv_r_i5_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, src: GPR) {…}

    emit_extr_r_w ¶
    Source

    emit_extr_r_w :: emit_extr_r_w_r_i5_i5

    emit_extr_r_w_r_i5_i5 ¶
    Source

    emit_extr_r_w_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, imm2: i64) {…}

    emit_extr_rs_w ¶
    Source

    emit_extr_rs_w :: emit_extr_rs_w_r_i5_i5

    emit_extr_rs_w_r_i5_i5 ¶
    Source

    emit_extr_rs_w_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, imm2: i64) {…}

    emit_extr_s_h ¶
    Source

    emit_extr_s_h :: emit_extr_s_h_r_i5_i5

    emit_extr_s_h_r_i5_i5 ¶
    Source

    emit_extr_s_h_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, imm2: i64) {…}

    emit_extr_w ¶
    Source

    emit_extr_w :: emit_extr_w_r_i5_i5

    emit_extr_w_r_i5_i5 ¶
    Source

    emit_extr_w_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, imm2: i64) {…}

    emit_extrv_r_w ¶
    Source

    emit_extrv_r_w :: emit_extrv_r_w_r_i5_r

    emit_extrv_r_w_r_i5_r ¶
    Source

    emit_extrv_r_w_r_i5_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, src: GPR) {…}

    emit_extrv_rs_w ¶
    Source

    emit_extrv_rs_w :: emit_extrv_rs_w_r_i5_r

    emit_extrv_rs_w_r_i5_r ¶
    Source

    emit_extrv_rs_w_r_i5_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, src: GPR) {…}

    emit_extrv_s_h ¶
    Source

    emit_extrv_s_h :: emit_extrv_s_h_r_i5_r

    emit_extrv_s_h_r_i5_r ¶
    Source

    emit_extrv_s_h_r_i5_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, src: GPR) {…}

    emit_extrv_w ¶
    Source

    emit_extrv_w :: emit_extrv_w_r_i5_r

    emit_extrv_w_r_i5_r ¶
    Source

    emit_extrv_w_r_i5_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64, src: GPR) {…}

    emit_fadd_d ¶
    Source

    emit_fadd_d :: emit_fadd_d_w_w_w

    emit_fadd_d_w_w_w ¶
    Source

    emit_fadd_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fadd_w ¶
    Source

    emit_fadd_w :: emit_fadd_w_w_w_w

    emit_fadd_w_w_w_w ¶
    Source

    emit_fadd_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fceq_d ¶
    Source

    emit_fceq_d :: emit_fceq_d_w_w_w

    emit_fceq_d_w_w_w ¶
    Source

    emit_fceq_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fceq_w ¶
    Source

    emit_fceq_w :: emit_fceq_w_w_w_w

    emit_fceq_w_w_w_w ¶
    Source

    emit_fceq_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fcle_d ¶
    Source

    emit_fcle_d :: emit_fcle_d_w_w_w

    emit_fcle_d_w_w_w ¶
    Source

    emit_fcle_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fcle_w ¶
    Source

    emit_fcle_w :: emit_fcle_w_w_w_w

    emit_fcle_w_w_w_w ¶
    Source

    emit_fcle_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fclt_d ¶
    Source

    emit_fclt_d :: emit_fclt_d_w_w_w

    emit_fclt_d_w_w_w ¶
    Source

    emit_fclt_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fclt_w ¶
    Source

    emit_fclt_w :: emit_fclt_w_w_w_w

    emit_fclt_w_w_w_w ¶
    Source

    emit_fclt_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fcne_d ¶
    Source

    emit_fcne_d :: emit_fcne_d_w_w_w

    emit_fcne_d_w_w_w ¶
    Source

    emit_fcne_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fcne_w ¶
    Source

    emit_fcne_w :: emit_fcne_w_w_w_w

    emit_fcne_w_w_w_w ¶
    Source

    emit_fcne_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fcvt_d_w ¶
    Source

    emit_fcvt_d_w :: emit_fcvt_d_w_f_f

    emit_fcvt_d_w_f_f ¶
    Source

    emit_fcvt_d_w_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_fcvt_s_d ¶
    Source

    emit_fcvt_s_d :: emit_fcvt_s_d_f_f

    emit_fcvt_s_d_f_f ¶
    Source

    emit_fcvt_s_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_fcvt_s_w ¶
    Source

    emit_fcvt_s_w :: emit_fcvt_s_w_f_f

    emit_fcvt_s_w_f_f ¶
    Source

    emit_fcvt_s_w_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_fdiv_d ¶
    Source

    emit_fdiv_d :: emit_fdiv_d_w_w_w

    emit_fdiv_d_w_w_w ¶
    Source

    emit_fdiv_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fdiv_w ¶
    Source

    emit_fdiv_w :: emit_fdiv_w_w_w_w

    emit_fdiv_w_w_w_w ¶
    Source

    emit_fdiv_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_ffint_s_d ¶
    Source

    emit_ffint_s_d :: emit_ffint_s_d_w_w

    emit_ffint_s_d_w_w ¶
    Source

    emit_ffint_s_d_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_ffint_s_w ¶
    Source

    emit_ffint_s_w :: emit_ffint_s_w_w_w

    emit_ffint_s_w_w_w ¶
    Source

    emit_ffint_s_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_ffint_u_d ¶
    Source

    emit_ffint_u_d :: emit_ffint_u_d_w_w

    emit_ffint_u_d_w_w ¶
    Source

    emit_ffint_u_d_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_ffint_u_w ¶
    Source

    emit_ffint_u_w :: emit_ffint_u_w_w_w

    emit_ffint_u_w_w_w ¶
    Source

    emit_ffint_u_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_floor_l_d ¶
    Source

    emit_floor_l_d :: emit_floor_l_d_f_f

    emit_floor_l_d_f_f ¶
    Source

    emit_floor_l_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_floor_l_s ¶
    Source

    emit_floor_l_s :: emit_floor_l_s_f_f

    emit_floor_l_s_f_f ¶
    Source

    emit_floor_l_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_floor_w_d ¶
    Source

    emit_floor_w_d :: emit_floor_w_d_f_f

    emit_floor_w_d_f_f ¶
    Source

    emit_floor_w_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_floor_w_s ¶
    Source

    emit_floor_w_s :: emit_floor_w_s_f_f

    emit_floor_w_s_f_f ¶
    Source

    emit_floor_w_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_fmax_d ¶
    Source

    emit_fmax_d :: emit_fmax_d_w_w_w

    emit_fmax_d_w_w_w ¶
    Source

    emit_fmax_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fmax_w ¶
    Source

    emit_fmax_w :: emit_fmax_w_w_w_w

    emit_fmax_w_w_w_w ¶
    Source

    emit_fmax_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fmin_d ¶
    Source

    emit_fmin_d :: emit_fmin_d_w_w_w

    emit_fmin_d_w_w_w ¶
    Source

    emit_fmin_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fmin_w ¶
    Source

    emit_fmin_w :: emit_fmin_w_w_w_w

    emit_fmin_w_w_w_w ¶
    Source

    emit_fmin_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fmul_d ¶
    Source

    emit_fmul_d :: emit_fmul_d_w_w_w

    emit_fmul_d_w_w_w ¶
    Source

    emit_fmul_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fmul_w ¶
    Source

    emit_fmul_w :: emit_fmul_w_w_w_w

    emit_fmul_w_w_w_w ¶
    Source

    emit_fmul_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_frcp_d ¶
    Source

    emit_frcp_d :: emit_frcp_d_w_w

    emit_frcp_d_w_w ¶
    Source

    emit_frcp_d_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_frcp_w ¶
    Source

    emit_frcp_w :: emit_frcp_w_w_w

    emit_frcp_w_w_w ¶
    Source

    emit_frcp_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_frint_d ¶
    Source

    emit_frint_d :: emit_frint_d_w_w

    emit_frint_d_w_w ¶
    Source

    emit_frint_d_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_frint_w ¶
    Source

    emit_frint_w :: emit_frint_w_w_w

    emit_frint_w_w_w ¶
    Source

    emit_frint_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_frsqrt_d ¶
    Source

    emit_frsqrt_d :: emit_frsqrt_d_w_w

    emit_frsqrt_d_w_w ¶
    Source

    emit_frsqrt_d_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_frsqrt_w ¶
    Source

    emit_frsqrt_w :: emit_frsqrt_w_w_w

    emit_frsqrt_w_w_w ¶
    Source

    emit_frsqrt_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_fsqrt_d ¶
    Source

    emit_fsqrt_d :: emit_fsqrt_d_w_w

    emit_fsqrt_d_w_w ¶
    Source

    emit_fsqrt_d_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_fsqrt_w ¶
    Source

    emit_fsqrt_w :: emit_fsqrt_w_w_w

    emit_fsqrt_w_w_w ¶
    Source

    emit_fsqrt_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_fsub_d ¶
    Source

    emit_fsub_d :: emit_fsub_d_w_w_w

    emit_fsub_d_w_w_w ¶
    Source

    emit_fsub_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_fsub_w ¶
    Source

    emit_fsub_w :: emit_fsub_w_w_w_w

    emit_fsub_w_w_w_w ¶
    Source

    emit_fsub_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_ftrunc_s_d ¶
    Source

    emit_ftrunc_s_d :: emit_ftrunc_s_d_w_w

    emit_ftrunc_s_d_w_w ¶
    Source

    emit_ftrunc_s_d_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_ftrunc_s_w ¶
    Source

    emit_ftrunc_s_w :: emit_ftrunc_s_w_w_w

    emit_ftrunc_s_w_w_w ¶
    Source

    emit_ftrunc_s_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_ftrunc_u_d ¶
    Source

    emit_ftrunc_u_d :: emit_ftrunc_u_d_w_w

    emit_ftrunc_u_d_w_w ¶
    Source

    emit_ftrunc_u_d_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_ftrunc_u_w ¶
    Source

    emit_ftrunc_u_w :: emit_ftrunc_u_w_w_w

    emit_ftrunc_u_w_w_w ¶
    Source

    emit_ftrunc_u_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_gpf ¶
    Source

    emit_gpf :: emit_gpf_none

    emit_gpf_none ¶
    Source

    emit_gpf_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_gpl ¶
    Source

    emit_gpl :: emit_gpl_none

    emit_gpl_none ¶
    Source

    emit_gpl_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_ins ¶
    Source

    emit_ins :: emit_ins_r_r_i5_i5

    emit_ins_r_r_i5_i5 ¶
    Source

    emit_ins_r_r_i5_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64, imm2: i64) {…}

    emit_insert_b ¶
    Source

    emit_insert_b :: emit_insert_b_w_r_i5

    emit_insert_b_w_r_i5 ¶
    Source

    emit_insert_b_w_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: GPR, imm: i64) {…}

    emit_insert_d ¶
    Source

    emit_insert_d :: emit_insert_d_w_r_i5

    emit_insert_d_w_r_i5 ¶
    Source

    emit_insert_d_w_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: GPR, imm: i64) {…}

    emit_insert_h ¶
    Source

    emit_insert_h :: emit_insert_h_w_r_i5

    emit_insert_h_w_r_i5 ¶
    Source

    emit_insert_h_w_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: GPR, imm: i64) {…}

    emit_insert_w ¶
    Source

    emit_insert_w :: emit_insert_w_w_r_i5

    emit_insert_w_w_r_i5 ¶
    Source

    emit_insert_w_w_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: GPR, imm: i64) {…}

    emit_insv ¶
    Source

    emit_insv :: emit_insv_r_r

    emit_insv_r_r ¶
    Source

    emit_insv_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_insve_b ¶
    Source

    emit_insve_b :: emit_insve_b_w_w_i5

    emit_insve_b_w_w_i5 ¶
    Source

    emit_insve_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_insve_d ¶
    Source

    emit_insve_d :: emit_insve_d_w_w_i5

    emit_insve_d_w_w_i5 ¶
    Source

    emit_insve_d_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_insve_h ¶
    Source

    emit_insve_h :: emit_insve_h_w_w_i5

    emit_insve_h_w_w_i5 ¶
    Source

    emit_insve_h_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_insve_w ¶
    Source

    emit_insve_w :: emit_insve_w_w_w_i5

    emit_insve_w_w_w_i5 ¶
    Source

    emit_insve_w_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_intpl ¶
    Source

    emit_intpl :: emit_intpl_none

    emit_intpl_none ¶
    Source

    emit_intpl_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_j ¶
    Source

    emit_j :: emit_j_j

    emit_j_j ¶
    Source

    emit_j_j :: proc(instructions: ^[dynamic]Instruction, target: u32) {…}

    emit_jal ¶
    Source

    emit_jal :: emit_jal_j

    emit_jal_j ¶
    Source

    emit_jal_j :: proc(instructions: ^[dynamic]Instruction, target: u32) {…}

    emit_jalr ¶
    Source

    emit_jalr :: emit_jalr_r_r

    emit_jalr_r_r ¶
    Source

    emit_jalr_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_jialc ¶
    Source

    emit_jialc :: emit_jialc_r_i16

    emit_jialc_r_i16 ¶
    Source

    emit_jialc_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_jic ¶
    Source

    emit_jic :: emit_jic_r_i16

    emit_jic_r_i16 ¶
    Source

    emit_jic_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_jr ¶
    Source

    emit_jr :: emit_jr_r

    emit_jr_r ¶
    Source

    emit_jr_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_lb ¶
    Source

    emit_lb :: emit_lb_r_m

    emit_lb_r_m ¶
    Source

    emit_lb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_lbu ¶
    Source

    emit_lbu :: emit_lbu_r_m

    emit_lbu_r_m ¶
    Source

    emit_lbu_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_lbux ¶
    Source

    emit_lbux :: emit_lbux_r_r_r

    emit_lbux_r_r_r ¶
    Source

    emit_lbux_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_ld ¶
    Source

    emit_ld :: emit_ld_r_m

    emit_ld_b ¶
    Source

    emit_ld_b :: emit_ld_b_w_m

    emit_ld_b_w_m ¶
    Source

    emit_ld_b_w_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_ld_d ¶
    Source

    emit_ld_d :: emit_ld_d_w_m

    emit_ld_d_w_m ¶
    Source

    emit_ld_d_w_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_ld_h ¶
    Source

    emit_ld_h :: emit_ld_h_w_m

    emit_ld_h_w_m ¶
    Source

    emit_ld_h_w_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_ld_r_m ¶
    Source

    emit_ld_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_ld_w ¶
    Source

    emit_ld_w :: emit_ld_w_w_m

    emit_ld_w_w_m ¶
    Source

    emit_ld_w_w_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_ldc1 ¶
    Source

    emit_ldc1 :: emit_ldc1_f_m

    emit_ldc1_f_m ¶
    Source

    emit_ldc1_f_m :: proc(instructions: ^[dynamic]Instruction, dst: FPR, mem: Memory) {…}

    emit_ldc2 ¶
    Source

    emit_ldc2 :: emit_ldc2_c2_m

    emit_ldc2_c2_m ¶
    Source

    emit_ldc2_c2_m :: proc(instructions: ^[dynamic]Instruction, dst: GTE_DataReg, mem: Memory) {…}

    emit_ldi_b ¶
    Source

    emit_ldi_b :: emit_ldi_b_w_i5

    emit_ldi_b_w_i5 ¶
    Source

    emit_ldi_b_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

    emit_ldi_d ¶
    Source

    emit_ldi_d :: emit_ldi_d_w_i5

    emit_ldi_d_w_i5 ¶
    Source

    emit_ldi_d_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

    emit_ldi_h ¶
    Source

    emit_ldi_h :: emit_ldi_h_w_i5

    emit_ldi_h_w_i5 ¶
    Source

    emit_ldi_h_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

    emit_ldi_w ¶
    Source

    emit_ldi_w :: emit_ldi_w_w_i5

    emit_ldi_w_w_i5 ¶
    Source

    emit_ldi_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

    emit_ldl ¶
    Source

    emit_ldl :: emit_ldl_r_m

    emit_ldl_r_m ¶
    Source

    emit_ldl_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_ldpc ¶
    Source

    emit_ldpc :: emit_ldpc_r_rel

    emit_ldpc_r_rel ¶
    Source

    emit_ldpc_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_ldr ¶
    Source

    emit_ldr :: emit_ldr_r_m

    emit_ldr_r_m ¶
    Source

    emit_ldr_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_ldxc1 ¶
    Source

    emit_ldxc1 :: emit_ldxc1_f_r_r

    emit_ldxc1_f_r_r ¶
    Source

    emit_ldxc1_f_r_r :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: GPR, src2: GPR) {…}

    emit_lh ¶
    Source

    emit_lh :: emit_lh_r_m

    emit_lh_r_m ¶
    Source

    emit_lh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_lhu ¶
    Source

    emit_lhu :: emit_lhu_r_m

    emit_lhu_r_m ¶
    Source

    emit_lhu_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_lhx ¶
    Source

    emit_lhx :: emit_lhx_r_r_r

    emit_lhx_r_r_r ¶
    Source

    emit_lhx_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_ll ¶
    Source

    emit_ll :: emit_ll_r_m

    emit_ll_r_m ¶
    Source

    emit_ll_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_lld ¶
    Source

    emit_lld :: emit_lld_r_m

    emit_lld_r_m ¶
    Source

    emit_lld_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_lq ¶
    Source

    emit_lq :: emit_lq_r_m

    emit_lq_r_m ¶
    Source

    emit_lq_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_lqc2 ¶
    Source

    emit_lqc2 :: emit_lqc2_c2_m

    emit_lqc2_c2_m ¶
    Source

    emit_lqc2_c2_m :: proc(instructions: ^[dynamic]Instruction, dst: GTE_DataReg, mem: Memory) {…}

    emit_lsa ¶
    Source

    emit_lsa :: emit_lsa_r_r_r_i5

    emit_lsa_r_r_r_i5 ¶
    Source

    emit_lsa_r_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR, imm: i64) {…}

    emit_lui ¶
    Source

    emit_lui :: emit_lui_r_u16

    emit_lui_r_u16 ¶
    Source

    emit_lui_r_u16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_lv_q ¶
    Source

    emit_lv_q :: emit_lv_q_vq_m

    emit_lv_q_vq_m ¶
    Source

    emit_lv_q_vq_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_lv_s ¶
    Source

    emit_lv_s :: emit_lv_s_vs_m

    emit_lv_s_vs_m ¶
    Source

    emit_lv_s_vs_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_lvl_q ¶
    Source

    emit_lvl_q :: emit_lvl_q_vq_m

    emit_lvl_q_vq_m ¶
    Source

    emit_lvl_q_vq_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_lvr_q ¶
    Source

    emit_lvr_q :: emit_lvr_q_vq_m

    emit_lvr_q_vq_m ¶
    Source

    emit_lvr_q_vq_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_lw ¶
    Source

    emit_lw :: emit_lw_r_m

    emit_lw_r_m ¶
    Source

    emit_lw_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_lwc1 ¶
    Source

    emit_lwc1 :: emit_lwc1_f_m

    emit_lwc1_f_m ¶
    Source

    emit_lwc1_f_m :: proc(instructions: ^[dynamic]Instruction, dst: FPR, mem: Memory) {…}

    emit_lwc2 ¶
    Source

    emit_lwc2 :: emit_lwc2_c2_m

    emit_lwc2_c2_m ¶
    Source

    emit_lwc2_c2_m :: proc(instructions: ^[dynamic]Instruction, dst: GTE_DataReg, mem: Memory) {…}

    emit_lwl ¶
    Source

    emit_lwl :: emit_lwl_r_m

    emit_lwl_r_m ¶
    Source

    emit_lwl_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_lwpc ¶
    Source

    emit_lwpc :: emit_lwpc_r_rel

    emit_lwpc_r_rel ¶
    Source

    emit_lwpc_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_lwr ¶
    Source

    emit_lwr :: emit_lwr_r_m

    emit_lwr_r_m ¶
    Source

    emit_lwr_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_lwu ¶
    Source

    emit_lwu :: emit_lwu_r_m

    emit_lwu_r_m ¶
    Source

    emit_lwu_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_lwupc ¶
    Source

    emit_lwupc :: emit_lwupc_r_rel

    emit_lwupc_r_rel ¶
    Source

    emit_lwupc_r_rel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, target: u32) {…}

    emit_lwx ¶
    Source

    emit_lwx :: emit_lwx_r_r_r

    emit_lwx_r_r_r ¶
    Source

    emit_lwx_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_lwxc1 ¶
    Source

    emit_lwxc1 :: emit_lwxc1_f_r_r

    emit_lwxc1_f_r_r ¶
    Source

    emit_lwxc1_f_r_r :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: GPR, src2: GPR) {…}

    emit_madd ¶
    Source

    emit_madd :: emit_madd_r_r

    emit_madd1 ¶
    Source

    emit_madd1 :: emit_madd1_r_r

    emit_madd1_r_r ¶
    Source

    emit_madd1_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_madd_d ¶
    Source

    emit_madd_d :: emit_madd_d_f_f_f_f

    emit_madd_d_f_f_f_f ¶
    Source

    emit_madd_d_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_madd_ee ¶
    Source

    emit_madd_ee :: emit_madd_ee_r_r_r

    emit_madd_ee_r_r_r ¶
    Source

    emit_madd_ee_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_madd_ps ¶
    Source

    emit_madd_ps :: emit_madd_ps_f_f_f_f

    emit_madd_ps_f_f_f_f ¶
    Source

    emit_madd_ps_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_madd_r_r ¶
    Source

    emit_madd_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_madd_s ¶
    Source

    emit_madd_s :: emit_madd_s_f_f_f_f

    emit_madd_s_f_f_f_f ¶
    Source

    emit_madd_s_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_maddu ¶
    Source

    emit_maddu :: emit_maddu_r_r

    emit_maddu1 ¶
    Source

    emit_maddu1 :: emit_maddu1_r_r

    emit_maddu1_r_r ¶
    Source

    emit_maddu1_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_maddu_ee ¶
    Source

    emit_maddu_ee :: emit_maddu_ee_r_r_r

    emit_maddu_ee_r_r_r ¶
    Source

    emit_maddu_ee_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_maddu_r_r ¶
    Source

    emit_maddu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_maddv_b ¶
    Source

    emit_maddv_b :: emit_maddv_b_w_w_w

    emit_maddv_b_w_w_w ¶
    Source

    emit_maddv_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_maddv_d ¶
    Source

    emit_maddv_d :: emit_maddv_d_w_w_w

    emit_maddv_d_w_w_w ¶
    Source

    emit_maddv_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_maddv_h ¶
    Source

    emit_maddv_h :: emit_maddv_h_w_w_w

    emit_maddv_h_w_w_w ¶
    Source

    emit_maddv_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_maddv_w ¶
    Source

    emit_maddv_w :: emit_maddv_w_w_w_w

    emit_maddv_w_w_w_w ¶
    Source

    emit_maddv_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_maq_s_w_phl ¶
    Source

    emit_maq_s_w_phl :: emit_maq_s_w_phl_i5_r_r

    emit_maq_s_w_phl_i5_r_r ¶
    Source

    emit_maq_s_w_phl_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_maq_s_w_phr ¶
    Source

    emit_maq_s_w_phr :: emit_maq_s_w_phr_i5_r_r

    emit_maq_s_w_phr_i5_r_r ¶
    Source

    emit_maq_s_w_phr_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_maq_sa_w_phl ¶
    Source

    emit_maq_sa_w_phl :: emit_maq_sa_w_phl_i5_r_r

    emit_maq_sa_w_phl_i5_r_r ¶
    Source

    emit_maq_sa_w_phl_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_maq_sa_w_phr ¶
    Source

    emit_maq_sa_w_phr :: emit_maq_sa_w_phr_i5_r_r

    emit_maq_sa_w_phr_i5_r_r ¶
    Source

    emit_maq_sa_w_phr_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_max_s_b ¶
    Source

    emit_max_s_b :: emit_max_s_b_w_w_w

    emit_max_s_b_w_w_w ¶
    Source

    emit_max_s_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_max_s_d ¶
    Source

    emit_max_s_d :: emit_max_s_d_w_w_w

    emit_max_s_d_w_w_w ¶
    Source

    emit_max_s_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_max_s_h ¶
    Source

    emit_max_s_h :: emit_max_s_h_w_w_w

    emit_max_s_h_w_w_w ¶
    Source

    emit_max_s_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_max_s_w ¶
    Source

    emit_max_s_w :: emit_max_s_w_w_w_w

    emit_max_s_w_w_w_w ¶
    Source

    emit_max_s_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_max_u_b ¶
    Source

    emit_max_u_b :: emit_max_u_b_w_w_w

    emit_max_u_b_w_w_w ¶
    Source

    emit_max_u_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_max_u_d ¶
    Source

    emit_max_u_d :: emit_max_u_d_w_w_w

    emit_max_u_d_w_w_w ¶
    Source

    emit_max_u_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_max_u_h ¶
    Source

    emit_max_u_h :: emit_max_u_h_w_w_w

    emit_max_u_h_w_w_w ¶
    Source

    emit_max_u_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_max_u_w ¶
    Source

    emit_max_u_w :: emit_max_u_w_w_w_w

    emit_max_u_w_w_w_w ¶
    Source

    emit_max_u_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mfc0 ¶
    Source

    emit_mfc0 :: emit_mfc0_r_c0_sel

    emit_mfc0_r_c0_sel ¶
    Source

    emit_mfc0_r_c0_sel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: CP0_Reg, imm: i64) {…}

    emit_mfc1 ¶
    Source

    emit_mfc1 :: emit_mfc1_r_f

    emit_mfc1_r_f ¶
    Source

    emit_mfc1_r_f :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: FPR) {…}

    emit_mfc2 ¶
    Source

    emit_mfc2 :: emit_mfc2_r_c2

    emit_mfc2_r_c2 ¶
    Source

    emit_mfc2_r_c2 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GTE_DataReg) {…}

    emit_mfhc0 ¶
    Source

    emit_mfhc0 :: emit_mfhc0_r_c0_sel

    emit_mfhc0_r_c0_sel ¶
    Source

    emit_mfhc0_r_c0_sel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: CP0_Reg, imm: i64) {…}

    emit_mfhc1 ¶
    Source

    emit_mfhc1 :: emit_mfhc1_r_f

    emit_mfhc1_r_f ¶
    Source

    emit_mfhc1_r_f :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: FPR) {…}

    emit_mfhi ¶
    Source

    emit_mfhi :: emit_mfhi_r

    emit_mfhi1 ¶
    Source

    emit_mfhi1 :: emit_mfhi1_r

    emit_mfhi1_r ¶
    Source

    emit_mfhi1_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_mfhi_r ¶
    Source

    emit_mfhi_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_mflo ¶
    Source

    emit_mflo :: emit_mflo_r

    emit_mflo1 ¶
    Source

    emit_mflo1 :: emit_mflo1_r

    emit_mflo1_r ¶
    Source

    emit_mflo1_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_mflo_r ¶
    Source

    emit_mflo_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_mfsa ¶
    Source

    emit_mfsa :: emit_mfsa_r

    emit_mfsa_r ¶
    Source

    emit_mfsa_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_mfv ¶
    Source

    emit_mfv :: emit_mfv_r_vs

    emit_mfv_r_vs ¶
    Source

    emit_mfv_r_vs :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: Register) {…}

    emit_mfvc ¶
    Source

    emit_mfvc :: emit_mfvc_r_i5

    emit_mfvc_r_i5 ¶
    Source

    emit_mfvc_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_min_s_b ¶
    Source

    emit_min_s_b :: emit_min_s_b_w_w_w

    emit_min_s_b_w_w_w ¶
    Source

    emit_min_s_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_min_s_d ¶
    Source

    emit_min_s_d :: emit_min_s_d_w_w_w

    emit_min_s_d_w_w_w ¶
    Source

    emit_min_s_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_min_s_h ¶
    Source

    emit_min_s_h :: emit_min_s_h_w_w_w

    emit_min_s_h_w_w_w ¶
    Source

    emit_min_s_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_min_s_w ¶
    Source

    emit_min_s_w :: emit_min_s_w_w_w_w

    emit_min_s_w_w_w_w ¶
    Source

    emit_min_s_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_min_u_b ¶
    Source

    emit_min_u_b :: emit_min_u_b_w_w_w

    emit_min_u_b_w_w_w ¶
    Source

    emit_min_u_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_min_u_d ¶
    Source

    emit_min_u_d :: emit_min_u_d_w_w_w

    emit_min_u_d_w_w_w ¶
    Source

    emit_min_u_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_min_u_h ¶
    Source

    emit_min_u_h :: emit_min_u_h_w_w_w

    emit_min_u_h_w_w_w ¶
    Source

    emit_min_u_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_min_u_w ¶
    Source

    emit_min_u_w :: emit_min_u_w_w_w_w

    emit_min_u_w_w_w_w ¶
    Source

    emit_min_u_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mod ¶
    Source

    emit_mod :: emit_mod_r_r_r

    emit_mod_r_r_r ¶
    Source

    emit_mod_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_mod_s_b ¶
    Source

    emit_mod_s_b :: emit_mod_s_b_w_w_w

    emit_mod_s_b_w_w_w ¶
    Source

    emit_mod_s_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mod_s_d ¶
    Source

    emit_mod_s_d :: emit_mod_s_d_w_w_w

    emit_mod_s_d_w_w_w ¶
    Source

    emit_mod_s_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mod_s_h ¶
    Source

    emit_mod_s_h :: emit_mod_s_h_w_w_w

    emit_mod_s_h_w_w_w ¶
    Source

    emit_mod_s_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mod_s_w ¶
    Source

    emit_mod_s_w :: emit_mod_s_w_w_w_w

    emit_mod_s_w_w_w_w ¶
    Source

    emit_mod_s_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mod_u_b ¶
    Source

    emit_mod_u_b :: emit_mod_u_b_w_w_w

    emit_mod_u_b_w_w_w ¶
    Source

    emit_mod_u_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mod_u_d ¶
    Source

    emit_mod_u_d :: emit_mod_u_d_w_w_w

    emit_mod_u_d_w_w_w ¶
    Source

    emit_mod_u_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mod_u_h ¶
    Source

    emit_mod_u_h :: emit_mod_u_h_w_w_w

    emit_mod_u_h_w_w_w ¶
    Source

    emit_mod_u_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mod_u_w ¶
    Source

    emit_mod_u_w :: emit_mod_u_w_w_w_w

    emit_mod_u_w_w_w_w ¶
    Source

    emit_mod_u_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_modu ¶
    Source

    emit_modu :: emit_modu_r_r_r

    emit_modu_r_r_r ¶
    Source

    emit_modu_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_mov_d ¶
    Source

    emit_mov_d :: emit_mov_d_f_f

    emit_mov_d_f_f ¶
    Source

    emit_mov_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_mov_ps ¶
    Source

    emit_mov_ps :: emit_mov_ps_f_f

    emit_mov_ps_f_f ¶
    Source

    emit_mov_ps_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_mov_s ¶
    Source

    emit_mov_s :: emit_mov_s_f_f

    emit_mov_s_f_f ¶
    Source

    emit_mov_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_movf ¶
    Source

    emit_movf :: emit_movf_r_r_cc

    emit_movf_d ¶
    Source

    emit_movf_d :: emit_movf_d_f_f_cc

    emit_movf_d_f_f_cc ¶
    Source

    emit_movf_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_movf_ps ¶
    Source

    emit_movf_ps :: emit_movf_ps_f_f_cc

    emit_movf_ps_f_f_cc ¶
    Source

    emit_movf_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_movf_r_r_cc ¶
    Source

    emit_movf_r_r_cc :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_movf_s ¶
    Source

    emit_movf_s :: emit_movf_s_f_f_cc

    emit_movf_s_f_f_cc ¶
    Source

    emit_movf_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_movn ¶
    Source

    emit_movn :: emit_movn_r_r_r

    emit_movn_d ¶
    Source

    emit_movn_d :: emit_movn_d_f_f_r

    emit_movn_d_f_f_r ¶
    Source

    emit_movn_d_f_f_r :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: GPR) {…}

    emit_movn_ps ¶
    Source

    emit_movn_ps :: emit_movn_ps_f_f_r

    emit_movn_ps_f_f_r ¶
    Source

    emit_movn_ps_f_f_r :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: GPR) {…}

    emit_movn_r_r_r ¶
    Source

    emit_movn_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_movn_s ¶
    Source

    emit_movn_s :: emit_movn_s_f_f_r

    emit_movn_s_f_f_r ¶
    Source

    emit_movn_s_f_f_r :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: GPR) {…}

    emit_movt ¶
    Source

    emit_movt :: emit_movt_r_r_cc

    emit_movt_d ¶
    Source

    emit_movt_d :: emit_movt_d_f_f_cc

    emit_movt_d_f_f_cc ¶
    Source

    emit_movt_d_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_movt_ps ¶
    Source

    emit_movt_ps :: emit_movt_ps_f_f_cc

    emit_movt_ps_f_f_cc ¶
    Source

    emit_movt_ps_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_movt_r_r_cc ¶
    Source

    emit_movt_r_r_cc :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_movt_s ¶
    Source

    emit_movt_s :: emit_movt_s_f_f_cc

    emit_movt_s_f_f_cc ¶
    Source

    emit_movt_s_f_f_cc :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, imm: i64) {…}

    emit_movz ¶
    Source

    emit_movz :: emit_movz_r_r_r

    emit_movz_d ¶
    Source

    emit_movz_d :: emit_movz_d_f_f_r

    emit_movz_d_f_f_r ¶
    Source

    emit_movz_d_f_f_r :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: GPR) {…}

    emit_movz_ps ¶
    Source

    emit_movz_ps :: emit_movz_ps_f_f_r

    emit_movz_ps_f_f_r ¶
    Source

    emit_movz_ps_f_f_r :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: GPR) {…}

    emit_movz_r_r_r ¶
    Source

    emit_movz_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_movz_s ¶
    Source

    emit_movz_s :: emit_movz_s_f_f_r

    emit_movz_s_f_f_r ¶
    Source

    emit_movz_s_f_f_r :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: GPR) {…}

    emit_msub ¶
    Source

    emit_msub :: emit_msub_r_r

    emit_msub1 ¶
    Source

    emit_msub1 :: emit_msub1_r_r

    emit_msub1_r_r ¶
    Source

    emit_msub1_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_msub_d ¶
    Source

    emit_msub_d :: emit_msub_d_f_f_f_f

    emit_msub_d_f_f_f_f ¶
    Source

    emit_msub_d_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_msub_ee ¶
    Source

    emit_msub_ee :: emit_msub_ee_r_r_r

    emit_msub_ee_r_r_r ¶
    Source

    emit_msub_ee_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_msub_ps ¶
    Source

    emit_msub_ps :: emit_msub_ps_f_f_f_f

    emit_msub_ps_f_f_f_f ¶
    Source

    emit_msub_ps_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_msub_r_r ¶
    Source

    emit_msub_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_msub_s ¶
    Source

    emit_msub_s :: emit_msub_s_f_f_f_f

    emit_msub_s_f_f_f_f ¶
    Source

    emit_msub_s_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_msubu ¶
    Source

    emit_msubu :: emit_msubu_r_r

    emit_msubu1 ¶
    Source

    emit_msubu1 :: emit_msubu1_r_r

    emit_msubu1_r_r ¶
    Source

    emit_msubu1_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_msubu_ee ¶
    Source

    emit_msubu_ee :: emit_msubu_ee_r_r_r

    emit_msubu_ee_r_r_r ¶
    Source

    emit_msubu_ee_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_msubu_r_r ¶
    Source

    emit_msubu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_msubv_b ¶
    Source

    emit_msubv_b :: emit_msubv_b_w_w_w

    emit_msubv_b_w_w_w ¶
    Source

    emit_msubv_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_msubv_d ¶
    Source

    emit_msubv_d :: emit_msubv_d_w_w_w

    emit_msubv_d_w_w_w ¶
    Source

    emit_msubv_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_msubv_h ¶
    Source

    emit_msubv_h :: emit_msubv_h_w_w_w

    emit_msubv_h_w_w_w ¶
    Source

    emit_msubv_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_msubv_w ¶
    Source

    emit_msubv_w :: emit_msubv_w_w_w_w

    emit_msubv_w_w_w_w ¶
    Source

    emit_msubv_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mtc0 ¶
    Source

    emit_mtc0 :: emit_mtc0_r_c0_sel

    emit_mtc0_r_c0_sel ¶
    Source

    emit_mtc0_r_c0_sel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: CP0_Reg, imm: i64) {…}

    emit_mtc1 ¶
    Source

    emit_mtc1 :: emit_mtc1_r_f

    emit_mtc1_r_f ¶
    Source

    emit_mtc1_r_f :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: FPR) {…}

    emit_mtc2 ¶
    Source

    emit_mtc2 :: emit_mtc2_r_c2

    emit_mtc2_r_c2 ¶
    Source

    emit_mtc2_r_c2 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GTE_DataReg) {…}

    emit_mthc0 ¶
    Source

    emit_mthc0 :: emit_mthc0_r_c0_sel

    emit_mthc0_r_c0_sel ¶
    Source

    emit_mthc0_r_c0_sel :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: CP0_Reg, imm: i64) {…}

    emit_mthc1 ¶
    Source

    emit_mthc1 :: emit_mthc1_r_f

    emit_mthc1_r_f ¶
    Source

    emit_mthc1_r_f :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: FPR) {…}

    emit_mthi ¶
    Source

    emit_mthi :: emit_mthi_r

    emit_mthi1 ¶
    Source

    emit_mthi1 :: emit_mthi1_r

    emit_mthi1_r ¶
    Source

    emit_mthi1_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_mthi_r ¶
    Source

    emit_mthi_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_mthlip ¶
    Source

    emit_mthlip :: emit_mthlip_r_i5

    emit_mthlip_r_i5 ¶
    Source

    emit_mthlip_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_mtlo ¶
    Source

    emit_mtlo :: emit_mtlo_r

    emit_mtlo1 ¶
    Source

    emit_mtlo1 :: emit_mtlo1_r

    emit_mtlo1_r ¶
    Source

    emit_mtlo1_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_mtlo_r ¶
    Source

    emit_mtlo_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_mtsa ¶
    Source

    emit_mtsa :: emit_mtsa_r

    emit_mtsa_r ¶
    Source

    emit_mtsa_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_mtsab ¶
    Source

    emit_mtsab :: emit_mtsab_r_i16

    emit_mtsab_r_i16 ¶
    Source

    emit_mtsab_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_mtsah ¶
    Source

    emit_mtsah :: emit_mtsah_r_i16

    emit_mtsah_r_i16 ¶
    Source

    emit_mtsah_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_mtv ¶
    Source

    emit_mtv :: emit_mtv_r_vs

    emit_mtv_r_vs ¶
    Source

    emit_mtv_r_vs :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: Register) {…}

    emit_mtvc ¶
    Source

    emit_mtvc :: emit_mtvc_r_i5

    emit_mtvc_r_i5 ¶
    Source

    emit_mtvc_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_muh ¶
    Source

    emit_muh :: emit_muh_r_r_r

    emit_muh_r_r_r ¶
    Source

    emit_muh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_muhu ¶
    Source

    emit_muhu :: emit_muhu_r_r_r

    emit_muhu_r_r_r ¶
    Source

    emit_muhu_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_mul ¶
    Source

    emit_mul :: emit_mul_r_r_r

    emit_mul_d ¶
    Source

    emit_mul_d :: emit_mul_d_f_f_f

    emit_mul_d_f_f_f ¶
    Source

    emit_mul_d_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_mul_ps ¶
    Source

    emit_mul_ps :: emit_mul_ps_f_f_f

    emit_mul_ps_f_f_f ¶
    Source

    emit_mul_ps_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_mul_r_r_r ¶
    Source

    emit_mul_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_mul_s ¶
    Source

    emit_mul_s :: emit_mul_s_f_f_f

    emit_mul_s_f_f_f ¶
    Source

    emit_mul_s_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_muleq_s_w_phl ¶
    Source

    emit_muleq_s_w_phl :: emit_muleq_s_w_phl_r_r_r

    emit_muleq_s_w_phl_r_r_r ¶
    Source

    emit_muleq_s_w_phl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_muleq_s_w_phr ¶
    Source

    emit_muleq_s_w_phr :: emit_muleq_s_w_phr_r_r_r

    emit_muleq_s_w_phr_r_r_r ¶
    Source

    emit_muleq_s_w_phr_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_muleu_s_ph_qbl ¶
    Source

    emit_muleu_s_ph_qbl :: emit_muleu_s_ph_qbl_r_r_r

    emit_muleu_s_ph_qbl_r_r_r ¶
    Source

    emit_muleu_s_ph_qbl_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_muleu_s_ph_qbr ¶
    Source

    emit_muleu_s_ph_qbr :: emit_muleu_s_ph_qbr_r_r_r

    emit_muleu_s_ph_qbr_r_r_r ¶
    Source

    emit_muleu_s_ph_qbr_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_mulq_rs_ph ¶
    Source

    emit_mulq_rs_ph :: emit_mulq_rs_ph_r_r_r

    emit_mulq_rs_ph_r_r_r ¶
    Source

    emit_mulq_rs_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_mulq_s_ph ¶
    Source

    emit_mulq_s_ph :: emit_mulq_s_ph_r_r_r

    emit_mulq_s_ph_r_r_r ¶
    Source

    emit_mulq_s_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_mulsaq_s_w_ph ¶
    Source

    emit_mulsaq_s_w_ph :: emit_mulsaq_s_w_ph_i5_r_r

    emit_mulsaq_s_w_ph_i5_r_r ¶
    Source

    emit_mulsaq_s_w_ph_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_mult ¶
    Source

    emit_mult :: emit_mult_r_r

    emit_mult1 ¶
    Source

    emit_mult1 :: emit_mult1_r_r

    emit_mult1_r_r ¶
    Source

    emit_mult1_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_mult_r_r ¶
    Source

    emit_mult_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_multu ¶
    Source

    emit_multu :: emit_multu_r_r

    emit_multu1 ¶
    Source

    emit_multu1 :: emit_multu1_r_r

    emit_multu1_r_r ¶
    Source

    emit_multu1_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_multu_r_r ¶
    Source

    emit_multu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_mulu ¶
    Source

    emit_mulu :: emit_mulu_r_r_r

    emit_mulu_r_r_r ¶
    Source

    emit_mulu_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_mulv_b ¶
    Source

    emit_mulv_b :: emit_mulv_b_w_w_w

    emit_mulv_b_w_w_w ¶
    Source

    emit_mulv_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mulv_d ¶
    Source

    emit_mulv_d :: emit_mulv_d_w_w_w

    emit_mulv_d_w_w_w ¶
    Source

    emit_mulv_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mulv_h ¶
    Source

    emit_mulv_h :: emit_mulv_h_w_w_w

    emit_mulv_h_w_w_w ¶
    Source

    emit_mulv_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mulv_w ¶
    Source

    emit_mulv_w :: emit_mulv_w_w_w_w

    emit_mulv_w_w_w_w ¶
    Source

    emit_mulv_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_mvmva ¶
    Source

    emit_mvmva :: emit_mvmva_none

    emit_mvmva_none ¶
    Source

    emit_mvmva_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_nccs ¶
    Source

    emit_nccs :: emit_nccs_none

    emit_nccs_none ¶
    Source

    emit_nccs_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_ncct ¶
    Source

    emit_ncct :: emit_ncct_none

    emit_ncct_none ¶
    Source

    emit_ncct_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_ncds ¶
    Source

    emit_ncds :: emit_ncds_none

    emit_ncds_none ¶
    Source

    emit_ncds_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_ncdt ¶
    Source

    emit_ncdt :: emit_ncdt_none

    emit_ncdt_none ¶
    Source

    emit_ncdt_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_nclip ¶
    Source

    emit_nclip :: emit_nclip_none

    emit_nclip_none ¶
    Source

    emit_nclip_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_ncs ¶
    Source

    emit_ncs :: emit_ncs_none

    emit_ncs_none ¶
    Source

    emit_ncs_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_nct ¶
    Source

    emit_nct :: emit_nct_none

    emit_nct_none ¶
    Source

    emit_nct_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_neg_d ¶
    Source

    emit_neg_d :: emit_neg_d_f_f

    emit_neg_d_f_f ¶
    Source

    emit_neg_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_neg_ps ¶
    Source

    emit_neg_ps :: emit_neg_ps_f_f

    emit_neg_ps_f_f ¶
    Source

    emit_neg_ps_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_neg_s ¶
    Source

    emit_neg_s :: emit_neg_s_f_f

    emit_neg_s_f_f ¶
    Source

    emit_neg_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_nloc_b ¶
    Source

    emit_nloc_b :: emit_nloc_b_w_w

    emit_nloc_b_w_w ¶
    Source

    emit_nloc_b_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_nloc_d ¶
    Source

    emit_nloc_d :: emit_nloc_d_w_w

    emit_nloc_d_w_w ¶
    Source

    emit_nloc_d_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_nloc_h ¶
    Source

    emit_nloc_h :: emit_nloc_h_w_w

    emit_nloc_h_w_w ¶
    Source

    emit_nloc_h_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_nloc_w ¶
    Source

    emit_nloc_w :: emit_nloc_w_w_w

    emit_nloc_w_w_w ¶
    Source

    emit_nloc_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_nlzc_b ¶
    Source

    emit_nlzc_b :: emit_nlzc_b_w_w

    emit_nlzc_b_w_w ¶
    Source

    emit_nlzc_b_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_nlzc_d ¶
    Source

    emit_nlzc_d :: emit_nlzc_d_w_w

    emit_nlzc_d_w_w ¶
    Source

    emit_nlzc_d_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_nlzc_h ¶
    Source

    emit_nlzc_h :: emit_nlzc_h_w_w

    emit_nlzc_h_w_w ¶
    Source

    emit_nlzc_h_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_nlzc_w ¶
    Source

    emit_nlzc_w :: emit_nlzc_w_w_w

    emit_nlzc_w_w_w ¶
    Source

    emit_nlzc_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_nmadd_d ¶
    Source

    emit_nmadd_d :: emit_nmadd_d_f_f_f_f

    emit_nmadd_d_f_f_f_f ¶
    Source

    emit_nmadd_d_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_nmadd_ps ¶
    Source

    emit_nmadd_ps :: emit_nmadd_ps_f_f_f_f

    emit_nmadd_ps_f_f_f_f ¶
    Source

    emit_nmadd_ps_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_nmadd_s ¶
    Source

    emit_nmadd_s :: emit_nmadd_s_f_f_f_f

    emit_nmadd_s_f_f_f_f ¶
    Source

    emit_nmadd_s_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_nmsub_d ¶
    Source

    emit_nmsub_d :: emit_nmsub_d_f_f_f_f

    emit_nmsub_d_f_f_f_f ¶
    Source

    emit_nmsub_d_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_nmsub_ps ¶
    Source

    emit_nmsub_ps :: emit_nmsub_ps_f_f_f_f

    emit_nmsub_ps_f_f_f_f ¶
    Source

    emit_nmsub_ps_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_nmsub_s ¶
    Source

    emit_nmsub_s :: emit_nmsub_s_f_f_f_f

    emit_nmsub_s_f_f_f_f ¶
    Source

    emit_nmsub_s_f_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR, src3: FPR) {…}

    emit_nop ¶
    Source

    emit_nop :: emit_nop_none

    emit_nop_none ¶
    Source

    emit_nop_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_nor ¶
    Source

    emit_nor :: emit_nor_r_r_r

    emit_nor_r_r_r ¶
    Source

    emit_nor_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_nor_v ¶
    Source

    emit_nor_v :: emit_nor_v_w_w_w

    emit_nor_v_w_w_w ¶
    Source

    emit_nor_v_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_nori_b ¶
    Source

    emit_nori_b :: emit_nori_b_w_w_i5

    emit_nori_b_w_w_i5 ¶
    Source

    emit_nori_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_op_gte ¶
    Source

    emit_op_gte :: emit_op_gte_none

    emit_op_gte_none ¶
    Source

    emit_op_gte_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_or ¶
    Source

    emit_or :: emit_or_r_r_r

    emit_or_r_r_r ¶
    Source

    emit_or_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_or_v ¶
    Source

    emit_or_v :: emit_or_v_w_w_w

    emit_or_v_w_w_w ¶
    Source

    emit_or_v_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_ori ¶
    Source

    emit_ori :: emit_ori_r_r_u16

    emit_ori_b ¶
    Source

    emit_ori_b :: emit_ori_b_w_w_i5

    emit_ori_b_w_w_i5 ¶
    Source

    emit_ori_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_ori_r_r_u16 ¶
    Source

    emit_ori_r_r_u16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_pabsh ¶
    Source

    emit_pabsh :: emit_pabsh_r_r

    emit_pabsh_r_r ¶
    Source

    emit_pabsh_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_pabsw ¶
    Source

    emit_pabsw :: emit_pabsw_r_r

    emit_pabsw_r_r ¶
    Source

    emit_pabsw_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_paddb ¶
    Source

    emit_paddb :: emit_paddb_r_r_r

    emit_paddb_r_r_r ¶
    Source

    emit_paddb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_paddh ¶
    Source

    emit_paddh :: emit_paddh_r_r_r

    emit_paddh_r_r_r ¶
    Source

    emit_paddh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_paddsb ¶
    Source

    emit_paddsb :: emit_paddsb_r_r_r

    emit_paddsb_r_r_r ¶
    Source

    emit_paddsb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_paddsh ¶
    Source

    emit_paddsh :: emit_paddsh_r_r_r

    emit_paddsh_r_r_r ¶
    Source

    emit_paddsh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_paddsw ¶
    Source

    emit_paddsw :: emit_paddsw_r_r_r

    emit_paddsw_r_r_r ¶
    Source

    emit_paddsw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_paddub ¶
    Source

    emit_paddub :: emit_paddub_r_r_r

    emit_paddub_r_r_r ¶
    Source

    emit_paddub_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_padduh ¶
    Source

    emit_padduh :: emit_padduh_r_r_r

    emit_padduh_r_r_r ¶
    Source

    emit_padduh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_padduw ¶
    Source

    emit_padduw :: emit_padduw_r_r_r

    emit_padduw_r_r_r ¶
    Source

    emit_padduw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_paddw ¶
    Source

    emit_paddw :: emit_paddw_r_r_r

    emit_paddw_r_r_r ¶
    Source

    emit_paddw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pand ¶
    Source

    emit_pand :: emit_pand_r_r_r

    emit_pand_r_r_r ¶
    Source

    emit_pand_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pause ¶
    Source

    emit_pause :: emit_pause_none

    emit_pause_none ¶
    Source

    emit_pause_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_pceqb ¶
    Source

    emit_pceqb :: emit_pceqb_r_r_r

    emit_pceqb_r_r_r ¶
    Source

    emit_pceqb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pceqh ¶
    Source

    emit_pceqh :: emit_pceqh_r_r_r

    emit_pceqh_r_r_r ¶
    Source

    emit_pceqh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pceqw ¶
    Source

    emit_pceqw :: emit_pceqw_r_r_r

    emit_pceqw_r_r_r ¶
    Source

    emit_pceqw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pcgtb ¶
    Source

    emit_pcgtb :: emit_pcgtb_r_r_r

    emit_pcgtb_r_r_r ¶
    Source

    emit_pcgtb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pcgth ¶
    Source

    emit_pcgth :: emit_pcgth_r_r_r

    emit_pcgth_r_r_r ¶
    Source

    emit_pcgth_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pcgtw ¶
    Source

    emit_pcgtw :: emit_pcgtw_r_r_r

    emit_pcgtw_r_r_r ¶
    Source

    emit_pcgtw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pcnt_b ¶
    Source

    emit_pcnt_b :: emit_pcnt_b_w_w

    emit_pcnt_b_w_w ¶
    Source

    emit_pcnt_b_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_pcnt_d ¶
    Source

    emit_pcnt_d :: emit_pcnt_d_w_w

    emit_pcnt_d_w_w ¶
    Source

    emit_pcnt_d_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_pcnt_h ¶
    Source

    emit_pcnt_h :: emit_pcnt_h_w_w

    emit_pcnt_h_w_w ¶
    Source

    emit_pcnt_h_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_pcnt_w ¶
    Source

    emit_pcnt_w :: emit_pcnt_w_w_w

    emit_pcnt_w_w_w ¶
    Source

    emit_pcnt_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_pcpyh ¶
    Source

    emit_pcpyh :: emit_pcpyh_r_r

    emit_pcpyh_r_r ¶
    Source

    emit_pcpyh_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_pcpyld ¶
    Source

    emit_pcpyld :: emit_pcpyld_r_r_r

    emit_pcpyld_r_r_r ¶
    Source

    emit_pcpyld_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pcpyud ¶
    Source

    emit_pcpyud :: emit_pcpyud_r_r_r

    emit_pcpyud_r_r_r ¶
    Source

    emit_pcpyud_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pdivbw ¶
    Source

    emit_pdivbw :: emit_pdivbw_r_r

    emit_pdivbw_r_r ¶
    Source

    emit_pdivbw_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_pdivuw ¶
    Source

    emit_pdivuw :: emit_pdivuw_r_r

    emit_pdivuw_r_r ¶
    Source

    emit_pdivuw_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_pdivw ¶
    Source

    emit_pdivw :: emit_pdivw_r_r

    emit_pdivw_r_r ¶
    Source

    emit_pdivw_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_pexch ¶
    Source

    emit_pexch :: emit_pexch_r_r

    emit_pexch_r_r ¶
    Source

    emit_pexch_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_pexcw ¶
    Source

    emit_pexcw :: emit_pexcw_r_r

    emit_pexcw_r_r ¶
    Source

    emit_pexcw_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_pexeh ¶
    Source

    emit_pexeh :: emit_pexeh_r_r

    emit_pexeh_r_r ¶
    Source

    emit_pexeh_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_pexew ¶
    Source

    emit_pexew :: emit_pexew_r_r

    emit_pexew_r_r ¶
    Source

    emit_pexew_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_pext5 ¶
    Source

    emit_pext5 :: emit_pext5_r_r_r

    emit_pext5_r_r_r ¶
    Source

    emit_pext5_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pextlb ¶
    Source

    emit_pextlb :: emit_pextlb_r_r_r

    emit_pextlb_r_r_r ¶
    Source

    emit_pextlb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pextlh ¶
    Source

    emit_pextlh :: emit_pextlh_r_r_r

    emit_pextlh_r_r_r ¶
    Source

    emit_pextlh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pextlw ¶
    Source

    emit_pextlw :: emit_pextlw_r_r_r

    emit_pextlw_r_r_r ¶
    Source

    emit_pextlw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pextub ¶
    Source

    emit_pextub :: emit_pextub_r_r_r

    emit_pextub_r_r_r ¶
    Source

    emit_pextub_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pextuh ¶
    Source

    emit_pextuh :: emit_pextuh_r_r_r

    emit_pextuh_r_r_r ¶
    Source

    emit_pextuh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pextuw ¶
    Source

    emit_pextuw :: emit_pextuw_r_r_r

    emit_pextuw_r_r_r ¶
    Source

    emit_pextuw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_phmadh ¶
    Source

    emit_phmadh :: emit_phmadh_r_r_r

    emit_phmadh_r_r_r ¶
    Source

    emit_phmadh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_phmsbh ¶
    Source

    emit_phmsbh :: emit_phmsbh_r_r_r

    emit_phmsbh_r_r_r ¶
    Source

    emit_phmsbh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pick_ph ¶
    Source

    emit_pick_ph :: emit_pick_ph_r_r_r

    emit_pick_ph_r_r_r ¶
    Source

    emit_pick_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pick_qb ¶
    Source

    emit_pick_qb :: emit_pick_qb_r_r_r

    emit_pick_qb_r_r_r ¶
    Source

    emit_pick_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pinth ¶
    Source

    emit_pinth :: emit_pinth_r_r_r

    emit_pinth_r_r_r ¶
    Source

    emit_pinth_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pintoh ¶
    Source

    emit_pintoh :: emit_pintoh_r_r_r

    emit_pintoh_r_r_r ¶
    Source

    emit_pintoh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pll_ps ¶
    Source

    emit_pll_ps :: emit_pll_ps_f_f_f

    emit_pll_ps_f_f_f ¶
    Source

    emit_pll_ps_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_plu_ps ¶
    Source

    emit_plu_ps :: emit_plu_ps_f_f_f

    emit_plu_ps_f_f_f ¶
    Source

    emit_plu_ps_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_plzcw ¶
    Source

    emit_plzcw :: emit_plzcw_r_r

    emit_plzcw_r_r ¶
    Source

    emit_plzcw_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_pmaddh ¶
    Source

    emit_pmaddh :: emit_pmaddh_r_r_r

    emit_pmaddh_r_r_r ¶
    Source

    emit_pmaddh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pmadduw ¶
    Source

    emit_pmadduw :: emit_pmadduw_r_r_r

    emit_pmadduw_r_r_r ¶
    Source

    emit_pmadduw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pmaddw ¶
    Source

    emit_pmaddw :: emit_pmaddw_r_r_r

    emit_pmaddw_r_r_r ¶
    Source

    emit_pmaddw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pmaxh ¶
    Source

    emit_pmaxh :: emit_pmaxh_r_r_r

    emit_pmaxh_r_r_r ¶
    Source

    emit_pmaxh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pmaxw ¶
    Source

    emit_pmaxw :: emit_pmaxw_r_r_r

    emit_pmaxw_r_r_r ¶
    Source

    emit_pmaxw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pmfhi ¶
    Source

    emit_pmfhi :: emit_pmfhi_r

    emit_pmfhi_r ¶
    Source

    emit_pmfhi_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_pmfhl_lh ¶
    Source

    emit_pmfhl_lh :: emit_pmfhl_lh_r

    emit_pmfhl_lh_r ¶
    Source

    emit_pmfhl_lh_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_pmfhl_lw ¶
    Source

    emit_pmfhl_lw :: emit_pmfhl_lw_r

    emit_pmfhl_lw_r ¶
    Source

    emit_pmfhl_lw_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_pmfhl_sh ¶
    Source

    emit_pmfhl_sh :: emit_pmfhl_sh_r

    emit_pmfhl_sh_r ¶
    Source

    emit_pmfhl_sh_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_pmfhl_slw ¶
    Source

    emit_pmfhl_slw :: emit_pmfhl_slw_r

    emit_pmfhl_slw_r ¶
    Source

    emit_pmfhl_slw_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_pmfhl_uw ¶
    Source

    emit_pmfhl_uw :: emit_pmfhl_uw_r

    emit_pmfhl_uw_r ¶
    Source

    emit_pmfhl_uw_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_pmflo ¶
    Source

    emit_pmflo :: emit_pmflo_r

    emit_pmflo_r ¶
    Source

    emit_pmflo_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_pminh ¶
    Source

    emit_pminh :: emit_pminh_r_r_r

    emit_pminh_r_r_r ¶
    Source

    emit_pminh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pminw ¶
    Source

    emit_pminw :: emit_pminw_r_r_r

    emit_pminw_r_r_r ¶
    Source

    emit_pminw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pmsubh ¶
    Source

    emit_pmsubh :: emit_pmsubh_r_r_r

    emit_pmsubh_r_r_r ¶
    Source

    emit_pmsubh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pmsubw ¶
    Source

    emit_pmsubw :: emit_pmsubw_r_r_r

    emit_pmsubw_r_r_r ¶
    Source

    emit_pmsubw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pmthi ¶
    Source

    emit_pmthi :: emit_pmthi_r

    emit_pmthi_r ¶
    Source

    emit_pmthi_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_pmthl_lw ¶
    Source

    emit_pmthl_lw :: emit_pmthl_lw_r

    emit_pmthl_lw_r ¶
    Source

    emit_pmthl_lw_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_pmtlo ¶
    Source

    emit_pmtlo :: emit_pmtlo_r

    emit_pmtlo_r ¶
    Source

    emit_pmtlo_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR) {…}

    emit_pmulth ¶
    Source

    emit_pmulth :: emit_pmulth_r_r_r

    emit_pmulth_r_r_r ¶
    Source

    emit_pmulth_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pmultuw ¶
    Source

    emit_pmultuw :: emit_pmultuw_r_r_r

    emit_pmultuw_r_r_r ¶
    Source

    emit_pmultuw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pmultw ¶
    Source

    emit_pmultw :: emit_pmultw_r_r_r

    emit_pmultw_r_r_r ¶
    Source

    emit_pmultw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pnor ¶
    Source

    emit_pnor :: emit_pnor_r_r_r

    emit_pnor_r_r_r ¶
    Source

    emit_pnor_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_por ¶
    Source

    emit_por :: emit_por_r_r_r

    emit_por_r_r_r ¶
    Source

    emit_por_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_ppac5 ¶
    Source

    emit_ppac5 :: emit_ppac5_r_r_r

    emit_ppac5_r_r_r ¶
    Source

    emit_ppac5_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_ppacb ¶
    Source

    emit_ppacb :: emit_ppacb_r_r_r

    emit_ppacb_r_r_r ¶
    Source

    emit_ppacb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_ppach ¶
    Source

    emit_ppach :: emit_ppach_r_r_r

    emit_ppach_r_r_r ¶
    Source

    emit_ppach_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_ppacw ¶
    Source

    emit_ppacw :: emit_ppacw_r_r_r

    emit_ppacw_r_r_r ¶
    Source

    emit_ppacw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_preceq_w_phl ¶
    Source

    emit_preceq_w_phl :: emit_preceq_w_phl_r_r

    emit_preceq_w_phl_r_r ¶
    Source

    emit_preceq_w_phl_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_preceq_w_phr ¶
    Source

    emit_preceq_w_phr :: emit_preceq_w_phr_r_r

    emit_preceq_w_phr_r_r ¶
    Source

    emit_preceq_w_phr_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_precequ_ph_qbl ¶
    Source

    emit_precequ_ph_qbl :: emit_precequ_ph_qbl_r_r

    emit_precequ_ph_qbl_r_r ¶
    Source

    emit_precequ_ph_qbl_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_precequ_ph_qbla ¶
    Source

    emit_precequ_ph_qbla :: emit_precequ_ph_qbla_r_r

    emit_precequ_ph_qbla_r_r ¶
    Source

    emit_precequ_ph_qbla_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_precequ_ph_qbr ¶
    Source

    emit_precequ_ph_qbr :: emit_precequ_ph_qbr_r_r

    emit_precequ_ph_qbr_r_r ¶
    Source

    emit_precequ_ph_qbr_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_precequ_ph_qbra ¶
    Source

    emit_precequ_ph_qbra :: emit_precequ_ph_qbra_r_r

    emit_precequ_ph_qbra_r_r ¶
    Source

    emit_precequ_ph_qbra_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_preceu_ph_qbl ¶
    Source

    emit_preceu_ph_qbl :: emit_preceu_ph_qbl_r_r

    emit_preceu_ph_qbl_r_r ¶
    Source

    emit_preceu_ph_qbl_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_preceu_ph_qbla ¶
    Source

    emit_preceu_ph_qbla :: emit_preceu_ph_qbla_r_r

    emit_preceu_ph_qbla_r_r ¶
    Source

    emit_preceu_ph_qbla_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_preceu_ph_qbr ¶
    Source

    emit_preceu_ph_qbr :: emit_preceu_ph_qbr_r_r

    emit_preceu_ph_qbr_r_r ¶
    Source

    emit_preceu_ph_qbr_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_preceu_ph_qbra ¶
    Source

    emit_preceu_ph_qbra :: emit_preceu_ph_qbra_r_r

    emit_preceu_ph_qbra_r_r ¶
    Source

    emit_preceu_ph_qbra_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_precrq_ph_w ¶
    Source

    emit_precrq_ph_w :: emit_precrq_ph_w_r_r_r

    emit_precrq_ph_w_r_r_r ¶
    Source

    emit_precrq_ph_w_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_precrq_qb_ph ¶
    Source

    emit_precrq_qb_ph :: emit_precrq_qb_ph_r_r_r

    emit_precrq_qb_ph_r_r_r ¶
    Source

    emit_precrq_qb_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_precrq_rs_ph_w ¶
    Source

    emit_precrq_rs_ph_w :: emit_precrq_rs_ph_w_r_r_r

    emit_precrq_rs_ph_w_r_r_r ¶
    Source

    emit_precrq_rs_ph_w_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_precrqu_s_qb_ph ¶
    Source

    emit_precrqu_s_qb_ph :: emit_precrqu_s_qb_ph_r_r_r

    emit_precrqu_s_qb_ph_r_r_r ¶
    Source

    emit_precrqu_s_qb_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pref ¶
    Source

    emit_pref :: emit_pref_i5_m

    emit_pref_i5_m ¶
    Source

    emit_pref_i5_m :: proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) {…}

    emit_prefx ¶
    Source

    emit_prefx :: emit_prefx_i5_r_r

    emit_prefx_i5_r_r ¶
    Source

    emit_prefx_i5_r_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR, src: GPR) {…}

    emit_prot3w ¶
    Source

    emit_prot3w :: emit_prot3w_r_r

    emit_prot3w_r_r ¶
    Source

    emit_prot3w_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_psllh ¶
    Source

    emit_psllh :: emit_psllh_r_r_i5

    emit_psllh_r_r_i5 ¶
    Source

    emit_psllh_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_psllvw ¶
    Source

    emit_psllvw :: emit_psllvw_r_r_r

    emit_psllvw_r_r_r ¶
    Source

    emit_psllvw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_psllw ¶
    Source

    emit_psllw :: emit_psllw_r_r_i5

    emit_psllw_r_r_i5 ¶
    Source

    emit_psllw_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_psrah ¶
    Source

    emit_psrah :: emit_psrah_r_r_i5

    emit_psrah_r_r_i5 ¶
    Source

    emit_psrah_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_psravw ¶
    Source

    emit_psravw :: emit_psravw_r_r_r

    emit_psravw_r_r_r ¶
    Source

    emit_psravw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_psraw ¶
    Source

    emit_psraw :: emit_psraw_r_r_i5

    emit_psraw_r_r_i5 ¶
    Source

    emit_psraw_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_psrlh ¶
    Source

    emit_psrlh :: emit_psrlh_r_r_i5

    emit_psrlh_r_r_i5 ¶
    Source

    emit_psrlh_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_psrlvw ¶
    Source

    emit_psrlvw :: emit_psrlvw_r_r_r

    emit_psrlvw_r_r_r ¶
    Source

    emit_psrlvw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_psrlw ¶
    Source

    emit_psrlw :: emit_psrlw_r_r_i5

    emit_psrlw_r_r_i5 ¶
    Source

    emit_psrlw_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_psubb ¶
    Source

    emit_psubb :: emit_psubb_r_r_r

    emit_psubb_r_r_r ¶
    Source

    emit_psubb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_psubh ¶
    Source

    emit_psubh :: emit_psubh_r_r_r

    emit_psubh_r_r_r ¶
    Source

    emit_psubh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_psubsb ¶
    Source

    emit_psubsb :: emit_psubsb_r_r_r

    emit_psubsb_r_r_r ¶
    Source

    emit_psubsb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_psubsh ¶
    Source

    emit_psubsh :: emit_psubsh_r_r_r

    emit_psubsh_r_r_r ¶
    Source

    emit_psubsh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_psubsw ¶
    Source

    emit_psubsw :: emit_psubsw_r_r_r

    emit_psubsw_r_r_r ¶
    Source

    emit_psubsw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_psubub ¶
    Source

    emit_psubub :: emit_psubub_r_r_r

    emit_psubub_r_r_r ¶
    Source

    emit_psubub_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_psubuh ¶
    Source

    emit_psubuh :: emit_psubuh_r_r_r

    emit_psubuh_r_r_r ¶
    Source

    emit_psubuh_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_psubuw ¶
    Source

    emit_psubuw :: emit_psubuw_r_r_r

    emit_psubuw_r_r_r ¶
    Source

    emit_psubuw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_psubw ¶
    Source

    emit_psubw :: emit_psubw_r_r_r

    emit_psubw_r_r_r ¶
    Source

    emit_psubw_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_pul_ps ¶
    Source

    emit_pul_ps :: emit_pul_ps_f_f_f

    emit_pul_ps_f_f_f ¶
    Source

    emit_pul_ps_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_puu_ps ¶
    Source

    emit_puu_ps :: emit_puu_ps_f_f_f

    emit_puu_ps_f_f_f ¶
    Source

    emit_puu_ps_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_pxor ¶
    Source

    emit_pxor :: emit_pxor_r_r_r

    emit_pxor_r_r_r ¶
    Source

    emit_pxor_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_qfsrv ¶
    Source

    emit_qfsrv :: emit_qfsrv_r_r_r

    emit_qfsrv_r_r_r ¶
    Source

    emit_qfsrv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_rddsp ¶
    Source

    emit_rddsp :: emit_rddsp_r_i5

    emit_rddsp_r_i5 ¶
    Source

    emit_rddsp_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_rdhwr ¶
    Source

    emit_rdhwr :: emit_rdhwr_r_r

    emit_rdhwr_r_r ¶
    Source

    emit_rdhwr_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_rdpgpr ¶
    Source

    emit_rdpgpr :: emit_rdpgpr_r_r

    emit_rdpgpr_r_r ¶
    Source

    emit_rdpgpr_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_recip_d ¶
    Source

    emit_recip_d :: emit_recip_d_f_f

    emit_recip_d_f_f ¶
    Source

    emit_recip_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_recip_s ¶
    Source

    emit_recip_s :: emit_recip_s_f_f

    emit_recip_s_f_f ¶
    Source

    emit_recip_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_repl_ph ¶
    Source

    emit_repl_ph :: emit_repl_ph_r_i5

    emit_repl_ph_r_i5 ¶
    Source

    emit_repl_ph_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_repl_qb ¶
    Source

    emit_repl_qb :: emit_repl_qb_r_i5

    emit_repl_qb_r_i5 ¶
    Source

    emit_repl_qb_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_replv_ph ¶
    Source

    emit_replv_ph :: emit_replv_ph_r_r

    emit_replv_ph_r_r ¶
    Source

    emit_replv_ph_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_replv_qb ¶
    Source

    emit_replv_qb :: emit_replv_qb_r_r

    emit_replv_qb_r_r ¶
    Source

    emit_replv_qb_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_rotr ¶
    Source

    emit_rotr :: emit_rotr_r_r_i5

    emit_rotr_r_r_i5 ¶
    Source

    emit_rotr_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_rotrv ¶
    Source

    emit_rotrv :: emit_rotrv_r_r_r

    emit_rotrv_r_r_r ¶
    Source

    emit_rotrv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_round_l_d ¶
    Source

    emit_round_l_d :: emit_round_l_d_f_f

    emit_round_l_d_f_f ¶
    Source

    emit_round_l_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_round_l_s ¶
    Source

    emit_round_l_s :: emit_round_l_s_f_f

    emit_round_l_s_f_f ¶
    Source

    emit_round_l_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_round_w_d ¶
    Source

    emit_round_w_d :: emit_round_w_d_f_f

    emit_round_w_d_f_f ¶
    Source

    emit_round_w_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_round_w_s ¶
    Source

    emit_round_w_s :: emit_round_w_s_f_f

    emit_round_w_s_f_f ¶
    Source

    emit_round_w_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_rsqrt_d ¶
    Source

    emit_rsqrt_d :: emit_rsqrt_d_f_f

    emit_rsqrt_d_f_f ¶
    Source

    emit_rsqrt_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_rsqrt_s ¶
    Source

    emit_rsqrt_s :: emit_rsqrt_s_f_f

    emit_rsqrt_s_f_f ¶
    Source

    emit_rsqrt_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_rtps ¶
    Source

    emit_rtps :: emit_rtps_none

    emit_rtps_none ¶
    Source

    emit_rtps_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_rtpt ¶
    Source

    emit_rtpt :: emit_rtpt_none

    emit_rtpt_none ¶
    Source

    emit_rtpt_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_sb ¶
    Source

    emit_sb :: emit_sb_r_m

    emit_sb_r_m ¶
    Source

    emit_sb_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_sc ¶
    Source

    emit_sc :: emit_sc_r_m

    emit_sc_r_m ¶
    Source

    emit_sc_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_scd ¶
    Source

    emit_scd :: emit_scd_r_m

    emit_scd_r_m ¶
    Source

    emit_scd_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_sd ¶
    Source

    emit_sd :: emit_sd_r_m

    emit_sd_r_m ¶
    Source

    emit_sd_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_sdbbp ¶
    Source

    emit_sdbbp :: emit_sdbbp_i20

    emit_sdbbp_i20 ¶
    Source

    emit_sdbbp_i20 :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

    emit_sdc1 ¶
    Source

    emit_sdc1 :: emit_sdc1_f_m

    emit_sdc1_f_m ¶
    Source

    emit_sdc1_f_m :: proc(instructions: ^[dynamic]Instruction, dst: FPR, mem: Memory) {…}

    emit_sdc2 ¶
    Source

    emit_sdc2 :: emit_sdc2_c2_m

    emit_sdc2_c2_m ¶
    Source

    emit_sdc2_c2_m :: proc(instructions: ^[dynamic]Instruction, dst: GTE_DataReg, mem: Memory) {…}

    emit_sdl ¶
    Source

    emit_sdl :: emit_sdl_r_m

    emit_sdl_r_m ¶
    Source

    emit_sdl_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_sdr ¶
    Source

    emit_sdr :: emit_sdr_r_m

    emit_sdr_r_m ¶
    Source

    emit_sdr_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_sdxc1 ¶
    Source

    emit_sdxc1 :: emit_sdxc1_f_r_r

    emit_sdxc1_f_r_r ¶
    Source

    emit_sdxc1_f_r_r :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: GPR, src2: GPR) {…}

    emit_seb ¶
    Source

    emit_seb :: emit_seb_r_r

    emit_seb_r_r ¶
    Source

    emit_seb_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_seh ¶
    Source

    emit_seh :: emit_seh_r_r

    emit_seh_r_r ¶
    Source

    emit_seh_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_seleqz ¶
    Source

    emit_seleqz :: emit_seleqz_r_r_r

    emit_seleqz_r_r_r ¶
    Source

    emit_seleqz_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_selnez ¶
    Source

    emit_selnez :: emit_selnez_r_r_r

    emit_selnez_r_r_r ¶
    Source

    emit_selnez_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_sh ¶
    Source

    emit_sh :: emit_sh_r_m

    emit_sh_r_m ¶
    Source

    emit_sh_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_shf_b ¶
    Source

    emit_shf_b :: emit_shf_b_w_w_i5

    emit_shf_b_w_w_i5 ¶
    Source

    emit_shf_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_shf_h ¶
    Source

    emit_shf_h :: emit_shf_h_w_w_i5

    emit_shf_h_w_w_i5 ¶
    Source

    emit_shf_h_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_shf_w ¶
    Source

    emit_shf_w :: emit_shf_w_w_w_i5

    emit_shf_w_w_w_i5 ¶
    Source

    emit_shf_w_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_shilo ¶
    Source

    emit_shilo :: emit_shilo_i5_i5

    emit_shilo_i5_i5 ¶
    Source

    emit_shilo_i5_i5 :: proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) {…}

    emit_shilov ¶
    Source

    emit_shilov :: emit_shilov_i5_r

    emit_shilov_i5_r ¶
    Source

    emit_shilov_i5_r :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: GPR) {…}

    emit_shll_ph ¶
    Source

    emit_shll_ph :: emit_shll_ph_r_r_i5

    emit_shll_ph_r_r_i5 ¶
    Source

    emit_shll_ph_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_shll_qb ¶
    Source

    emit_shll_qb :: emit_shll_qb_r_r_i5

    emit_shll_qb_r_r_i5 ¶
    Source

    emit_shll_qb_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_shll_s_ph ¶
    Source

    emit_shll_s_ph :: emit_shll_s_ph_r_r_i5

    emit_shll_s_ph_r_r_i5 ¶
    Source

    emit_shll_s_ph_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_shll_s_w ¶
    Source

    emit_shll_s_w :: emit_shll_s_w_r_r_i5

    emit_shll_s_w_r_r_i5 ¶
    Source

    emit_shll_s_w_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_shllv_ph ¶
    Source

    emit_shllv_ph :: emit_shllv_ph_r_r_r

    emit_shllv_ph_r_r_r ¶
    Source

    emit_shllv_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_shllv_qb ¶
    Source

    emit_shllv_qb :: emit_shllv_qb_r_r_r

    emit_shllv_qb_r_r_r ¶
    Source

    emit_shllv_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_shllv_s_ph ¶
    Source

    emit_shllv_s_ph :: emit_shllv_s_ph_r_r_r

    emit_shllv_s_ph_r_r_r ¶
    Source

    emit_shllv_s_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_shllv_s_w ¶
    Source

    emit_shllv_s_w :: emit_shllv_s_w_r_r_r

    emit_shllv_s_w_r_r_r ¶
    Source

    emit_shllv_s_w_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_shra_ph ¶
    Source

    emit_shra_ph :: emit_shra_ph_r_r_i5

    emit_shra_ph_r_r_i5 ¶
    Source

    emit_shra_ph_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_shra_qb ¶
    Source

    emit_shra_qb :: emit_shra_qb_r_r_i5

    emit_shra_qb_r_r_i5 ¶
    Source

    emit_shra_qb_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_shra_r_ph ¶
    Source

    emit_shra_r_ph :: emit_shra_r_ph_r_r_i5

    emit_shra_r_ph_r_r_i5 ¶
    Source

    emit_shra_r_ph_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_shra_r_qb ¶
    Source

    emit_shra_r_qb :: emit_shra_r_qb_r_r_i5

    emit_shra_r_qb_r_r_i5 ¶
    Source

    emit_shra_r_qb_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_shra_r_w ¶
    Source

    emit_shra_r_w :: emit_shra_r_w_r_r_i5

    emit_shra_r_w_r_r_i5 ¶
    Source

    emit_shra_r_w_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_shrav_ph ¶
    Source

    emit_shrav_ph :: emit_shrav_ph_r_r_r

    emit_shrav_ph_r_r_r ¶
    Source

    emit_shrav_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_shrav_qb ¶
    Source

    emit_shrav_qb :: emit_shrav_qb_r_r_r

    emit_shrav_qb_r_r_r ¶
    Source

    emit_shrav_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_shrav_r_ph ¶
    Source

    emit_shrav_r_ph :: emit_shrav_r_ph_r_r_r

    emit_shrav_r_ph_r_r_r ¶
    Source

    emit_shrav_r_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_shrav_r_qb ¶
    Source

    emit_shrav_r_qb :: emit_shrav_r_qb_r_r_r

    emit_shrav_r_qb_r_r_r ¶
    Source

    emit_shrav_r_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_shrav_r_w ¶
    Source

    emit_shrav_r_w :: emit_shrav_r_w_r_r_r

    emit_shrav_r_w_r_r_r ¶
    Source

    emit_shrav_r_w_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_shrl_ph ¶
    Source

    emit_shrl_ph :: emit_shrl_ph_r_r_i5

    emit_shrl_ph_r_r_i5 ¶
    Source

    emit_shrl_ph_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_shrl_qb ¶
    Source

    emit_shrl_qb :: emit_shrl_qb_r_r_i5

    emit_shrl_qb_r_r_i5 ¶
    Source

    emit_shrl_qb_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_shrlv_ph ¶
    Source

    emit_shrlv_ph :: emit_shrlv_ph_r_r_r

    emit_shrlv_ph_r_r_r ¶
    Source

    emit_shrlv_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_shrlv_qb ¶
    Source

    emit_shrlv_qb :: emit_shrlv_qb_r_r_r

    emit_shrlv_qb_r_r_r ¶
    Source

    emit_shrlv_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_sigrie ¶
    Source

    emit_sigrie :: emit_sigrie_u16

    emit_sigrie_u16 ¶
    Source

    emit_sigrie_u16 :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

    emit_sld_b ¶
    Source

    emit_sld_b :: emit_sld_b_w_w_r

    emit_sld_b_w_w_r ¶
    Source

    emit_sld_b_w_w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) {…}

    emit_sld_d ¶
    Source

    emit_sld_d :: emit_sld_d_w_w_r

    emit_sld_d_w_w_r ¶
    Source

    emit_sld_d_w_w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) {…}

    emit_sld_h ¶
    Source

    emit_sld_h :: emit_sld_h_w_w_r

    emit_sld_h_w_w_r ¶
    Source

    emit_sld_h_w_w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) {…}

    emit_sld_w ¶
    Source

    emit_sld_w :: emit_sld_w_w_w_r

    emit_sld_w_w_w_r ¶
    Source

    emit_sld_w_w_w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) {…}

    emit_sldi_b ¶
    Source

    emit_sldi_b :: emit_sldi_b_w_w_i5

    emit_sldi_b_w_w_i5 ¶
    Source

    emit_sldi_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_sldi_d ¶
    Source

    emit_sldi_d :: emit_sldi_d_w_w_i5

    emit_sldi_d_w_w_i5 ¶
    Source

    emit_sldi_d_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_sldi_h ¶
    Source

    emit_sldi_h :: emit_sldi_h_w_w_i5

    emit_sldi_h_w_w_i5 ¶
    Source

    emit_sldi_h_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_sldi_w ¶
    Source

    emit_sldi_w :: emit_sldi_w_w_w_i5

    emit_sldi_w_w_w_i5 ¶
    Source

    emit_sldi_w_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_sll ¶
    Source

    emit_sll :: emit_sll_r_r_i5

    emit_sll_b ¶
    Source

    emit_sll_b :: emit_sll_b_w_w_w

    emit_sll_b_w_w_w ¶
    Source

    emit_sll_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_sll_d ¶
    Source

    emit_sll_d :: emit_sll_d_w_w_w

    emit_sll_d_w_w_w ¶
    Source

    emit_sll_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_sll_h ¶
    Source

    emit_sll_h :: emit_sll_h_w_w_w

    emit_sll_h_w_w_w ¶
    Source

    emit_sll_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_sll_r_r_i5 ¶
    Source

    emit_sll_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_sll_w ¶
    Source

    emit_sll_w :: emit_sll_w_w_w_w

    emit_sll_w_w_w_w ¶
    Source

    emit_sll_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_slli_b ¶
    Source

    emit_slli_b :: emit_slli_b_w_w_i5

    emit_slli_b_w_w_i5 ¶
    Source

    emit_slli_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_slli_d ¶
    Source

    emit_slli_d :: emit_slli_d_w_w_i5

    emit_slli_d_w_w_i5 ¶
    Source

    emit_slli_d_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_slli_h ¶
    Source

    emit_slli_h :: emit_slli_h_w_w_i5

    emit_slli_h_w_w_i5 ¶
    Source

    emit_slli_h_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_slli_w ¶
    Source

    emit_slli_w :: emit_slli_w_w_w_i5

    emit_slli_w_w_w_i5 ¶
    Source

    emit_slli_w_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_sllv ¶
    Source

    emit_sllv :: emit_sllv_r_r_r

    emit_sllv_r_r_r ¶
    Source

    emit_sllv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_slt ¶
    Source

    emit_slt :: emit_slt_r_r_r

    emit_slt_r_r_r ¶
    Source

    emit_slt_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_slti ¶
    Source

    emit_slti :: emit_slti_r_r_i16

    emit_slti_r_r_i16 ¶
    Source

    emit_slti_r_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_sltiu ¶
    Source

    emit_sltiu :: emit_sltiu_r_r_i16

    emit_sltiu_r_r_i16 ¶
    Source

    emit_sltiu_r_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_sltu ¶
    Source

    emit_sltu :: emit_sltu_r_r_r

    emit_sltu_r_r_r ¶
    Source

    emit_sltu_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_splat_b ¶
    Source

    emit_splat_b :: emit_splat_b_w_w_r

    emit_splat_b_w_w_r ¶
    Source

    emit_splat_b_w_w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) {…}

    emit_splat_d ¶
    Source

    emit_splat_d :: emit_splat_d_w_w_r

    emit_splat_d_w_w_r ¶
    Source

    emit_splat_d_w_w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) {…}

    emit_splat_h ¶
    Source

    emit_splat_h :: emit_splat_h_w_w_r

    emit_splat_h_w_w_r ¶
    Source

    emit_splat_h_w_w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) {…}

    emit_splat_w ¶
    Source

    emit_splat_w :: emit_splat_w_w_w_r

    emit_splat_w_w_w_r ¶
    Source

    emit_splat_w_w_w_r :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) {…}

    emit_splati_b ¶
    Source

    emit_splati_b :: emit_splati_b_w_w_i5

    emit_splati_b_w_w_i5 ¶
    Source

    emit_splati_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_splati_d ¶
    Source

    emit_splati_d :: emit_splati_d_w_w_i5

    emit_splati_d_w_w_i5 ¶
    Source

    emit_splati_d_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_splati_h ¶
    Source

    emit_splati_h :: emit_splati_h_w_w_i5

    emit_splati_h_w_w_i5 ¶
    Source

    emit_splati_h_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_splati_w ¶
    Source

    emit_splati_w :: emit_splati_w_w_w_i5

    emit_splati_w_w_w_i5 ¶
    Source

    emit_splati_w_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_sq ¶
    Source

    emit_sq :: emit_sq_r_m

    emit_sq_r_m ¶
    Source

    emit_sq_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_sqc2 ¶
    Source

    emit_sqc2 :: emit_sqc2_c2_m

    emit_sqc2_c2_m ¶
    Source

    emit_sqc2_c2_m :: proc(instructions: ^[dynamic]Instruction, dst: GTE_DataReg, mem: Memory) {…}

    emit_sqr_gte ¶
    Source

    emit_sqr_gte :: emit_sqr_gte_none

    emit_sqr_gte_none ¶
    Source

    emit_sqr_gte_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_sqrt_d ¶
    Source

    emit_sqrt_d :: emit_sqrt_d_f_f

    emit_sqrt_d_f_f ¶
    Source

    emit_sqrt_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_sqrt_s ¶
    Source

    emit_sqrt_s :: emit_sqrt_s_f_f

    emit_sqrt_s_f_f ¶
    Source

    emit_sqrt_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_sra ¶
    Source

    emit_sra :: emit_sra_r_r_i5

    emit_sra_b ¶
    Source

    emit_sra_b :: emit_sra_b_w_w_w

    emit_sra_b_w_w_w ¶
    Source

    emit_sra_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_sra_d ¶
    Source

    emit_sra_d :: emit_sra_d_w_w_w

    emit_sra_d_w_w_w ¶
    Source

    emit_sra_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_sra_h ¶
    Source

    emit_sra_h :: emit_sra_h_w_w_w

    emit_sra_h_w_w_w ¶
    Source

    emit_sra_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_sra_r_r_i5 ¶
    Source

    emit_sra_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_sra_w ¶
    Source

    emit_sra_w :: emit_sra_w_w_w_w

    emit_sra_w_w_w_w ¶
    Source

    emit_sra_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_srai_b ¶
    Source

    emit_srai_b :: emit_srai_b_w_w_i5

    emit_srai_b_w_w_i5 ¶
    Source

    emit_srai_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_srai_d ¶
    Source

    emit_srai_d :: emit_srai_d_w_w_i5

    emit_srai_d_w_w_i5 ¶
    Source

    emit_srai_d_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_srai_h ¶
    Source

    emit_srai_h :: emit_srai_h_w_w_i5

    emit_srai_h_w_w_i5 ¶
    Source

    emit_srai_h_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_srai_w ¶
    Source

    emit_srai_w :: emit_srai_w_w_w_i5

    emit_srai_w_w_w_i5 ¶
    Source

    emit_srai_w_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_srav ¶
    Source

    emit_srav :: emit_srav_r_r_r

    emit_srav_r_r_r ¶
    Source

    emit_srav_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_srl ¶
    Source

    emit_srl :: emit_srl_r_r_i5

    emit_srl_b ¶
    Source

    emit_srl_b :: emit_srl_b_w_w_w

    emit_srl_b_w_w_w ¶
    Source

    emit_srl_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_srl_d ¶
    Source

    emit_srl_d :: emit_srl_d_w_w_w

    emit_srl_d_w_w_w ¶
    Source

    emit_srl_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_srl_h ¶
    Source

    emit_srl_h :: emit_srl_h_w_w_w

    emit_srl_h_w_w_w ¶
    Source

    emit_srl_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_srl_r_r_i5 ¶
    Source

    emit_srl_r_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    emit_srl_w ¶
    Source

    emit_srl_w :: emit_srl_w_w_w_w

    emit_srl_w_w_w_w ¶
    Source

    emit_srl_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_srli_b ¶
    Source

    emit_srli_b :: emit_srli_b_w_w_i5

    emit_srli_b_w_w_i5 ¶
    Source

    emit_srli_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_srli_d ¶
    Source

    emit_srli_d :: emit_srli_d_w_w_i5

    emit_srli_d_w_w_i5 ¶
    Source

    emit_srli_d_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_srli_h ¶
    Source

    emit_srli_h :: emit_srli_h_w_w_i5

    emit_srli_h_w_w_i5 ¶
    Source

    emit_srli_h_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_srli_w ¶
    Source

    emit_srli_w :: emit_srli_w_w_w_i5

    emit_srli_w_w_w_i5 ¶
    Source

    emit_srli_w_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_srlv ¶
    Source

    emit_srlv :: emit_srlv_r_r_r

    emit_srlv_r_r_r ¶
    Source

    emit_srlv_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_ssnop ¶
    Source

    emit_ssnop :: emit_ssnop_none

    emit_ssnop_none ¶
    Source

    emit_ssnop_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_st_b ¶
    Source

    emit_st_b :: emit_st_b_w_m

    emit_st_b_w_m ¶
    Source

    emit_st_b_w_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_st_d ¶
    Source

    emit_st_d :: emit_st_d_w_m

    emit_st_d_w_m ¶
    Source

    emit_st_d_w_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_st_h ¶
    Source

    emit_st_h :: emit_st_h_w_m

    emit_st_h_w_m ¶
    Source

    emit_st_h_w_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_st_w ¶
    Source

    emit_st_w :: emit_st_w_w_m

    emit_st_w_w_m ¶
    Source

    emit_st_w_w_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_sub ¶
    Source

    emit_sub :: emit_sub_r_r_r

    emit_sub_d ¶
    Source

    emit_sub_d :: emit_sub_d_f_f_f

    emit_sub_d_f_f_f ¶
    Source

    emit_sub_d_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_sub_ps ¶
    Source

    emit_sub_ps :: emit_sub_ps_f_f_f

    emit_sub_ps_f_f_f ¶
    Source

    emit_sub_ps_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_sub_r_r_r ¶
    Source

    emit_sub_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_sub_s ¶
    Source

    emit_sub_s :: emit_sub_s_f_f_f

    emit_sub_s_f_f_f ¶
    Source

    emit_sub_s_f_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR, src2: FPR) {…}

    emit_subq_ph ¶
    Source

    emit_subq_ph :: emit_subq_ph_r_r_r

    emit_subq_ph_r_r_r ¶
    Source

    emit_subq_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_subq_s_ph ¶
    Source

    emit_subq_s_ph :: emit_subq_s_ph_r_r_r

    emit_subq_s_ph_r_r_r ¶
    Source

    emit_subq_s_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_subq_s_w ¶
    Source

    emit_subq_s_w :: emit_subq_s_w_r_r_r

    emit_subq_s_w_r_r_r ¶
    Source

    emit_subq_s_w_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_subs_s_b ¶
    Source

    emit_subs_s_b :: emit_subs_s_b_w_w_w

    emit_subs_s_b_w_w_w ¶
    Source

    emit_subs_s_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_subs_s_d ¶
    Source

    emit_subs_s_d :: emit_subs_s_d_w_w_w

    emit_subs_s_d_w_w_w ¶
    Source

    emit_subs_s_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_subs_s_h ¶
    Source

    emit_subs_s_h :: emit_subs_s_h_w_w_w

    emit_subs_s_h_w_w_w ¶
    Source

    emit_subs_s_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_subs_s_w ¶
    Source

    emit_subs_s_w :: emit_subs_s_w_w_w_w

    emit_subs_s_w_w_w_w ¶
    Source

    emit_subs_s_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_subs_u_b ¶
    Source

    emit_subs_u_b :: emit_subs_u_b_w_w_w

    emit_subs_u_b_w_w_w ¶
    Source

    emit_subs_u_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_subs_u_d ¶
    Source

    emit_subs_u_d :: emit_subs_u_d_w_w_w

    emit_subs_u_d_w_w_w ¶
    Source

    emit_subs_u_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_subs_u_h ¶
    Source

    emit_subs_u_h :: emit_subs_u_h_w_w_w

    emit_subs_u_h_w_w_w ¶
    Source

    emit_subs_u_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_subs_u_w ¶
    Source

    emit_subs_u_w :: emit_subs_u_w_w_w_w

    emit_subs_u_w_w_w_w ¶
    Source

    emit_subs_u_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_subu ¶
    Source

    emit_subu :: emit_subu_r_r_r

    emit_subu_ph ¶
    Source

    emit_subu_ph :: emit_subu_ph_r_r_r

    emit_subu_ph_r_r_r ¶
    Source

    emit_subu_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_subu_qb ¶
    Source

    emit_subu_qb :: emit_subu_qb_r_r_r

    emit_subu_qb_r_r_r ¶
    Source

    emit_subu_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_subu_r_r_r ¶
    Source

    emit_subu_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_subu_s_ph ¶
    Source

    emit_subu_s_ph :: emit_subu_s_ph_r_r_r

    emit_subu_s_ph_r_r_r ¶
    Source

    emit_subu_s_ph_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_subu_s_qb ¶
    Source

    emit_subu_s_qb :: emit_subu_s_qb_r_r_r

    emit_subu_s_qb_r_r_r ¶
    Source

    emit_subu_s_qb_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_subv_b ¶
    Source

    emit_subv_b :: emit_subv_b_w_w_w

    emit_subv_b_w_w_w ¶
    Source

    emit_subv_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_subv_d ¶
    Source

    emit_subv_d :: emit_subv_d_w_w_w

    emit_subv_d_w_w_w ¶
    Source

    emit_subv_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_subv_h ¶
    Source

    emit_subv_h :: emit_subv_h_w_w_w

    emit_subv_h_w_w_w ¶
    Source

    emit_subv_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_subv_w ¶
    Source

    emit_subv_w :: emit_subv_w_w_w_w

    emit_subv_w_w_w_w ¶
    Source

    emit_subv_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_sv_q ¶
    Source

    emit_sv_q :: emit_sv_q_vq_m

    emit_sv_q_vq_m ¶
    Source

    emit_sv_q_vq_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_sv_s ¶
    Source

    emit_sv_s :: emit_sv_s_vs_m

    emit_sv_s_vs_m ¶
    Source

    emit_sv_s_vs_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_svl_q ¶
    Source

    emit_svl_q :: emit_svl_q_vq_m

    emit_svl_q_vq_m ¶
    Source

    emit_svl_q_vq_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_svr_q ¶
    Source

    emit_svr_q :: emit_svr_q_vq_m

    emit_svr_q_vq_m ¶
    Source

    emit_svr_q_vq_m :: proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) {…}

    emit_sw ¶
    Source

    emit_sw :: emit_sw_r_m

    emit_sw_r_m ¶
    Source

    emit_sw_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_swc1 ¶
    Source

    emit_swc1 :: emit_swc1_f_m

    emit_swc1_f_m ¶
    Source

    emit_swc1_f_m :: proc(instructions: ^[dynamic]Instruction, dst: FPR, mem: Memory) {…}

    emit_swc2 ¶
    Source

    emit_swc2 :: emit_swc2_c2_m

    emit_swc2_c2_m ¶
    Source

    emit_swc2_c2_m :: proc(instructions: ^[dynamic]Instruction, dst: GTE_DataReg, mem: Memory) {…}

    emit_swl ¶
    Source

    emit_swl :: emit_swl_r_m

    emit_swl_r_m ¶
    Source

    emit_swl_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_swr ¶
    Source

    emit_swr :: emit_swr_r_m

    emit_swr_r_m ¶
    Source

    emit_swr_r_m :: proc(instructions: ^[dynamic]Instruction, dst: GPR, mem: Memory) {…}

    emit_swxc1 ¶
    Source

    emit_swxc1 :: emit_swxc1_f_r_r

    emit_swxc1_f_r_r ¶
    Source

    emit_swxc1_f_r_r :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: GPR, src2: GPR) {…}

    emit_sync ¶
    Source

    emit_sync :: emit_sync_i5

    emit_sync_i5 ¶
    Source

    emit_sync_i5 :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

    emit_syscall ¶
    Source

    emit_syscall :: emit_syscall_i20

    emit_syscall_i20 ¶
    Source

    emit_syscall_i20 :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

    emit_teq ¶
    Source

    emit_teq :: emit_teq_r_r

    emit_teq_r_r ¶
    Source

    emit_teq_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_teqi ¶
    Source

    emit_teqi :: emit_teqi_r_i16

    emit_teqi_r_i16 ¶
    Source

    emit_teqi_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_tge ¶
    Source

    emit_tge :: emit_tge_r_r

    emit_tge_r_r ¶
    Source

    emit_tge_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_tgei ¶
    Source

    emit_tgei :: emit_tgei_r_i16

    emit_tgei_r_i16 ¶
    Source

    emit_tgei_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_tgeiu ¶
    Source

    emit_tgeiu :: emit_tgeiu_r_i16

    emit_tgeiu_r_i16 ¶
    Source

    emit_tgeiu_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_tgeu ¶
    Source

    emit_tgeu :: emit_tgeu_r_r

    emit_tgeu_r_r ¶
    Source

    emit_tgeu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_tlbp ¶
    Source

    emit_tlbp :: emit_tlbp_none

    emit_tlbp_none ¶
    Source

    emit_tlbp_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_tlbr ¶
    Source

    emit_tlbr :: emit_tlbr_none

    emit_tlbr_none ¶
    Source

    emit_tlbr_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_tlbwi ¶
    Source

    emit_tlbwi :: emit_tlbwi_none

    emit_tlbwi_none ¶
    Source

    emit_tlbwi_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_tlbwr ¶
    Source

    emit_tlbwr :: emit_tlbwr_none

    emit_tlbwr_none ¶
    Source

    emit_tlbwr_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_tlt ¶
    Source

    emit_tlt :: emit_tlt_r_r

    emit_tlt_r_r ¶
    Source

    emit_tlt_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_tlti ¶
    Source

    emit_tlti :: emit_tlti_r_i16

    emit_tlti_r_i16 ¶
    Source

    emit_tlti_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_tltiu ¶
    Source

    emit_tltiu :: emit_tltiu_r_i16

    emit_tltiu_r_i16 ¶
    Source

    emit_tltiu_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_tltu ¶
    Source

    emit_tltu :: emit_tltu_r_r

    emit_tltu_r_r ¶
    Source

    emit_tltu_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_tne ¶
    Source

    emit_tne :: emit_tne_r_r

    emit_tne_r_r ¶
    Source

    emit_tne_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_tnei ¶
    Source

    emit_tnei :: emit_tnei_r_i16

    emit_tnei_r_i16 ¶
    Source

    emit_tnei_r_i16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_trunc_l_d ¶
    Source

    emit_trunc_l_d :: emit_trunc_l_d_f_f

    emit_trunc_l_d_f_f ¶
    Source

    emit_trunc_l_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_trunc_l_s ¶
    Source

    emit_trunc_l_s :: emit_trunc_l_s_f_f

    emit_trunc_l_s_f_f ¶
    Source

    emit_trunc_l_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_trunc_w_d ¶
    Source

    emit_trunc_w_d :: emit_trunc_w_d_f_f

    emit_trunc_w_d_f_f ¶
    Source

    emit_trunc_w_d_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_trunc_w_s ¶
    Source

    emit_trunc_w_s :: emit_trunc_w_s_f_f

    emit_trunc_w_s_f_f ¶
    Source

    emit_trunc_w_s_f_f :: proc(instructions: ^[dynamic]Instruction, dst: FPR, src: FPR) {…}

    emit_vabs_p ¶
    Source

    emit_vabs_p :: emit_vabs_p_vp_vp

    emit_vabs_p_vp_vp ¶
    Source

    emit_vabs_p_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vabs_q ¶
    Source

    emit_vabs_q :: emit_vabs_q_vq_vq

    emit_vabs_q_vq_vq ¶
    Source

    emit_vabs_q_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vabs_s ¶
    Source

    emit_vabs_s :: emit_vabs_s_vs_vs

    emit_vabs_s_vs_vs ¶
    Source

    emit_vabs_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vabs_t ¶
    Source

    emit_vabs_t :: emit_vabs_t_vt_vt

    emit_vabs_t_vt_vt ¶
    Source

    emit_vabs_t_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vadd_p ¶
    Source

    emit_vadd_p :: emit_vadd_p_vp_vp_vp

    emit_vadd_p_vp_vp_vp ¶
    Source

    emit_vadd_p_vp_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vadd_q ¶
    Source

    emit_vadd_q :: emit_vadd_q_vq_vq_vq

    emit_vadd_q_vq_vq_vq ¶
    Source

    emit_vadd_q_vq_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vadd_s ¶
    Source

    emit_vadd_s :: emit_vadd_s_vs_vs_vs

    emit_vadd_s_vs_vs_vs ¶
    Source

    emit_vadd_s_vs_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vadd_t ¶
    Source

    emit_vadd_t :: emit_vadd_t_vt_vt_vt

    emit_vadd_t_vt_vt_vt ¶
    Source

    emit_vadd_t_vt_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vasin_s ¶
    Source

    emit_vasin_s :: emit_vasin_s_vs_vs

    emit_vasin_s_vs_vs ¶
    Source

    emit_vasin_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vavg_p ¶
    Source

    emit_vavg_p :: emit_vavg_p_vs_vp

    emit_vavg_p_vs_vp ¶
    Source

    emit_vavg_p_vs_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vavg_q ¶
    Source

    emit_vavg_q :: emit_vavg_q_vs_vq

    emit_vavg_q_vs_vq ¶
    Source

    emit_vavg_q_vs_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vavg_t ¶
    Source

    emit_vavg_t :: emit_vavg_t_vs_vt

    emit_vavg_t_vs_vt ¶
    Source

    emit_vavg_t_vs_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vcmp_p ¶
    Source

    emit_vcmp_p :: emit_vcmp_p_i5_vp_vp

    emit_vcmp_p_i5_vp_vp ¶
    Source

    emit_vcmp_p_i5_vp_vp :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) {…}

    emit_vcmp_q ¶
    Source

    emit_vcmp_q :: emit_vcmp_q_i5_vq_vq

    emit_vcmp_q_i5_vq_vq ¶
    Source

    emit_vcmp_q_i5_vq_vq :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) {…}

    emit_vcmp_s ¶
    Source

    emit_vcmp_s :: emit_vcmp_s_i5_vs_vs

    emit_vcmp_s_i5_vs_vs ¶
    Source

    emit_vcmp_s_i5_vs_vs :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) {…}

    emit_vcmp_t ¶
    Source

    emit_vcmp_t :: emit_vcmp_t_i5_vt_vt

    emit_vcmp_t_i5_vt_vt ¶
    Source

    emit_vcmp_t_i5_vt_vt :: proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) {…}

    emit_vcos_s ¶
    Source

    emit_vcos_s :: emit_vcos_s_vs_vs

    emit_vcos_s_vs_vs ¶
    Source

    emit_vcos_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vcrs_t ¶
    Source

    emit_vcrs_t :: emit_vcrs_t_vt_vt_vt

    emit_vcrs_t_vt_vt_vt ¶
    Source

    emit_vcrs_t_vt_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vcrsp_t ¶
    Source

    emit_vcrsp_t :: emit_vcrsp_t_vt_vt_vt

    emit_vcrsp_t_vt_vt_vt ¶
    Source

    emit_vcrsp_t_vt_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vcst_p ¶
    Source

    emit_vcst_p :: emit_vcst_p_vp_i5

    emit_vcst_p_vp_i5 ¶
    Source

    emit_vcst_p_vp_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

    emit_vcst_q ¶
    Source

    emit_vcst_q :: emit_vcst_q_vq_i5

    emit_vcst_q_vq_i5 ¶
    Source

    emit_vcst_q_vq_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

    emit_vcst_s ¶
    Source

    emit_vcst_s :: emit_vcst_s_vs_i5

    emit_vcst_s_vs_i5 ¶
    Source

    emit_vcst_s_vs_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

    emit_vcst_t ¶
    Source

    emit_vcst_t :: emit_vcst_t_vt_i5

    emit_vcst_t_vt_i5 ¶
    Source

    emit_vcst_t_vt_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

    emit_vdiv_p ¶
    Source

    emit_vdiv_p :: emit_vdiv_p_vp_vp_vp

    emit_vdiv_p_vp_vp_vp ¶
    Source

    emit_vdiv_p_vp_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vdiv_q ¶
    Source

    emit_vdiv_q :: emit_vdiv_q_vq_vq_vq

    emit_vdiv_q_vq_vq_vq ¶
    Source

    emit_vdiv_q_vq_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vdiv_s ¶
    Source

    emit_vdiv_s :: emit_vdiv_s_vs_vs_vs

    emit_vdiv_s_vs_vs_vs ¶
    Source

    emit_vdiv_s_vs_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vdiv_t ¶
    Source

    emit_vdiv_t :: emit_vdiv_t_vt_vt_vt

    emit_vdiv_t_vt_vt_vt ¶
    Source

    emit_vdiv_t_vt_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vdot_p ¶
    Source

    emit_vdot_p :: emit_vdot_p_vs_vp_vp

    emit_vdot_p_vs_vp_vp ¶
    Source

    emit_vdot_p_vs_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vdot_q ¶
    Source

    emit_vdot_q :: emit_vdot_q_vs_vq_vq

    emit_vdot_q_vs_vq_vq ¶
    Source

    emit_vdot_q_vs_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vdot_t ¶
    Source

    emit_vdot_t :: emit_vdot_t_vs_vt_vt

    emit_vdot_t_vs_vt_vt ¶
    Source

    emit_vdot_t_vs_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vexp2_s ¶
    Source

    emit_vexp2_s :: emit_vexp2_s_vs_vs

    emit_vexp2_s_vs_vs ¶
    Source

    emit_vexp2_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vf2h_p ¶
    Source

    emit_vf2h_p :: emit_vf2h_p_vs_vp

    emit_vf2h_p_vs_vp ¶
    Source

    emit_vf2h_p_vs_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vf2id_p ¶
    Source

    emit_vf2id_p :: emit_vf2id_p_vp_vp_i5

    emit_vf2id_p_vp_vp_i5 ¶
    Source

    emit_vf2id_p_vp_vp_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2id_q ¶
    Source

    emit_vf2id_q :: emit_vf2id_q_vq_vq_i5

    emit_vf2id_q_vq_vq_i5 ¶
    Source

    emit_vf2id_q_vq_vq_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2id_s ¶
    Source

    emit_vf2id_s :: emit_vf2id_s_vs_vs_i5

    emit_vf2id_s_vs_vs_i5 ¶
    Source

    emit_vf2id_s_vs_vs_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2id_t ¶
    Source

    emit_vf2id_t :: emit_vf2id_t_vt_vt_i5

    emit_vf2id_t_vt_vt_i5 ¶
    Source

    emit_vf2id_t_vt_vt_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2in_p ¶
    Source

    emit_vf2in_p :: emit_vf2in_p_vp_vp_i5

    emit_vf2in_p_vp_vp_i5 ¶
    Source

    emit_vf2in_p_vp_vp_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2in_q ¶
    Source

    emit_vf2in_q :: emit_vf2in_q_vq_vq_i5

    emit_vf2in_q_vq_vq_i5 ¶
    Source

    emit_vf2in_q_vq_vq_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2in_s ¶
    Source

    emit_vf2in_s :: emit_vf2in_s_vs_vs_i5

    emit_vf2in_s_vs_vs_i5 ¶
    Source

    emit_vf2in_s_vs_vs_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2in_t ¶
    Source

    emit_vf2in_t :: emit_vf2in_t_vt_vt_i5

    emit_vf2in_t_vt_vt_i5 ¶
    Source

    emit_vf2in_t_vt_vt_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2iu_p ¶
    Source

    emit_vf2iu_p :: emit_vf2iu_p_vp_vp_i5

    emit_vf2iu_p_vp_vp_i5 ¶
    Source

    emit_vf2iu_p_vp_vp_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2iu_q ¶
    Source

    emit_vf2iu_q :: emit_vf2iu_q_vq_vq_i5

    emit_vf2iu_q_vq_vq_i5 ¶
    Source

    emit_vf2iu_q_vq_vq_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2iu_s ¶
    Source

    emit_vf2iu_s :: emit_vf2iu_s_vs_vs_i5

    emit_vf2iu_s_vs_vs_i5 ¶
    Source

    emit_vf2iu_s_vs_vs_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2iu_t ¶
    Source

    emit_vf2iu_t :: emit_vf2iu_t_vt_vt_i5

    emit_vf2iu_t_vt_vt_i5 ¶
    Source

    emit_vf2iu_t_vt_vt_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2iz_p ¶
    Source

    emit_vf2iz_p :: emit_vf2iz_p_vp_vp_i5

    emit_vf2iz_p_vp_vp_i5 ¶
    Source

    emit_vf2iz_p_vp_vp_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2iz_q ¶
    Source

    emit_vf2iz_q :: emit_vf2iz_q_vq_vq_i5

    emit_vf2iz_q_vq_vq_i5 ¶
    Source

    emit_vf2iz_q_vq_vq_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2iz_s ¶
    Source

    emit_vf2iz_s :: emit_vf2iz_s_vs_vs_i5

    emit_vf2iz_s_vs_vs_i5 ¶
    Source

    emit_vf2iz_s_vs_vs_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vf2iz_t ¶
    Source

    emit_vf2iz_t :: emit_vf2iz_t_vt_vt_i5

    emit_vf2iz_t_vt_vt_i5 ¶
    Source

    emit_vf2iz_t_vt_vt_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vfad_p ¶
    Source

    emit_vfad_p :: emit_vfad_p_vs_vp

    emit_vfad_p_vs_vp ¶
    Source

    emit_vfad_p_vs_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vfad_q ¶
    Source

    emit_vfad_q :: emit_vfad_q_vs_vq

    emit_vfad_q_vs_vq ¶
    Source

    emit_vfad_q_vs_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vfad_t ¶
    Source

    emit_vfad_t :: emit_vfad_t_vs_vt

    emit_vfad_t_vs_vt ¶
    Source

    emit_vfad_t_vs_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vfim_s ¶
    Source

    emit_vfim_s :: emit_vfim_s_vs_i16

    emit_vfim_s_vs_i16 ¶
    Source

    emit_vfim_s_vs_i16 :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

    emit_vflush ¶
    Source

    emit_vflush :: emit_vflush_none

    emit_vflush_none ¶
    Source

    emit_vflush_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_vh2f_s ¶
    Source

    emit_vh2f_s :: emit_vh2f_s_vp_vs

    emit_vh2f_s_vp_vs ¶
    Source

    emit_vh2f_s_vp_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vhdp_p ¶
    Source

    emit_vhdp_p :: emit_vhdp_p_vs_vp_vp

    emit_vhdp_p_vs_vp_vp ¶
    Source

    emit_vhdp_p_vs_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vhdp_q ¶
    Source

    emit_vhdp_q :: emit_vhdp_q_vs_vq_vq

    emit_vhdp_q_vs_vq_vq ¶
    Source

    emit_vhdp_q_vs_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vhdp_t ¶
    Source

    emit_vhdp_t :: emit_vhdp_t_vs_vt_vt

    emit_vhdp_t_vs_vt_vt ¶
    Source

    emit_vhdp_t_vs_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vhtfm2_p ¶
    Source

    emit_vhtfm2_p :: emit_vhtfm2_p_vp_vmp_vp

    emit_vhtfm2_p_vp_vmp_vp ¶
    Source

    emit_vhtfm2_p_vp_vmp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vhtfm3_t ¶
    Source

    emit_vhtfm3_t :: emit_vhtfm3_t_vt_vmt_vt

    emit_vhtfm3_t_vt_vmt_vt ¶
    Source

    emit_vhtfm3_t_vt_vmt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vhtfm4_q ¶
    Source

    emit_vhtfm4_q :: emit_vhtfm4_q_vq_vmq_vq

    emit_vhtfm4_q_vq_vmq_vq ¶
    Source

    emit_vhtfm4_q_vq_vmq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vi2f_p ¶
    Source

    emit_vi2f_p :: emit_vi2f_p_vp_vp_i5

    emit_vi2f_p_vp_vp_i5 ¶
    Source

    emit_vi2f_p_vp_vp_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vi2f_q ¶
    Source

    emit_vi2f_q :: emit_vi2f_q_vq_vq_i5

    emit_vi2f_q_vq_vq_i5 ¶
    Source

    emit_vi2f_q_vq_vq_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vi2f_s ¶
    Source

    emit_vi2f_s :: emit_vi2f_s_vs_vs_i5

    emit_vi2f_s_vs_vs_i5 ¶
    Source

    emit_vi2f_s_vs_vs_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_vi2f_t ¶
    Source

    emit_vi2f_t :: emit_vi2f_t_vt_vt_i5

    emit_vi2f_t_vt_vt_i5 ¶
    Source

    emit_vi2f_t_vt_vt_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_viim_s ¶
    Source

    emit_viim_s :: emit_viim_s_vs_i16

    emit_viim_s_vs_i16 ¶
    Source

    emit_viim_s_vs_i16 :: proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) {…}

    emit_vlog2_s ¶
    Source

    emit_vlog2_s :: emit_vlog2_s_vs_vs

    emit_vlog2_s_vs_vs ¶
    Source

    emit_vlog2_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vmax_p ¶
    Source

    emit_vmax_p :: emit_vmax_p_vp_vp_vp

    emit_vmax_p_vp_vp_vp ¶
    Source

    emit_vmax_p_vp_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmax_q ¶
    Source

    emit_vmax_q :: emit_vmax_q_vq_vq_vq

    emit_vmax_q_vq_vq_vq ¶
    Source

    emit_vmax_q_vq_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmax_s ¶
    Source

    emit_vmax_s :: emit_vmax_s_vs_vs_vs

    emit_vmax_s_vs_vs_vs ¶
    Source

    emit_vmax_s_vs_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmax_t ¶
    Source

    emit_vmax_t :: emit_vmax_t_vt_vt_vt

    emit_vmax_t_vt_vt_vt ¶
    Source

    emit_vmax_t_vt_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmidt_p ¶
    Source

    emit_vmidt_p :: emit_vmidt_p_vmp

    emit_vmidt_p_vmp ¶
    Source

    emit_vmidt_p_vmp :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

    emit_vmidt_q ¶
    Source

    emit_vmidt_q :: emit_vmidt_q_vmq

    emit_vmidt_q_vmq ¶
    Source

    emit_vmidt_q_vmq :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

    emit_vmidt_t ¶
    Source

    emit_vmidt_t :: emit_vmidt_t_vmt

    emit_vmidt_t_vmt ¶
    Source

    emit_vmidt_t_vmt :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

    emit_vmin_p ¶
    Source

    emit_vmin_p :: emit_vmin_p_vp_vp_vp

    emit_vmin_p_vp_vp_vp ¶
    Source

    emit_vmin_p_vp_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmin_q ¶
    Source

    emit_vmin_q :: emit_vmin_q_vq_vq_vq

    emit_vmin_q_vq_vq_vq ¶
    Source

    emit_vmin_q_vq_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmin_s ¶
    Source

    emit_vmin_s :: emit_vmin_s_vs_vs_vs

    emit_vmin_s_vs_vs_vs ¶
    Source

    emit_vmin_s_vs_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmin_t ¶
    Source

    emit_vmin_t :: emit_vmin_t_vt_vt_vt

    emit_vmin_t_vt_vt_vt ¶
    Source

    emit_vmin_t_vt_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmmov_p ¶
    Source

    emit_vmmov_p :: emit_vmmov_p_vmp_vmp

    emit_vmmov_p_vmp_vmp ¶
    Source

    emit_vmmov_p_vmp_vmp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vmmov_q ¶
    Source

    emit_vmmov_q :: emit_vmmov_q_vmq_vmq

    emit_vmmov_q_vmq_vmq ¶
    Source

    emit_vmmov_q_vmq_vmq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vmmov_t ¶
    Source

    emit_vmmov_t :: emit_vmmov_t_vmt_vmt

    emit_vmmov_t_vmt_vmt ¶
    Source

    emit_vmmov_t_vmt_vmt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vmmul_p ¶
    Source

    emit_vmmul_p :: emit_vmmul_p_vmp_vmp_vmp

    emit_vmmul_p_vmp_vmp_vmp ¶
    Source

    emit_vmmul_p_vmp_vmp_vmp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmmul_q ¶
    Source

    emit_vmmul_q :: emit_vmmul_q_vmq_vmq_vmq

    emit_vmmul_q_vmq_vmq_vmq ¶
    Source

    emit_vmmul_q_vmq_vmq_vmq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmmul_t ¶
    Source

    emit_vmmul_t :: emit_vmmul_t_vmt_vmt_vmt

    emit_vmmul_t_vmt_vmt_vmt ¶
    Source

    emit_vmmul_t_vmt_vmt_vmt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmone_p ¶
    Source

    emit_vmone_p :: emit_vmone_p_vmp

    emit_vmone_p_vmp ¶
    Source

    emit_vmone_p_vmp :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

    emit_vmone_q ¶
    Source

    emit_vmone_q :: emit_vmone_q_vmq

    emit_vmone_q_vmq ¶
    Source

    emit_vmone_q_vmq :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

    emit_vmone_t ¶
    Source

    emit_vmone_t :: emit_vmone_t_vmt

    emit_vmone_t_vmt ¶
    Source

    emit_vmone_t_vmt :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

    emit_vmov_p ¶
    Source

    emit_vmov_p :: emit_vmov_p_vp_vp

    emit_vmov_p_vp_vp ¶
    Source

    emit_vmov_p_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vmov_q ¶
    Source

    emit_vmov_q :: emit_vmov_q_vq_vq

    emit_vmov_q_vq_vq ¶
    Source

    emit_vmov_q_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vmov_s ¶
    Source

    emit_vmov_s :: emit_vmov_s_vs_vs

    emit_vmov_s_vs_vs ¶
    Source

    emit_vmov_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vmov_t ¶
    Source

    emit_vmov_t :: emit_vmov_t_vt_vt

    emit_vmov_t_vt_vt ¶
    Source

    emit_vmov_t_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vmscl_p ¶
    Source

    emit_vmscl_p :: emit_vmscl_p_vmp_vmp_vs

    emit_vmscl_p_vmp_vmp_vs ¶
    Source

    emit_vmscl_p_vmp_vmp_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmscl_q ¶
    Source

    emit_vmscl_q :: emit_vmscl_q_vmq_vmq_vs

    emit_vmscl_q_vmq_vmq_vs ¶
    Source

    emit_vmscl_q_vmq_vmq_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmscl_t ¶
    Source

    emit_vmscl_t :: emit_vmscl_t_vmt_vmt_vs

    emit_vmscl_t_vmt_vmt_vs ¶
    Source

    emit_vmscl_t_vmt_vmt_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmul_p ¶
    Source

    emit_vmul_p :: emit_vmul_p_vp_vp_vp

    emit_vmul_p_vp_vp_vp ¶
    Source

    emit_vmul_p_vp_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmul_q ¶
    Source

    emit_vmul_q :: emit_vmul_q_vq_vq_vq

    emit_vmul_q_vq_vq_vq ¶
    Source

    emit_vmul_q_vq_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmul_s ¶
    Source

    emit_vmul_s :: emit_vmul_s_vs_vs_vs

    emit_vmul_s_vs_vs_vs ¶
    Source

    emit_vmul_s_vs_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmul_t ¶
    Source

    emit_vmul_t :: emit_vmul_t_vt_vt_vt

    emit_vmul_t_vt_vt_vt ¶
    Source

    emit_vmul_t_vt_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vmzero_p ¶
    Source

    emit_vmzero_p :: emit_vmzero_p_vmp

    emit_vmzero_p_vmp ¶
    Source

    emit_vmzero_p_vmp :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

    emit_vmzero_q ¶
    Source

    emit_vmzero_q :: emit_vmzero_q_vmq

    emit_vmzero_q_vmq ¶
    Source

    emit_vmzero_q_vmq :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

    emit_vmzero_t ¶
    Source

    emit_vmzero_t :: emit_vmzero_t_vmt

    emit_vmzero_t_vmt ¶
    Source

    emit_vmzero_t_vmt :: proc(instructions: ^[dynamic]Instruction, dst: Register) {…}

    emit_vneg_p ¶
    Source

    emit_vneg_p :: emit_vneg_p_vp_vp

    emit_vneg_p_vp_vp ¶
    Source

    emit_vneg_p_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vneg_q ¶
    Source

    emit_vneg_q :: emit_vneg_q_vq_vq

    emit_vneg_q_vq_vq ¶
    Source

    emit_vneg_q_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vneg_s ¶
    Source

    emit_vneg_s :: emit_vneg_s_vs_vs

    emit_vneg_s_vs_vs ¶
    Source

    emit_vneg_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vneg_t ¶
    Source

    emit_vneg_t :: emit_vneg_t_vt_vt

    emit_vneg_t_vt_vt ¶
    Source

    emit_vneg_t_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vnop ¶
    Source

    emit_vnop :: emit_vnop_none

    emit_vnop_none ¶
    Source

    emit_vnop_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_vnrcp_s ¶
    Source

    emit_vnrcp_s :: emit_vnrcp_s_vs_vs

    emit_vnrcp_s_vs_vs ¶
    Source

    emit_vnrcp_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vnsin_s ¶
    Source

    emit_vnsin_s :: emit_vnsin_s_vs_vs

    emit_vnsin_s_vs_vs ¶
    Source

    emit_vnsin_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vpfxd ¶
    Source

    emit_vpfxd :: emit_vpfxd_i20

    emit_vpfxd_i20 ¶
    Source

    emit_vpfxd_i20 :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

    emit_vpfxs ¶
    Source

    emit_vpfxs :: emit_vpfxs_i20

    emit_vpfxs_i20 ¶
    Source

    emit_vpfxs_i20 :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

    emit_vpfxt ¶
    Source

    emit_vpfxt :: emit_vpfxt_i20

    emit_vpfxt_i20 ¶
    Source

    emit_vpfxt_i20 :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

    emit_vqmul_q ¶
    Source

    emit_vqmul_q :: emit_vqmul_q_vq_vq_vq

    emit_vqmul_q_vq_vq_vq ¶
    Source

    emit_vqmul_q_vq_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vrcp_p ¶
    Source

    emit_vrcp_p :: emit_vrcp_p_vp_vp

    emit_vrcp_p_vp_vp ¶
    Source

    emit_vrcp_p_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vrcp_q ¶
    Source

    emit_vrcp_q :: emit_vrcp_q_vq_vq

    emit_vrcp_q_vq_vq ¶
    Source

    emit_vrcp_q_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vrcp_s ¶
    Source

    emit_vrcp_s :: emit_vrcp_s_vs_vs

    emit_vrcp_s_vs_vs ¶
    Source

    emit_vrcp_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vrcp_t ¶
    Source

    emit_vrcp_t :: emit_vrcp_t_vt_vt

    emit_vrcp_t_vt_vt ¶
    Source

    emit_vrcp_t_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vrexp2_s ¶
    Source

    emit_vrexp2_s :: emit_vrexp2_s_vs_vs

    emit_vrexp2_s_vs_vs ¶
    Source

    emit_vrexp2_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vrsq_p ¶
    Source

    emit_vrsq_p :: emit_vrsq_p_vp_vp

    emit_vrsq_p_vp_vp ¶
    Source

    emit_vrsq_p_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vrsq_q ¶
    Source

    emit_vrsq_q :: emit_vrsq_q_vq_vq

    emit_vrsq_q_vq_vq ¶
    Source

    emit_vrsq_q_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vrsq_s ¶
    Source

    emit_vrsq_s :: emit_vrsq_s_vs_vs

    emit_vrsq_s_vs_vs ¶
    Source

    emit_vrsq_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vrsq_t ¶
    Source

    emit_vrsq_t :: emit_vrsq_t_vt_vt

    emit_vrsq_t_vt_vt ¶
    Source

    emit_vrsq_t_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vscl_p ¶
    Source

    emit_vscl_p :: emit_vscl_p_vp_vp_vs

    emit_vscl_p_vp_vp_vs ¶
    Source

    emit_vscl_p_vp_vp_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vscl_q ¶
    Source

    emit_vscl_q :: emit_vscl_q_vq_vq_vs

    emit_vscl_q_vq_vq_vs ¶
    Source

    emit_vscl_q_vq_vq_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vscl_t ¶
    Source

    emit_vscl_t :: emit_vscl_t_vt_vt_vs

    emit_vscl_t_vt_vt_vs ¶
    Source

    emit_vscl_t_vt_vt_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vsgn_s ¶
    Source

    emit_vsgn_s :: emit_vsgn_s_vs_vs

    emit_vsgn_s_vs_vs ¶
    Source

    emit_vsgn_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vshf_b ¶
    Source

    emit_vshf_b :: emit_vshf_b_w_w_w

    emit_vshf_b_w_w_w ¶
    Source

    emit_vshf_b_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vshf_d ¶
    Source

    emit_vshf_d :: emit_vshf_d_w_w_w

    emit_vshf_d_w_w_w ¶
    Source

    emit_vshf_d_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vshf_h ¶
    Source

    emit_vshf_h :: emit_vshf_h_w_w_w

    emit_vshf_h_w_w_w ¶
    Source

    emit_vshf_h_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vshf_w ¶
    Source

    emit_vshf_w :: emit_vshf_w_w_w_w

    emit_vshf_w_w_w_w ¶
    Source

    emit_vshf_w_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vsin_s ¶
    Source

    emit_vsin_s :: emit_vsin_s_vs_vs

    emit_vsin_s_vs_vs ¶
    Source

    emit_vsin_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vsqrt_s ¶
    Source

    emit_vsqrt_s :: emit_vsqrt_s_vs_vs

    emit_vsqrt_s_vs_vs ¶
    Source

    emit_vsqrt_s_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) {…}

    emit_vsub_p ¶
    Source

    emit_vsub_p :: emit_vsub_p_vp_vp_vp

    emit_vsub_p_vp_vp_vp ¶
    Source

    emit_vsub_p_vp_vp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vsub_q ¶
    Source

    emit_vsub_q :: emit_vsub_q_vq_vq_vq

    emit_vsub_q_vq_vq_vq ¶
    Source

    emit_vsub_q_vq_vq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vsub_s ¶
    Source

    emit_vsub_s :: emit_vsub_s_vs_vs_vs

    emit_vsub_s_vs_vs_vs ¶
    Source

    emit_vsub_s_vs_vs_vs :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vsub_t ¶
    Source

    emit_vsub_t :: emit_vsub_t_vt_vt_vt

    emit_vsub_t_vt_vt_vt ¶
    Source

    emit_vsub_t_vt_vt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vsync ¶
    Source

    emit_vsync :: emit_vsync_none

    emit_vsync_none ¶
    Source

    emit_vsync_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_vtfm2_p ¶
    Source

    emit_vtfm2_p :: emit_vtfm2_p_vp_vmp_vp

    emit_vtfm2_p_vp_vmp_vp ¶
    Source

    emit_vtfm2_p_vp_vmp_vp :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vtfm3_t ¶
    Source

    emit_vtfm3_t :: emit_vtfm3_t_vt_vmt_vt

    emit_vtfm3_t_vt_vmt_vt ¶
    Source

    emit_vtfm3_t_vt_vmt_vt :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_vtfm4_q ¶
    Source

    emit_vtfm4_q :: emit_vtfm4_q_vq_vmq_vq

    emit_vtfm4_q_vq_vmq_vq ¶
    Source

    emit_vtfm4_q_vq_vmq_vq :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_wait ¶
    Source

    emit_wait :: emit_wait_none

    emit_wait_none ¶
    Source

    emit_wait_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_wrdsp ¶
    Source

    emit_wrdsp :: emit_wrdsp_r_i5

    emit_wrdsp_r_i5 ¶
    Source

    emit_wrdsp_r_i5 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, imm: i64) {…}

    emit_wrpgpr ¶
    Source

    emit_wrpgpr :: emit_wrpgpr_r_r

    emit_wrpgpr_r_r ¶
    Source

    emit_wrpgpr_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_wsbh ¶
    Source

    emit_wsbh :: emit_wsbh_r_r

    emit_wsbh_r_r ¶
    Source

    emit_wsbh_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) {…}

    emit_xor ¶
    Source

    emit_xor :: emit_xor_r_r_r

    emit_xor_r_r_r ¶
    Source

    emit_xor_r_r_r :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) {…}

    emit_xor_v ¶
    Source

    emit_xor_v :: emit_xor_v_w_w_w

    emit_xor_v_w_w_w ¶
    Source

    emit_xor_v_w_w_w :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) {…}

    emit_xori ¶
    Source

    emit_xori :: emit_xori_r_r_u16

    emit_xori_b ¶
    Source

    emit_xori_b :: emit_xori_b_w_w_i5

    emit_xori_b_w_w_i5 ¶
    Source

    emit_xori_b_w_w_i5 :: proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) {…}

    emit_xori_r_r_u16 ¶
    Source

    emit_xori_r_r_u16 :: proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) {…}

    encode ¶
    Source

    encode :: proc(
	instructions: []Instruction, 
	label_defs:   []rexcode_isa.Label_Definition, 
	code:         []u8, 
	relocs:       ^[dynamic]Relocation, 
	errors:       ^[dynamic]rexcode_isa.Error, 
	endianness:   Endianness = .BIG, 
	resolve:      bool = true, 
	base_address: u64 = 0, 
) -> (byte_count: u32, ok: bool) {…}

    encode_max_code_size ¶
    Source

    encode_max_code_size :: proc "contextless" (instructions: []Instruction) -> int {…}
     

    Upper bound on bytes emitted for n instructions.

    encode_max_relocation_count ¶
    Source

    encode_max_relocation_count :: proc "contextless" (instructions: []Instruction) -> int {…}
     

    Upper bound on pending relocations for n instructions (each instruction has at most one label-referencing operand).

    encode_reserve ¶
    Source

    encode_reserve :: proc(code: ^[dynamic]u8, relocs: ^[dynamic]Relocation, instructions: []Instruction) {…}
     

    Pre-size the caller's encode outputs (code grown by length so code[:] is a valid emit target; relocs reserved by capacity) so the encode hot path never reallocates. Allocates no new buffers; pass nil to skip either array.

    fpr_from_num ¶
    Source

    fpr_from_num :: proc "contextless" (num: u8) -> Register {…}

    fprint ¶
    Source

    fprint :: proc(
	fd:           ^os.File, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    fprintln ¶
    Source

    fprintln :: proc(
	fd:           ^os.File, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    gpr_from_num ¶
    Source

    gpr_from_num :: proc "contextless" (num: u8) -> Register {…}

    inst_abs_d ¶
    Source

    inst_abs_d :: inst_abs_d_f_f

    inst_abs_d_f_f ¶
    Source

    inst_abs_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_abs_ps ¶
    Source

    inst_abs_ps :: inst_abs_ps_f_f

    inst_abs_ps_f_f ¶
    Source

    inst_abs_ps_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_abs_s ¶
    Source

    inst_abs_s :: inst_abs_s_f_f

    inst_abs_s_f_f ¶
    Source

    inst_abs_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_absq_s_ph ¶
    Source

    inst_absq_s_ph :: inst_absq_s_ph_r_r

    inst_absq_s_ph_r_r ¶
    Source

    inst_absq_s_ph_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_absq_s_w ¶
    Source

    inst_absq_s_w :: inst_absq_s_w_r_r

    inst_absq_s_w_r_r ¶
    Source

    inst_absq_s_w_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_add ¶
    Source

    inst_add :: inst_add_r_r_r

    inst_add_d ¶
    Source

    inst_add_d :: inst_add_d_f_f_f

    inst_add_d_f_f_f ¶
    Source

    inst_add_d_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_add_ps ¶
    Source

    inst_add_ps :: inst_add_ps_f_f_f

    inst_add_ps_f_f_f ¶
    Source

    inst_add_ps_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_add_r_r_r ¶
    Source

    inst_add_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_add_s ¶
    Source

    inst_add_s :: inst_add_s_f_f_f

    inst_add_s_f_f_f ¶
    Source

    inst_add_s_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_addi ¶
    Source

    inst_addi :: inst_addi_r_r_i16

    inst_addi_r_r_i16 ¶
    Source

    inst_addi_r_r_i16 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_addiu ¶
    Source

    inst_addiu :: inst_addiu_r_r_i16

    inst_addiu_r_r_i16 ¶
    Source

    inst_addiu_r_r_i16 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_addq_ph ¶
    Source

    inst_addq_ph :: inst_addq_ph_r_r_r

    inst_addq_ph_r_r_r ¶
    Source

    inst_addq_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_addq_s_ph ¶
    Source

    inst_addq_s_ph :: inst_addq_s_ph_r_r_r

    inst_addq_s_ph_r_r_r ¶
    Source

    inst_addq_s_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_addq_s_w ¶
    Source

    inst_addq_s_w :: inst_addq_s_w_r_r_r

    inst_addq_s_w_r_r_r ¶
    Source

    inst_addq_s_w_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_adds_s_b ¶
    Source

    inst_adds_s_b :: inst_adds_s_b_w_w_w

    inst_adds_s_b_w_w_w ¶
    Source

    inst_adds_s_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_adds_s_d ¶
    Source

    inst_adds_s_d :: inst_adds_s_d_w_w_w

    inst_adds_s_d_w_w_w ¶
    Source

    inst_adds_s_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_adds_s_h ¶
    Source

    inst_adds_s_h :: inst_adds_s_h_w_w_w

    inst_adds_s_h_w_w_w ¶
    Source

    inst_adds_s_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_adds_s_w ¶
    Source

    inst_adds_s_w :: inst_adds_s_w_w_w_w

    inst_adds_s_w_w_w_w ¶
    Source

    inst_adds_s_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_adds_u_b ¶
    Source

    inst_adds_u_b :: inst_adds_u_b_w_w_w

    inst_adds_u_b_w_w_w ¶
    Source

    inst_adds_u_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_adds_u_d ¶
    Source

    inst_adds_u_d :: inst_adds_u_d_w_w_w

    inst_adds_u_d_w_w_w ¶
    Source

    inst_adds_u_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_adds_u_h ¶
    Source

    inst_adds_u_h :: inst_adds_u_h_w_w_w

    inst_adds_u_h_w_w_w ¶
    Source

    inst_adds_u_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_adds_u_w ¶
    Source

    inst_adds_u_w :: inst_adds_u_w_w_w_w

    inst_adds_u_w_w_w_w ¶
    Source

    inst_adds_u_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_addsc ¶
    Source

    inst_addsc :: inst_addsc_r_r_r

    inst_addsc_r_r_r ¶
    Source

    inst_addsc_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_addu ¶
    Source

    inst_addu :: inst_addu_r_r_r

    inst_addu_ph ¶
    Source

    inst_addu_ph :: inst_addu_ph_r_r_r

    inst_addu_ph_r_r_r ¶
    Source

    inst_addu_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_addu_qb ¶
    Source

    inst_addu_qb :: inst_addu_qb_r_r_r

    inst_addu_qb_r_r_r ¶
    Source

    inst_addu_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_addu_r_r_r ¶
    Source

    inst_addu_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_addu_s_ph ¶
    Source

    inst_addu_s_ph :: inst_addu_s_ph_r_r_r

    inst_addu_s_ph_r_r_r ¶
    Source

    inst_addu_s_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_addu_s_qb ¶
    Source

    inst_addu_s_qb :: inst_addu_s_qb_r_r_r

    inst_addu_s_qb_r_r_r ¶
    Source

    inst_addu_s_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_addv_b ¶
    Source

    inst_addv_b :: inst_addv_b_w_w_w

    inst_addv_b_w_w_w ¶
    Source

    inst_addv_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_addv_d ¶
    Source

    inst_addv_d :: inst_addv_d_w_w_w

    inst_addv_d_w_w_w ¶
    Source

    inst_addv_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_addv_h ¶
    Source

    inst_addv_h :: inst_addv_h_w_w_w

    inst_addv_h_w_w_w ¶
    Source

    inst_addv_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_addv_w ¶
    Source

    inst_addv_w :: inst_addv_w_w_w_w

    inst_addv_w_w_w_w ¶
    Source

    inst_addv_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_addwc ¶
    Source

    inst_addwc :: inst_addwc_r_r_r

    inst_addwc_r_r_r ¶
    Source

    inst_addwc_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_align ¶
    Source

    inst_align :: inst_align_r_r_r_i5

    inst_align_r_r_r_i5 ¶
    Source

    inst_align_r_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, src2: GPR, imm: i64) -> Instruction {…}

    inst_aluipc ¶
    Source

    inst_aluipc :: inst_aluipc_r_i16

    inst_aluipc_r_i16 ¶
    Source

    inst_aluipc_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_and ¶
    Source

    inst_and :: inst_and_r_r_r

    inst_and_r_r_r ¶
    Source

    inst_and_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_and_v ¶
    Source

    inst_and_v :: inst_and_v_w_w_w

    inst_and_v_w_w_w ¶
    Source

    inst_and_v_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_andi ¶
    Source

    inst_andi :: inst_andi_r_r_u16

    inst_andi_b ¶
    Source

    inst_andi_b :: inst_andi_b_w_w_i5

    inst_andi_b_w_w_i5 ¶
    Source

    inst_andi_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_andi_r_r_u16 ¶
    Source

    inst_andi_r_r_u16 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_aui ¶
    Source

    inst_aui :: inst_aui_r_r_u16

    inst_aui_r_r_u16 ¶
    Source

    inst_aui_r_r_u16 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_auipc ¶
    Source

    inst_auipc :: inst_auipc_r_i16

    inst_auipc_r_i16 ¶
    Source

    inst_auipc_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_avsz3 ¶
    Source

    inst_avsz3 :: inst_avsz3_none

    inst_avsz3_none ¶
    Source

    inst_avsz3_none :: proc "contextless" () -> Instruction {…}

    inst_avsz4 ¶
    Source

    inst_avsz4 :: inst_avsz4_none

    inst_avsz4_none ¶
    Source

    inst_avsz4_none :: proc "contextless" () -> Instruction {…}

    inst_balc ¶
    Source

    inst_balc :: inst_balc_rel26

    inst_balc_rel26 ¶
    Source

    inst_balc_rel26 :: proc "contextless" (target: u32) -> Instruction {…}

    inst_bc ¶
    Source

    inst_bc :: inst_bc_rel26

    inst_bc1eqz ¶
    Source

    inst_bc1eqz :: inst_bc1eqz_f_rel

    inst_bc1eqz_f_rel ¶
    Source

    inst_bc1eqz_f_rel :: proc "contextless" (dst: FPR, target: u32) -> Instruction {…}

    inst_bc1f ¶
    Source

    inst_bc1f :: inst_bc1f_cc_rel

    inst_bc1f_cc_rel ¶
    Source

    inst_bc1f_cc_rel :: proc "contextless" (imm: i64, target: u32) -> Instruction {…}

    inst_bc1fl ¶
    Source

    inst_bc1fl :: inst_bc1fl_cc_rel

    inst_bc1fl_cc_rel ¶
    Source

    inst_bc1fl_cc_rel :: proc "contextless" (imm: i64, target: u32) -> Instruction {…}

    inst_bc1nez ¶
    Source

    inst_bc1nez :: inst_bc1nez_f_rel

    inst_bc1nez_f_rel ¶
    Source

    inst_bc1nez_f_rel :: proc "contextless" (dst: FPR, target: u32) -> Instruction {…}

    inst_bc1t ¶
    Source

    inst_bc1t :: inst_bc1t_cc_rel

    inst_bc1t_cc_rel ¶
    Source

    inst_bc1t_cc_rel :: proc "contextless" (imm: i64, target: u32) -> Instruction {…}

    inst_bc1tl ¶
    Source

    inst_bc1tl :: inst_bc1tl_cc_rel

    inst_bc1tl_cc_rel ¶
    Source

    inst_bc1tl_cc_rel :: proc "contextless" (imm: i64, target: u32) -> Instruction {…}

    inst_bc2eqz ¶
    Source

    inst_bc2eqz :: inst_bc2eqz_c2_rel

    inst_bc2eqz_c2_rel ¶
    Source

    inst_bc2eqz_c2_rel :: proc "contextless" (dst: GTE_DataReg, target: u32) -> Instruction {…}

    inst_bc2nez ¶
    Source

    inst_bc2nez :: inst_bc2nez_c2_rel

    inst_bc2nez_c2_rel ¶
    Source

    inst_bc2nez_c2_rel :: proc "contextless" (dst: GTE_DataReg, target: u32) -> Instruction {…}

    inst_bc_rel26 ¶
    Source

    inst_bc_rel26 :: proc "contextless" (target: u32) -> Instruction {…}

    inst_beq ¶
    Source

    inst_beq :: inst_beq_r_r_rel

    inst_beq_r_r_rel ¶
    Source

    inst_beq_r_r_rel :: proc "contextless" (dst: GPR, src: GPR, target: u32) -> Instruction {…}

    inst_beqc ¶
    Source

    inst_beqc :: inst_beqc_r_r_rel

    inst_beqc_r_r_rel ¶
    Source

    inst_beqc_r_r_rel :: proc "contextless" (dst: GPR, src: GPR, target: u32) -> Instruction {…}

    inst_beql ¶
    Source

    inst_beql :: inst_beql_r_r_rel

    inst_beql_r_r_rel ¶
    Source

    inst_beql_r_r_rel :: proc "contextless" (dst: GPR, src: GPR, target: u32) -> Instruction {…}

    inst_beqzc ¶
    Source

    inst_beqzc :: inst_beqzc_r_rel21

    inst_beqzc_r_rel21 ¶
    Source

    inst_beqzc_r_rel21 :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bgec ¶
    Source

    inst_bgec :: inst_bgec_r_r_rel

    inst_bgec_r_r_rel ¶
    Source

    inst_bgec_r_r_rel :: proc "contextless" (dst: GPR, src: GPR, target: u32) -> Instruction {…}

    inst_bgeuc ¶
    Source

    inst_bgeuc :: inst_bgeuc_r_r_rel

    inst_bgeuc_r_r_rel ¶
    Source

    inst_bgeuc_r_r_rel :: proc "contextless" (dst: GPR, src: GPR, target: u32) -> Instruction {…}

    inst_bgez ¶
    Source

    inst_bgez :: inst_bgez_r_rel

    inst_bgez_r_rel ¶
    Source

    inst_bgez_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bgezal ¶
    Source

    inst_bgezal :: inst_bgezal_r_rel

    inst_bgezal_r_rel ¶
    Source

    inst_bgezal_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bgezall ¶
    Source

    inst_bgezall :: inst_bgezall_r_rel

    inst_bgezall_r_rel ¶
    Source

    inst_bgezall_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bgezc ¶
    Source

    inst_bgezc :: inst_bgezc_r_rel

    inst_bgezc_r_rel ¶
    Source

    inst_bgezc_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bgezl ¶
    Source

    inst_bgezl :: inst_bgezl_r_rel

    inst_bgezl_r_rel ¶
    Source

    inst_bgezl_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bgtz ¶
    Source

    inst_bgtz :: inst_bgtz_r_rel

    inst_bgtz_r_rel ¶
    Source

    inst_bgtz_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bgtzc ¶
    Source

    inst_bgtzc :: inst_bgtzc_r_rel

    inst_bgtzc_r_rel ¶
    Source

    inst_bgtzc_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bgtzl ¶
    Source

    inst_bgtzl :: inst_bgtzl_r_rel

    inst_bgtzl_r_rel ¶
    Source

    inst_bgtzl_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bitrev ¶
    Source

    inst_bitrev :: inst_bitrev_r_r

    inst_bitrev_r_r ¶
    Source

    inst_bitrev_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_bitswap ¶
    Source

    inst_bitswap :: inst_bitswap_r_r

    inst_bitswap_r_r ¶
    Source

    inst_bitswap_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_blez ¶
    Source

    inst_blez :: inst_blez_r_rel

    inst_blez_r_rel ¶
    Source

    inst_blez_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_blezc ¶
    Source

    inst_blezc :: inst_blezc_r_rel

    inst_blezc_r_rel ¶
    Source

    inst_blezc_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_blezl ¶
    Source

    inst_blezl :: inst_blezl_r_rel

    inst_blezl_r_rel ¶
    Source

    inst_blezl_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bltc ¶
    Source

    inst_bltc :: inst_bltc_r_r_rel

    inst_bltc_r_r_rel ¶
    Source

    inst_bltc_r_r_rel :: proc "contextless" (dst: GPR, src: GPR, target: u32) -> Instruction {…}

    inst_bltuc ¶
    Source

    inst_bltuc :: inst_bltuc_r_r_rel

    inst_bltuc_r_r_rel ¶
    Source

    inst_bltuc_r_r_rel :: proc "contextless" (dst: GPR, src: GPR, target: u32) -> Instruction {…}

    inst_bltz ¶
    Source

    inst_bltz :: inst_bltz_r_rel

    inst_bltz_r_rel ¶
    Source

    inst_bltz_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bltzal ¶
    Source

    inst_bltzal :: inst_bltzal_r_rel

    inst_bltzal_r_rel ¶
    Source

    inst_bltzal_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bltzall ¶
    Source

    inst_bltzall :: inst_bltzall_r_rel

    inst_bltzall_r_rel ¶
    Source

    inst_bltzall_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bltzc ¶
    Source

    inst_bltzc :: inst_bltzc_r_rel

    inst_bltzc_r_rel ¶
    Source

    inst_bltzc_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bltzl ¶
    Source

    inst_bltzl :: inst_bltzl_r_rel

    inst_bltzl_r_rel ¶
    Source

    inst_bltzl_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bmnz_v ¶
    Source

    inst_bmnz_v :: inst_bmnz_v_w_w_w

    inst_bmnz_v_w_w_w ¶
    Source

    inst_bmnz_v_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_bmnzi_b ¶
    Source

    inst_bmnzi_b :: inst_bmnzi_b_w_w_i5

    inst_bmnzi_b_w_w_i5 ¶
    Source

    inst_bmnzi_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_bmz_v ¶
    Source

    inst_bmz_v :: inst_bmz_v_w_w_w

    inst_bmz_v_w_w_w ¶
    Source

    inst_bmz_v_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_bmzi_b ¶
    Source

    inst_bmzi_b :: inst_bmzi_b_w_w_i5

    inst_bmzi_b_w_w_i5 ¶
    Source

    inst_bmzi_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_bne ¶
    Source

    inst_bne :: inst_bne_r_r_rel

    inst_bne_r_r_rel ¶
    Source

    inst_bne_r_r_rel :: proc "contextless" (dst: GPR, src: GPR, target: u32) -> Instruction {…}

    inst_bnec ¶
    Source

    inst_bnec :: inst_bnec_r_r_rel

    inst_bnec_r_r_rel ¶
    Source

    inst_bnec_r_r_rel :: proc "contextless" (dst: GPR, src: GPR, target: u32) -> Instruction {…}

    inst_bnel ¶
    Source

    inst_bnel :: inst_bnel_r_r_rel

    inst_bnel_r_r_rel ¶
    Source

    inst_bnel_r_r_rel :: proc "contextless" (dst: GPR, src: GPR, target: u32) -> Instruction {…}

    inst_bnezc ¶
    Source

    inst_bnezc :: inst_bnezc_r_rel21

    inst_bnezc_r_rel21 ¶
    Source

    inst_bnezc_r_rel21 :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_bnz_b ¶
    Source

    inst_bnz_b :: inst_bnz_b_w_rel

    inst_bnz_b_w_rel ¶
    Source

    inst_bnz_b_w_rel :: proc "contextless" (dst: Register, target: u32) -> Instruction {…}

    inst_bnz_d ¶
    Source

    inst_bnz_d :: inst_bnz_d_w_rel

    inst_bnz_d_w_rel ¶
    Source

    inst_bnz_d_w_rel :: proc "contextless" (dst: Register, target: u32) -> Instruction {…}

    inst_bnz_h ¶
    Source

    inst_bnz_h :: inst_bnz_h_w_rel

    inst_bnz_h_w_rel ¶
    Source

    inst_bnz_h_w_rel :: proc "contextless" (dst: Register, target: u32) -> Instruction {…}

    inst_bnz_v ¶
    Source

    inst_bnz_v :: inst_bnz_v_w_rel

    inst_bnz_v_w_rel ¶
    Source

    inst_bnz_v_w_rel :: proc "contextless" (dst: Register, target: u32) -> Instruction {…}

    inst_bnz_w ¶
    Source

    inst_bnz_w :: inst_bnz_w_w_rel

    inst_bnz_w_w_rel ¶
    Source

    inst_bnz_w_w_rel :: proc "contextless" (dst: Register, target: u32) -> Instruction {…}

    inst_bposge32 ¶
    Source

    inst_bposge32 :: inst_bposge32_rel

    inst_bposge32_rel ¶
    Source

    inst_bposge32_rel :: proc "contextless" (target: u32) -> Instruction {…}

    inst_branch1 ¶
    Source

    inst_branch1 :: proc "contextless" (m: Mnemonic, rs: Register, label_id: u32) -> Instruction {…}
     

    One-reg branch + label (BLTZ/BGEZ/BLEZ/BGTZ/BLTZAL/BGEZAL/...).

    inst_branch2 ¶
    Source

    inst_branch2 :: proc "contextless" (m: Mnemonic, rs, rt: Register, label_id: u32) -> Instruction {…}
     

    Two-reg branch + label (BEQ/BNE: rs, rt, target).

    inst_break ¶
    Source

    inst_break :: inst_break_i20

    inst_break_i20 ¶
    Source

    inst_break_i20 :: proc "contextless" (imm: i64) -> Instruction {…}

    inst_bsel_v ¶
    Source

    inst_bsel_v :: inst_bsel_v_w_w_w

    inst_bsel_v_w_w_w ¶
    Source

    inst_bsel_v_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_bseli_b ¶
    Source

    inst_bseli_b :: inst_bseli_b_w_w_i5

    inst_bseli_b_w_w_i5 ¶
    Source

    inst_bseli_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_bvf ¶
    Source

    inst_bvf :: inst_bvf_i5_rel

    inst_bvf_i5_rel ¶
    Source

    inst_bvf_i5_rel :: proc "contextless" (imm: i64, target: u32) -> Instruction {…}

    inst_bvfl ¶
    Source

    inst_bvfl :: inst_bvfl_i5_rel

    inst_bvfl_i5_rel ¶
    Source

    inst_bvfl_i5_rel :: proc "contextless" (imm: i64, target: u32) -> Instruction {…}

    inst_bvt ¶
    Source

    inst_bvt :: inst_bvt_i5_rel

    inst_bvt_i5_rel ¶
    Source

    inst_bvt_i5_rel :: proc "contextless" (imm: i64, target: u32) -> Instruction {…}

    inst_bvtl ¶
    Source

    inst_bvtl :: inst_bvtl_i5_rel

    inst_bvtl_i5_rel ¶
    Source

    inst_bvtl_i5_rel :: proc "contextless" (imm: i64, target: u32) -> Instruction {…}

    inst_bz_b ¶
    Source

    inst_bz_b :: inst_bz_b_w_rel

    inst_bz_b_w_rel ¶
    Source

    inst_bz_b_w_rel :: proc "contextless" (dst: Register, target: u32) -> Instruction {…}

    inst_bz_d ¶
    Source

    inst_bz_d :: inst_bz_d_w_rel

    inst_bz_d_w_rel ¶
    Source

    inst_bz_d_w_rel :: proc "contextless" (dst: Register, target: u32) -> Instruction {…}

    inst_bz_h ¶
    Source

    inst_bz_h :: inst_bz_h_w_rel

    inst_bz_h_w_rel ¶
    Source

    inst_bz_h_w_rel :: proc "contextless" (dst: Register, target: u32) -> Instruction {…}

    inst_bz_v ¶
    Source

    inst_bz_v :: inst_bz_v_w_rel

    inst_bz_v_w_rel ¶
    Source

    inst_bz_v_w_rel :: proc "contextless" (dst: Register, target: u32) -> Instruction {…}

    inst_bz_w ¶
    Source

    inst_bz_w :: inst_bz_w_w_rel

    inst_bz_w_w_rel ¶
    Source

    inst_bz_w_w_rel :: proc "contextless" (dst: Register, target: u32) -> Instruction {…}

    inst_c_eq_d ¶
    Source

    inst_c_eq_d :: inst_c_eq_d_f_f_cc

    inst_c_eq_d_f_f_cc ¶
    Source

    inst_c_eq_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_eq_ps ¶
    Source

    inst_c_eq_ps :: inst_c_eq_ps_f_f_cc

    inst_c_eq_ps_f_f_cc ¶
    Source

    inst_c_eq_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_eq_s ¶
    Source

    inst_c_eq_s :: inst_c_eq_s_f_f_cc

    inst_c_eq_s_f_f_cc ¶
    Source

    inst_c_eq_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_f_d ¶
    Source

    inst_c_f_d :: inst_c_f_d_f_f_cc

    inst_c_f_d_f_f_cc ¶
    Source

    inst_c_f_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_f_ps ¶
    Source

    inst_c_f_ps :: inst_c_f_ps_f_f_cc

    inst_c_f_ps_f_f_cc ¶
    Source

    inst_c_f_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_f_s ¶
    Source

    inst_c_f_s :: inst_c_f_s_f_f_cc

    inst_c_f_s_f_f_cc ¶
    Source

    inst_c_f_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_le_d ¶
    Source

    inst_c_le_d :: inst_c_le_d_f_f_cc

    inst_c_le_d_f_f_cc ¶
    Source

    inst_c_le_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_le_ps ¶
    Source

    inst_c_le_ps :: inst_c_le_ps_f_f_cc

    inst_c_le_ps_f_f_cc ¶
    Source

    inst_c_le_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_le_s ¶
    Source

    inst_c_le_s :: inst_c_le_s_f_f_cc

    inst_c_le_s_f_f_cc ¶
    Source

    inst_c_le_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_lt_d ¶
    Source

    inst_c_lt_d :: inst_c_lt_d_f_f_cc

    inst_c_lt_d_f_f_cc ¶
    Source

    inst_c_lt_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_lt_ps ¶
    Source

    inst_c_lt_ps :: inst_c_lt_ps_f_f_cc

    inst_c_lt_ps_f_f_cc ¶
    Source

    inst_c_lt_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_lt_s ¶
    Source

    inst_c_lt_s :: inst_c_lt_s_f_f_cc

    inst_c_lt_s_f_f_cc ¶
    Source

    inst_c_lt_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_nge_d ¶
    Source

    inst_c_nge_d :: inst_c_nge_d_f_f_cc

    inst_c_nge_d_f_f_cc ¶
    Source

    inst_c_nge_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_nge_ps ¶
    Source

    inst_c_nge_ps :: inst_c_nge_ps_f_f_cc

    inst_c_nge_ps_f_f_cc ¶
    Source

    inst_c_nge_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_nge_s ¶
    Source

    inst_c_nge_s :: inst_c_nge_s_f_f_cc

    inst_c_nge_s_f_f_cc ¶
    Source

    inst_c_nge_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ngl_d ¶
    Source

    inst_c_ngl_d :: inst_c_ngl_d_f_f_cc

    inst_c_ngl_d_f_f_cc ¶
    Source

    inst_c_ngl_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ngl_ps ¶
    Source

    inst_c_ngl_ps :: inst_c_ngl_ps_f_f_cc

    inst_c_ngl_ps_f_f_cc ¶
    Source

    inst_c_ngl_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ngl_s ¶
    Source

    inst_c_ngl_s :: inst_c_ngl_s_f_f_cc

    inst_c_ngl_s_f_f_cc ¶
    Source

    inst_c_ngl_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ngle_d ¶
    Source

    inst_c_ngle_d :: inst_c_ngle_d_f_f_cc

    inst_c_ngle_d_f_f_cc ¶
    Source

    inst_c_ngle_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ngle_ps ¶
    Source

    inst_c_ngle_ps :: inst_c_ngle_ps_f_f_cc

    inst_c_ngle_ps_f_f_cc ¶
    Source

    inst_c_ngle_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ngle_s ¶
    Source

    inst_c_ngle_s :: inst_c_ngle_s_f_f_cc

    inst_c_ngle_s_f_f_cc ¶
    Source

    inst_c_ngle_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ngt_d ¶
    Source

    inst_c_ngt_d :: inst_c_ngt_d_f_f_cc

    inst_c_ngt_d_f_f_cc ¶
    Source

    inst_c_ngt_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ngt_ps ¶
    Source

    inst_c_ngt_ps :: inst_c_ngt_ps_f_f_cc

    inst_c_ngt_ps_f_f_cc ¶
    Source

    inst_c_ngt_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ngt_s ¶
    Source

    inst_c_ngt_s :: inst_c_ngt_s_f_f_cc

    inst_c_ngt_s_f_f_cc ¶
    Source

    inst_c_ngt_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ole_d ¶
    Source

    inst_c_ole_d :: inst_c_ole_d_f_f_cc

    inst_c_ole_d_f_f_cc ¶
    Source

    inst_c_ole_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ole_ps ¶
    Source

    inst_c_ole_ps :: inst_c_ole_ps_f_f_cc

    inst_c_ole_ps_f_f_cc ¶
    Source

    inst_c_ole_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ole_s ¶
    Source

    inst_c_ole_s :: inst_c_ole_s_f_f_cc

    inst_c_ole_s_f_f_cc ¶
    Source

    inst_c_ole_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_olt_d ¶
    Source

    inst_c_olt_d :: inst_c_olt_d_f_f_cc

    inst_c_olt_d_f_f_cc ¶
    Source

    inst_c_olt_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_olt_ps ¶
    Source

    inst_c_olt_ps :: inst_c_olt_ps_f_f_cc

    inst_c_olt_ps_f_f_cc ¶
    Source

    inst_c_olt_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_olt_s ¶
    Source

    inst_c_olt_s :: inst_c_olt_s_f_f_cc

    inst_c_olt_s_f_f_cc ¶
    Source

    inst_c_olt_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_seq_d ¶
    Source

    inst_c_seq_d :: inst_c_seq_d_f_f_cc

    inst_c_seq_d_f_f_cc ¶
    Source

    inst_c_seq_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_seq_ps ¶
    Source

    inst_c_seq_ps :: inst_c_seq_ps_f_f_cc

    inst_c_seq_ps_f_f_cc ¶
    Source

    inst_c_seq_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_seq_s ¶
    Source

    inst_c_seq_s :: inst_c_seq_s_f_f_cc

    inst_c_seq_s_f_f_cc ¶
    Source

    inst_c_seq_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_sf_d ¶
    Source

    inst_c_sf_d :: inst_c_sf_d_f_f_cc

    inst_c_sf_d_f_f_cc ¶
    Source

    inst_c_sf_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_sf_ps ¶
    Source

    inst_c_sf_ps :: inst_c_sf_ps_f_f_cc

    inst_c_sf_ps_f_f_cc ¶
    Source

    inst_c_sf_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_sf_s ¶
    Source

    inst_c_sf_s :: inst_c_sf_s_f_f_cc

    inst_c_sf_s_f_f_cc ¶
    Source

    inst_c_sf_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ueq_d ¶
    Source

    inst_c_ueq_d :: inst_c_ueq_d_f_f_cc

    inst_c_ueq_d_f_f_cc ¶
    Source

    inst_c_ueq_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ueq_ps ¶
    Source

    inst_c_ueq_ps :: inst_c_ueq_ps_f_f_cc

    inst_c_ueq_ps_f_f_cc ¶
    Source

    inst_c_ueq_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ueq_s ¶
    Source

    inst_c_ueq_s :: inst_c_ueq_s_f_f_cc

    inst_c_ueq_s_f_f_cc ¶
    Source

    inst_c_ueq_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ule_d ¶
    Source

    inst_c_ule_d :: inst_c_ule_d_f_f_cc

    inst_c_ule_d_f_f_cc ¶
    Source

    inst_c_ule_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ule_ps ¶
    Source

    inst_c_ule_ps :: inst_c_ule_ps_f_f_cc

    inst_c_ule_ps_f_f_cc ¶
    Source

    inst_c_ule_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ule_s ¶
    Source

    inst_c_ule_s :: inst_c_ule_s_f_f_cc

    inst_c_ule_s_f_f_cc ¶
    Source

    inst_c_ule_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ult_d ¶
    Source

    inst_c_ult_d :: inst_c_ult_d_f_f_cc

    inst_c_ult_d_f_f_cc ¶
    Source

    inst_c_ult_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ult_ps ¶
    Source

    inst_c_ult_ps :: inst_c_ult_ps_f_f_cc

    inst_c_ult_ps_f_f_cc ¶
    Source

    inst_c_ult_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_ult_s ¶
    Source

    inst_c_ult_s :: inst_c_ult_s_f_f_cc

    inst_c_ult_s_f_f_cc ¶
    Source

    inst_c_ult_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_un_d ¶
    Source

    inst_c_un_d :: inst_c_un_d_f_f_cc

    inst_c_un_d_f_f_cc ¶
    Source

    inst_c_un_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_un_ps ¶
    Source

    inst_c_un_ps :: inst_c_un_ps_f_f_cc

    inst_c_un_ps_f_f_cc ¶
    Source

    inst_c_un_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_c_un_s ¶
    Source

    inst_c_un_s :: inst_c_un_s_f_f_cc

    inst_c_un_s_f_f_cc ¶
    Source

    inst_c_un_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_cache ¶
    Source

    inst_cache :: inst_cache_i5_m

    inst_cache_i5_m ¶
    Source

    inst_cache_i5_m :: proc "contextless" (imm: i64, mem: Memory) -> Instruction {…}

    inst_cc ¶
    Source

    inst_cc :: inst_cc_none

    inst_cc_none ¶
    Source

    inst_cc_none :: proc "contextless" () -> Instruction {…}

    inst_cdp ¶
    Source

    inst_cdp :: inst_cdp_none

    inst_cdp_none ¶
    Source

    inst_cdp_none :: proc "contextless" () -> Instruction {…}

    inst_ceil_l_d ¶
    Source

    inst_ceil_l_d :: inst_ceil_l_d_f_f

    inst_ceil_l_d_f_f ¶
    Source

    inst_ceil_l_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_ceil_l_s ¶
    Source

    inst_ceil_l_s :: inst_ceil_l_s_f_f

    inst_ceil_l_s_f_f ¶
    Source

    inst_ceil_l_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_ceil_w_d ¶
    Source

    inst_ceil_w_d :: inst_ceil_w_d_f_f

    inst_ceil_w_d_f_f ¶
    Source

    inst_ceil_w_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_ceil_w_s ¶
    Source

    inst_ceil_w_s :: inst_ceil_w_s_f_f

    inst_ceil_w_s_f_f ¶
    Source

    inst_ceil_w_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_ceq_b ¶
    Source

    inst_ceq_b :: inst_ceq_b_w_w_w

    inst_ceq_b_w_w_w ¶
    Source

    inst_ceq_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_ceq_d ¶
    Source

    inst_ceq_d :: inst_ceq_d_w_w_w

    inst_ceq_d_w_w_w ¶
    Source

    inst_ceq_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_ceq_h ¶
    Source

    inst_ceq_h :: inst_ceq_h_w_w_w

    inst_ceq_h_w_w_w ¶
    Source

    inst_ceq_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_ceq_w ¶
    Source

    inst_ceq_w :: inst_ceq_w_w_w_w

    inst_ceq_w_w_w_w ¶
    Source

    inst_ceq_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_cfc1 ¶
    Source

    inst_cfc1 :: inst_cfc1_r_fcr

    inst_cfc1_r_fcr ¶
    Source

    inst_cfc1_r_fcr :: proc "contextless" (dst: GPR, src: Register) -> Instruction {…}

    inst_cfc2 ¶
    Source

    inst_cfc2 :: inst_cfc2_r_c2c

    inst_cfc2_r_c2c ¶
    Source

    inst_cfc2_r_c2c :: proc "contextless" (dst: GPR, src: GTE_CtrlReg) -> Instruction {…}

    inst_cle_s_b ¶
    Source

    inst_cle_s_b :: inst_cle_s_b_w_w_w

    inst_cle_s_b_w_w_w ¶
    Source

    inst_cle_s_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_cle_s_d ¶
    Source

    inst_cle_s_d :: inst_cle_s_d_w_w_w

    inst_cle_s_d_w_w_w ¶
    Source

    inst_cle_s_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_cle_s_h ¶
    Source

    inst_cle_s_h :: inst_cle_s_h_w_w_w

    inst_cle_s_h_w_w_w ¶
    Source

    inst_cle_s_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_cle_s_w ¶
    Source

    inst_cle_s_w :: inst_cle_s_w_w_w_w

    inst_cle_s_w_w_w_w ¶
    Source

    inst_cle_s_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_cle_u_b ¶
    Source

    inst_cle_u_b :: inst_cle_u_b_w_w_w

    inst_cle_u_b_w_w_w ¶
    Source

    inst_cle_u_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_cle_u_d ¶
    Source

    inst_cle_u_d :: inst_cle_u_d_w_w_w

    inst_cle_u_d_w_w_w ¶
    Source

    inst_cle_u_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_cle_u_h ¶
    Source

    inst_cle_u_h :: inst_cle_u_h_w_w_w

    inst_cle_u_h_w_w_w ¶
    Source

    inst_cle_u_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_cle_u_w ¶
    Source

    inst_cle_u_w :: inst_cle_u_w_w_w_w

    inst_cle_u_w_w_w_w ¶
    Source

    inst_cle_u_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_clo ¶
    Source

    inst_clo :: inst_clo_r_r

    inst_clo_r_r ¶
    Source

    inst_clo_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_clt_s_b ¶
    Source

    inst_clt_s_b :: inst_clt_s_b_w_w_w

    inst_clt_s_b_w_w_w ¶
    Source

    inst_clt_s_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_clt_s_d ¶
    Source

    inst_clt_s_d :: inst_clt_s_d_w_w_w

    inst_clt_s_d_w_w_w ¶
    Source

    inst_clt_s_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_clt_s_h ¶
    Source

    inst_clt_s_h :: inst_clt_s_h_w_w_w

    inst_clt_s_h_w_w_w ¶
    Source

    inst_clt_s_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_clt_s_w ¶
    Source

    inst_clt_s_w :: inst_clt_s_w_w_w_w

    inst_clt_s_w_w_w_w ¶
    Source

    inst_clt_s_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_clt_u_b ¶
    Source

    inst_clt_u_b :: inst_clt_u_b_w_w_w

    inst_clt_u_b_w_w_w ¶
    Source

    inst_clt_u_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_clt_u_d ¶
    Source

    inst_clt_u_d :: inst_clt_u_d_w_w_w

    inst_clt_u_d_w_w_w ¶
    Source

    inst_clt_u_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_clt_u_h ¶
    Source

    inst_clt_u_h :: inst_clt_u_h_w_w_w

    inst_clt_u_h_w_w_w ¶
    Source

    inst_clt_u_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_clt_u_w ¶
    Source

    inst_clt_u_w :: inst_clt_u_w_w_w_w

    inst_clt_u_w_w_w_w ¶
    Source

    inst_clt_u_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_clz ¶
    Source

    inst_clz :: inst_clz_r_r

    inst_clz_r_r ¶
    Source

    inst_clz_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_cmp_eq_ph ¶
    Source

    inst_cmp_eq_ph :: inst_cmp_eq_ph_r_r

    inst_cmp_eq_ph_r_r ¶
    Source

    inst_cmp_eq_ph_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_cmp_le_ph ¶
    Source

    inst_cmp_le_ph :: inst_cmp_le_ph_r_r

    inst_cmp_le_ph_r_r ¶
    Source

    inst_cmp_le_ph_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_cmp_lt_ph ¶
    Source

    inst_cmp_lt_ph :: inst_cmp_lt_ph_r_r

    inst_cmp_lt_ph_r_r ¶
    Source

    inst_cmp_lt_ph_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_cmpgu_eq_qb ¶
    Source

    inst_cmpgu_eq_qb :: inst_cmpgu_eq_qb_r_r_r

    inst_cmpgu_eq_qb_r_r_r ¶
    Source

    inst_cmpgu_eq_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_cmpgu_le_qb ¶
    Source

    inst_cmpgu_le_qb :: inst_cmpgu_le_qb_r_r_r

    inst_cmpgu_le_qb_r_r_r ¶
    Source

    inst_cmpgu_le_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_cmpgu_lt_qb ¶
    Source

    inst_cmpgu_lt_qb :: inst_cmpgu_lt_qb_r_r_r

    inst_cmpgu_lt_qb_r_r_r ¶
    Source

    inst_cmpgu_lt_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_cmpu_eq_qb ¶
    Source

    inst_cmpu_eq_qb :: inst_cmpu_eq_qb_r_r

    inst_cmpu_eq_qb_r_r ¶
    Source

    inst_cmpu_eq_qb_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_cmpu_le_qb ¶
    Source

    inst_cmpu_le_qb :: inst_cmpu_le_qb_r_r

    inst_cmpu_le_qb_r_r ¶
    Source

    inst_cmpu_le_qb_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_cmpu_lt_qb ¶
    Source

    inst_cmpu_lt_qb :: inst_cmpu_lt_qb_r_r

    inst_cmpu_lt_qb_r_r ¶
    Source

    inst_cmpu_lt_qb_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_copy_s_b ¶
    Source

    inst_copy_s_b :: inst_copy_s_b_r_w_i5

    inst_copy_s_b_r_w_i5 ¶
    Source

    inst_copy_s_b_r_w_i5 :: proc "contextless" (dst: GPR, src: Register, imm: i64) -> Instruction {…}

    inst_copy_s_h ¶
    Source

    inst_copy_s_h :: inst_copy_s_h_r_w_i5

    inst_copy_s_h_r_w_i5 ¶
    Source

    inst_copy_s_h_r_w_i5 :: proc "contextless" (dst: GPR, src: Register, imm: i64) -> Instruction {…}

    inst_copy_s_w ¶
    Source

    inst_copy_s_w :: inst_copy_s_w_r_w_i5

    inst_copy_s_w_r_w_i5 ¶
    Source

    inst_copy_s_w_r_w_i5 :: proc "contextless" (dst: GPR, src: Register, imm: i64) -> Instruction {…}

    inst_copy_u_b ¶
    Source

    inst_copy_u_b :: inst_copy_u_b_r_w_i5

    inst_copy_u_b_r_w_i5 ¶
    Source

    inst_copy_u_b_r_w_i5 :: proc "contextless" (dst: GPR, src: Register, imm: i64) -> Instruction {…}

    inst_copy_u_h ¶
    Source

    inst_copy_u_h :: inst_copy_u_h_r_w_i5

    inst_copy_u_h_r_w_i5 ¶
    Source

    inst_copy_u_h_r_w_i5 :: proc "contextless" (dst: GPR, src: Register, imm: i64) -> Instruction {…}

    inst_copy_u_w ¶
    Source

    inst_copy_u_w :: inst_copy_u_w_r_w_i5

    inst_copy_u_w_r_w_i5 ¶
    Source

    inst_copy_u_w_r_w_i5 :: proc "contextless" (dst: GPR, src: Register, imm: i64) -> Instruction {…}

    inst_cp0_sel ¶
    Source

    inst_cp0_sel :: proc "contextless" (m: Mnemonic, rt, rd: Register, sel: u8) -> Instruction {…}
     

    COP0 move with explicit selector: MFC0 $rt, $rd, sel (R2+).

    inst_crc32b ¶
    Source

    inst_crc32b :: inst_crc32b_r_r

    inst_crc32b_r_r ¶
    Source

    inst_crc32b_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_crc32cb ¶
    Source

    inst_crc32cb :: inst_crc32cb_r_r

    inst_crc32cb_r_r ¶
    Source

    inst_crc32cb_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_crc32cd ¶
    Source

    inst_crc32cd :: inst_crc32cd_r_r

    inst_crc32cd_r_r ¶
    Source

    inst_crc32cd_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_crc32ch ¶
    Source

    inst_crc32ch :: inst_crc32ch_r_r

    inst_crc32ch_r_r ¶
    Source

    inst_crc32ch_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_crc32cw ¶
    Source

    inst_crc32cw :: inst_crc32cw_r_r

    inst_crc32cw_r_r ¶
    Source

    inst_crc32cw_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_crc32d ¶
    Source

    inst_crc32d :: inst_crc32d_r_r

    inst_crc32d_r_r ¶
    Source

    inst_crc32d_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_crc32h ¶
    Source

    inst_crc32h :: inst_crc32h_r_r

    inst_crc32h_r_r ¶
    Source

    inst_crc32h_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_crc32w ¶
    Source

    inst_crc32w :: inst_crc32w_r_r

    inst_crc32w_r_r ¶
    Source

    inst_crc32w_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_ctc1 ¶
    Source

    inst_ctc1 :: inst_ctc1_r_fcr

    inst_ctc1_r_fcr ¶
    Source

    inst_ctc1_r_fcr :: proc "contextless" (dst: GPR, src: Register) -> Instruction {…}

    inst_ctc2 ¶
    Source

    inst_ctc2 :: inst_ctc2_r_c2c

    inst_ctc2_r_c2c ¶
    Source

    inst_ctc2_r_c2c :: proc "contextless" (dst: GPR, src: GTE_CtrlReg) -> Instruction {…}

    inst_cvt_d_l ¶
    Source

    inst_cvt_d_l :: inst_cvt_d_l_f_f

    inst_cvt_d_l_f_f ¶
    Source

    inst_cvt_d_l_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_cvt_d_s ¶
    Source

    inst_cvt_d_s :: inst_cvt_d_s_f_f

    inst_cvt_d_s_f_f ¶
    Source

    inst_cvt_d_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_cvt_d_w ¶
    Source

    inst_cvt_d_w :: inst_cvt_d_w_f_f

    inst_cvt_d_w_f_f ¶
    Source

    inst_cvt_d_w_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_cvt_l_d ¶
    Source

    inst_cvt_l_d :: inst_cvt_l_d_f_f

    inst_cvt_l_d_f_f ¶
    Source

    inst_cvt_l_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_cvt_l_s ¶
    Source

    inst_cvt_l_s :: inst_cvt_l_s_f_f

    inst_cvt_l_s_f_f ¶
    Source

    inst_cvt_l_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_cvt_ps_s ¶
    Source

    inst_cvt_ps_s :: inst_cvt_ps_s_f_f_f

    inst_cvt_ps_s_f_f_f ¶
    Source

    inst_cvt_ps_s_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_cvt_s_d ¶
    Source

    inst_cvt_s_d :: inst_cvt_s_d_f_f

    inst_cvt_s_d_f_f ¶
    Source

    inst_cvt_s_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_cvt_s_l ¶
    Source

    inst_cvt_s_l :: inst_cvt_s_l_f_f

    inst_cvt_s_l_f_f ¶
    Source

    inst_cvt_s_l_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_cvt_s_pl ¶
    Source

    inst_cvt_s_pl :: inst_cvt_s_pl_f_f

    inst_cvt_s_pl_f_f ¶
    Source

    inst_cvt_s_pl_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_cvt_s_pu ¶
    Source

    inst_cvt_s_pu :: inst_cvt_s_pu_f_f

    inst_cvt_s_pu_f_f ¶
    Source

    inst_cvt_s_pu_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_cvt_s_w ¶
    Source

    inst_cvt_s_w :: inst_cvt_s_w_f_f

    inst_cvt_s_w_f_f ¶
    Source

    inst_cvt_s_w_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_cvt_w_d ¶
    Source

    inst_cvt_w_d :: inst_cvt_w_d_f_f

    inst_cvt_w_d_f_f ¶
    Source

    inst_cvt_w_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_cvt_w_s ¶
    Source

    inst_cvt_w_s :: inst_cvt_w_s_f_f

    inst_cvt_w_s_f_f ¶
    Source

    inst_cvt_w_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_dadd ¶
    Source

    inst_dadd :: inst_dadd_r_r_r

    inst_dadd_r_r_r ¶
    Source

    inst_dadd_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_daddi ¶
    Source

    inst_daddi :: inst_daddi_r_r_i16

    inst_daddi_r_r_i16 ¶
    Source

    inst_daddi_r_r_i16 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_daddiu ¶
    Source

    inst_daddiu :: inst_daddiu_r_r_i16

    inst_daddiu_r_r_i16 ¶
    Source

    inst_daddiu_r_r_i16 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_daddu ¶
    Source

    inst_daddu :: inst_daddu_r_r_r

    inst_daddu_r_r_r ¶
    Source

    inst_daddu_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dahi ¶
    Source

    inst_dahi :: inst_dahi_r_u16

    inst_dahi_r_u16 ¶
    Source

    inst_dahi_r_u16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_dalign ¶
    Source

    inst_dalign :: inst_dalign_r_r_r_i5

    inst_dalign_r_r_r_i5 ¶
    Source

    inst_dalign_r_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, src2: GPR, imm: i64) -> Instruction {…}

    inst_dati ¶
    Source

    inst_dati :: inst_dati_r_u16

    inst_dati_r_u16 ¶
    Source

    inst_dati_r_u16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_daui ¶
    Source

    inst_daui :: inst_daui_r_r_u16

    inst_daui_r_r_u16 ¶
    Source

    inst_daui_r_r_u16 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_dbitswap ¶
    Source

    inst_dbitswap :: inst_dbitswap_r_r

    inst_dbitswap_r_r ¶
    Source

    inst_dbitswap_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_dclo ¶
    Source

    inst_dclo :: inst_dclo_r_r

    inst_dclo_r_r ¶
    Source

    inst_dclo_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_dclz ¶
    Source

    inst_dclz :: inst_dclz_r_r

    inst_dclz_r_r ¶
    Source

    inst_dclz_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_dcpl ¶
    Source

    inst_dcpl :: inst_dcpl_none

    inst_dcpl_none ¶
    Source

    inst_dcpl_none :: proc "contextless" () -> Instruction {…}

    inst_ddiv ¶
    Source

    inst_ddiv :: inst_ddiv_r_r

    inst_ddiv_r6 ¶
    Source

    inst_ddiv_r6 :: inst_ddiv_r6_r_r_r

    inst_ddiv_r6_r_r_r ¶
    Source

    inst_ddiv_r6_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_ddiv_r_r ¶
    Source

    inst_ddiv_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_ddivu ¶
    Source

    inst_ddivu :: inst_ddivu_r_r

    inst_ddivu_r6 ¶
    Source

    inst_ddivu_r6 :: inst_ddivu_r6_r_r_r

    inst_ddivu_r6_r_r_r ¶
    Source

    inst_ddivu_r6_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_ddivu_r_r ¶
    Source

    inst_ddivu_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_deret ¶
    Source

    inst_deret :: inst_deret_none

    inst_deret_none ¶
    Source

    inst_deret_none :: proc "contextless" () -> Instruction {…}

    inst_dext ¶
    Source

    inst_dext :: inst_dext_r_r_i5_i5

    inst_dext_r_r_i5_i5 ¶
    Source

    inst_dext_r_r_i5_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_dextm ¶
    Source

    inst_dextm :: inst_dextm_r_r_i5_i5

    inst_dextm_r_r_i5_i5 ¶
    Source

    inst_dextm_r_r_i5_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_dextu ¶
    Source

    inst_dextu :: inst_dextu_r_r_i5_i5

    inst_dextu_r_r_i5_i5 ¶
    Source

    inst_dextu_r_r_i5_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_di ¶
    Source

    inst_di :: inst_di_r

    inst_di_r ¶
    Source

    inst_di_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_dins ¶
    Source

    inst_dins :: inst_dins_r_r_i5_i5

    inst_dins_r_r_i5_i5 ¶
    Source

    inst_dins_r_r_i5_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_dinsm ¶
    Source

    inst_dinsm :: inst_dinsm_r_r_i5_i5

    inst_dinsm_r_r_i5_i5 ¶
    Source

    inst_dinsm_r_r_i5_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_dinsu ¶
    Source

    inst_dinsu :: inst_dinsu_r_r_i5_i5

    inst_dinsu_r_r_i5_i5 ¶
    Source

    inst_dinsu_r_r_i5_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_div ¶
    Source

    inst_div :: inst_div_r_r

    inst_div1 ¶
    Source

    inst_div1 :: inst_div1_r_r

    inst_div1_r_r ¶
    Source

    inst_div1_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_div_d ¶
    Source

    inst_div_d :: inst_div_d_f_f_f

    inst_div_d_f_f_f ¶
    Source

    inst_div_d_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_div_r_r ¶
    Source

    inst_div_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_div_s ¶
    Source

    inst_div_s :: inst_div_s_f_f_f

    inst_div_s_b ¶
    Source

    inst_div_s_b :: inst_div_s_b_w_w_w

    inst_div_s_b_w_w_w ¶
    Source

    inst_div_s_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_div_s_d ¶
    Source

    inst_div_s_d :: inst_div_s_d_w_w_w

    inst_div_s_d_w_w_w ¶
    Source

    inst_div_s_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_div_s_f_f_f ¶
    Source

    inst_div_s_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_div_s_h ¶
    Source

    inst_div_s_h :: inst_div_s_h_w_w_w

    inst_div_s_h_w_w_w ¶
    Source

    inst_div_s_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_div_s_w ¶
    Source

    inst_div_s_w :: inst_div_s_w_w_w_w

    inst_div_s_w_w_w_w ¶
    Source

    inst_div_s_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_div_u_b ¶
    Source

    inst_div_u_b :: inst_div_u_b_w_w_w

    inst_div_u_b_w_w_w ¶
    Source

    inst_div_u_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_div_u_d ¶
    Source

    inst_div_u_d :: inst_div_u_d_w_w_w

    inst_div_u_d_w_w_w ¶
    Source

    inst_div_u_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_div_u_h ¶
    Source

    inst_div_u_h :: inst_div_u_h_w_w_w

    inst_div_u_h_w_w_w ¶
    Source

    inst_div_u_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_div_u_w ¶
    Source

    inst_div_u_w :: inst_div_u_w_w_w_w

    inst_div_u_w_w_w_w ¶
    Source

    inst_div_u_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_divu ¶
    Source

    inst_divu :: inst_divu_r_r

    inst_divu1 ¶
    Source

    inst_divu1 :: inst_divu1_r_r

    inst_divu1_r_r ¶
    Source

    inst_divu1_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_divu_r_r ¶
    Source

    inst_divu_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_dlsa ¶
    Source

    inst_dlsa :: inst_dlsa_r_r_r_i5

    inst_dlsa_r_r_r_i5 ¶
    Source

    inst_dlsa_r_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, src2: GPR, imm: i64) -> Instruction {…}

    inst_dmfc0 ¶
    Source

    inst_dmfc0 :: inst_dmfc0_r_c0_sel

    inst_dmfc0_r_c0_sel ¶
    Source

    inst_dmfc0_r_c0_sel :: proc "contextless" (dst: GPR, src: CP0_Reg, imm: i64) -> Instruction {…}

    inst_dmfc1 ¶
    Source

    inst_dmfc1 :: inst_dmfc1_r_f

    inst_dmfc1_r_f ¶
    Source

    inst_dmfc1_r_f :: proc "contextless" (dst: GPR, src: FPR) -> Instruction {…}

    inst_dmod ¶
    Source

    inst_dmod :: inst_dmod_r_r_r

    inst_dmod_r_r_r ¶
    Source

    inst_dmod_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dmodu ¶
    Source

    inst_dmodu :: inst_dmodu_r_r_r

    inst_dmodu_r_r_r ¶
    Source

    inst_dmodu_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dmtc0 ¶
    Source

    inst_dmtc0 :: inst_dmtc0_r_c0_sel

    inst_dmtc0_r_c0_sel ¶
    Source

    inst_dmtc0_r_c0_sel :: proc "contextless" (dst: GPR, src: CP0_Reg, imm: i64) -> Instruction {…}

    inst_dmtc1 ¶
    Source

    inst_dmtc1 :: inst_dmtc1_r_f

    inst_dmtc1_r_f ¶
    Source

    inst_dmtc1_r_f :: proc "contextless" (dst: GPR, src: FPR) -> Instruction {…}

    inst_dmuh ¶
    Source

    inst_dmuh :: inst_dmuh_r_r_r

    inst_dmuh_r_r_r ¶
    Source

    inst_dmuh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dmuhu ¶
    Source

    inst_dmuhu :: inst_dmuhu_r_r_r

    inst_dmuhu_r_r_r ¶
    Source

    inst_dmuhu_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dmul_r6 ¶
    Source

    inst_dmul_r6 :: inst_dmul_r6_r_r_r

    inst_dmul_r6_r_r_r ¶
    Source

    inst_dmul_r6_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dmult ¶
    Source

    inst_dmult :: inst_dmult_r_r

    inst_dmult_r_r ¶
    Source

    inst_dmult_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_dmultu ¶
    Source

    inst_dmultu :: inst_dmultu_r_r

    inst_dmultu_r_r ¶
    Source

    inst_dmultu_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_dmulu ¶
    Source

    inst_dmulu :: inst_dmulu_r_r_r

    inst_dmulu_r_r_r ¶
    Source

    inst_dmulu_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dotp_s_d ¶
    Source

    inst_dotp_s_d :: inst_dotp_s_d_w_w_w

    inst_dotp_s_d_w_w_w ¶
    Source

    inst_dotp_s_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_dotp_s_h ¶
    Source

    inst_dotp_s_h :: inst_dotp_s_h_w_w_w

    inst_dotp_s_h_w_w_w ¶
    Source

    inst_dotp_s_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_dotp_s_w ¶
    Source

    inst_dotp_s_w :: inst_dotp_s_w_w_w_w

    inst_dotp_s_w_w_w_w ¶
    Source

    inst_dotp_s_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_dotp_u_d ¶
    Source

    inst_dotp_u_d :: inst_dotp_u_d_w_w_w

    inst_dotp_u_d_w_w_w ¶
    Source

    inst_dotp_u_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_dotp_u_h ¶
    Source

    inst_dotp_u_h :: inst_dotp_u_h_w_w_w

    inst_dotp_u_h_w_w_w ¶
    Source

    inst_dotp_u_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_dotp_u_w ¶
    Source

    inst_dotp_u_w :: inst_dotp_u_w_w_w_w

    inst_dotp_u_w_w_w_w ¶
    Source

    inst_dotp_u_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_dpa_w_ph ¶
    Source

    inst_dpa_w_ph :: inst_dpa_w_ph_i5_r_r

    inst_dpa_w_ph_i5_r_r ¶
    Source

    inst_dpa_w_ph_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_dpaq_s_w_ph ¶
    Source

    inst_dpaq_s_w_ph :: inst_dpaq_s_w_ph_i5_r_r

    inst_dpaq_s_w_ph_i5_r_r ¶
    Source

    inst_dpaq_s_w_ph_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_dpaq_sa_l_w ¶
    Source

    inst_dpaq_sa_l_w :: inst_dpaq_sa_l_w_i5_r_r

    inst_dpaq_sa_l_w_i5_r_r ¶
    Source

    inst_dpaq_sa_l_w_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_dpau_h_qbl ¶
    Source

    inst_dpau_h_qbl :: inst_dpau_h_qbl_i5_r_r

    inst_dpau_h_qbl_i5_r_r ¶
    Source

    inst_dpau_h_qbl_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_dpau_h_qbr ¶
    Source

    inst_dpau_h_qbr :: inst_dpau_h_qbr_i5_r_r

    inst_dpau_h_qbr_i5_r_r ¶
    Source

    inst_dpau_h_qbr_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_dpax_w_ph ¶
    Source

    inst_dpax_w_ph :: inst_dpax_w_ph_i5_r_r

    inst_dpax_w_ph_i5_r_r ¶
    Source

    inst_dpax_w_ph_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_dpcs ¶
    Source

    inst_dpcs :: inst_dpcs_none

    inst_dpcs_none ¶
    Source

    inst_dpcs_none :: proc "contextless" () -> Instruction {…}

    inst_dpct ¶
    Source

    inst_dpct :: inst_dpct_none

    inst_dpct_none ¶
    Source

    inst_dpct_none :: proc "contextless" () -> Instruction {…}

    inst_dps_w_ph ¶
    Source

    inst_dps_w_ph :: inst_dps_w_ph_i5_r_r

    inst_dps_w_ph_i5_r_r ¶
    Source

    inst_dps_w_ph_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_dpsq_s_w_ph ¶
    Source

    inst_dpsq_s_w_ph :: inst_dpsq_s_w_ph_i5_r_r

    inst_dpsq_s_w_ph_i5_r_r ¶
    Source

    inst_dpsq_s_w_ph_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_dpsq_sa_l_w ¶
    Source

    inst_dpsq_sa_l_w :: inst_dpsq_sa_l_w_i5_r_r

    inst_dpsq_sa_l_w_i5_r_r ¶
    Source

    inst_dpsq_sa_l_w_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_dpsu_h_qbl ¶
    Source

    inst_dpsu_h_qbl :: inst_dpsu_h_qbl_i5_r_r

    inst_dpsu_h_qbl_i5_r_r ¶
    Source

    inst_dpsu_h_qbl_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_dpsu_h_qbr ¶
    Source

    inst_dpsu_h_qbr :: inst_dpsu_h_qbr_i5_r_r

    inst_dpsu_h_qbr_i5_r_r ¶
    Source

    inst_dpsu_h_qbr_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_dpsx_w_ph ¶
    Source

    inst_dpsx_w_ph :: inst_dpsx_w_ph_i5_r_r

    inst_dpsx_w_ph_i5_r_r ¶
    Source

    inst_dpsx_w_ph_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_drotr ¶
    Source

    inst_drotr :: inst_drotr_r_r_i5

    inst_drotr32 ¶
    Source

    inst_drotr32 :: inst_drotr32_r_r_i5

    inst_drotr32_r_r_i5 ¶
    Source

    inst_drotr32_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_drotr_r_r_i5 ¶
    Source

    inst_drotr_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_drotrv ¶
    Source

    inst_drotrv :: inst_drotrv_r_r_r

    inst_drotrv_r_r_r ¶
    Source

    inst_drotrv_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dsbh ¶
    Source

    inst_dsbh :: inst_dsbh_r_r

    inst_dsbh_r_r ¶
    Source

    inst_dsbh_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_dshd ¶
    Source

    inst_dshd :: inst_dshd_r_r

    inst_dshd_r_r ¶
    Source

    inst_dshd_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_dsll ¶
    Source

    inst_dsll :: inst_dsll_r_r_i5

    inst_dsll32 ¶
    Source

    inst_dsll32 :: inst_dsll32_r_r_i5

    inst_dsll32_r_r_i5 ¶
    Source

    inst_dsll32_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_dsll_r_r_i5 ¶
    Source

    inst_dsll_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_dsllv ¶
    Source

    inst_dsllv :: inst_dsllv_r_r_r

    inst_dsllv_r_r_r ¶
    Source

    inst_dsllv_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dsra ¶
    Source

    inst_dsra :: inst_dsra_r_r_i5

    inst_dsra32 ¶
    Source

    inst_dsra32 :: inst_dsra32_r_r_i5

    inst_dsra32_r_r_i5 ¶
    Source

    inst_dsra32_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_dsra_r_r_i5 ¶
    Source

    inst_dsra_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_dsrav ¶
    Source

    inst_dsrav :: inst_dsrav_r_r_r

    inst_dsrav_r_r_r ¶
    Source

    inst_dsrav_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dsrl ¶
    Source

    inst_dsrl :: inst_dsrl_r_r_i5

    inst_dsrl32 ¶
    Source

    inst_dsrl32 :: inst_dsrl32_r_r_i5

    inst_dsrl32_r_r_i5 ¶
    Source

    inst_dsrl32_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_dsrl_r_r_i5 ¶
    Source

    inst_dsrl_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_dsrlv ¶
    Source

    inst_dsrlv :: inst_dsrlv_r_r_r

    inst_dsrlv_r_r_r ¶
    Source

    inst_dsrlv_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dsub ¶
    Source

    inst_dsub :: inst_dsub_r_r_r

    inst_dsub_r_r_r ¶
    Source

    inst_dsub_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_dsubu ¶
    Source

    inst_dsubu :: inst_dsubu_r_r_r

    inst_dsubu_r_r_r ¶
    Source

    inst_dsubu_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_ehb ¶
    Source

    inst_ehb :: inst_ehb_none

    inst_ehb_none ¶
    Source

    inst_ehb_none :: proc "contextless" () -> Instruction {…}

    inst_ei ¶
    Source

    inst_ei :: inst_ei_r

    inst_ei_r ¶
    Source

    inst_ei_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_eret ¶
    Source

    inst_eret :: inst_eret_none

    inst_eret_none ¶
    Source

    inst_eret_none :: proc "contextless" () -> Instruction {…}

    inst_ext ¶
    Source

    inst_ext :: inst_ext_r_r_i5_i5

    inst_ext_r_r_i5_i5 ¶
    Source

    inst_ext_r_r_i5_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_extp ¶
    Source

    inst_extp :: inst_extp_r_i5_i5

    inst_extp_r_i5_i5 ¶
    Source

    inst_extp_r_i5_i5 :: proc "contextless" (dst: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_extpdp ¶
    Source

    inst_extpdp :: inst_extpdp_r_i5_i5

    inst_extpdp_r_i5_i5 ¶
    Source

    inst_extpdp_r_i5_i5 :: proc "contextless" (dst: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_extpdpv ¶
    Source

    inst_extpdpv :: inst_extpdpv_r_i5_r

    inst_extpdpv_r_i5_r ¶
    Source

    inst_extpdpv_r_i5_r :: proc "contextless" (dst: GPR, imm: i64, src: GPR) -> Instruction {…}

    inst_extpv ¶
    Source

    inst_extpv :: inst_extpv_r_i5_r

    inst_extpv_r_i5_r ¶
    Source

    inst_extpv_r_i5_r :: proc "contextless" (dst: GPR, imm: i64, src: GPR) -> Instruction {…}

    inst_extr_r_w ¶
    Source

    inst_extr_r_w :: inst_extr_r_w_r_i5_i5

    inst_extr_r_w_r_i5_i5 ¶
    Source

    inst_extr_r_w_r_i5_i5 :: proc "contextless" (dst: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_extr_rs_w ¶
    Source

    inst_extr_rs_w :: inst_extr_rs_w_r_i5_i5

    inst_extr_rs_w_r_i5_i5 ¶
    Source

    inst_extr_rs_w_r_i5_i5 :: proc "contextless" (dst: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_extr_s_h ¶
    Source

    inst_extr_s_h :: inst_extr_s_h_r_i5_i5

    inst_extr_s_h_r_i5_i5 ¶
    Source

    inst_extr_s_h_r_i5_i5 :: proc "contextless" (dst: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_extr_w ¶
    Source

    inst_extr_w :: inst_extr_w_r_i5_i5

    inst_extr_w_r_i5_i5 ¶
    Source

    inst_extr_w_r_i5_i5 :: proc "contextless" (dst: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_extrv_r_w ¶
    Source

    inst_extrv_r_w :: inst_extrv_r_w_r_i5_r

    inst_extrv_r_w_r_i5_r ¶
    Source

    inst_extrv_r_w_r_i5_r :: proc "contextless" (dst: GPR, imm: i64, src: GPR) -> Instruction {…}

    inst_extrv_rs_w ¶
    Source

    inst_extrv_rs_w :: inst_extrv_rs_w_r_i5_r

    inst_extrv_rs_w_r_i5_r ¶
    Source

    inst_extrv_rs_w_r_i5_r :: proc "contextless" (dst: GPR, imm: i64, src: GPR) -> Instruction {…}

    inst_extrv_s_h ¶
    Source

    inst_extrv_s_h :: inst_extrv_s_h_r_i5_r

    inst_extrv_s_h_r_i5_r ¶
    Source

    inst_extrv_s_h_r_i5_r :: proc "contextless" (dst: GPR, imm: i64, src: GPR) -> Instruction {…}

    inst_extrv_w ¶
    Source

    inst_extrv_w :: inst_extrv_w_r_i5_r

    inst_extrv_w_r_i5_r ¶
    Source

    inst_extrv_w_r_i5_r :: proc "contextless" (dst: GPR, imm: i64, src: GPR) -> Instruction {…}

    inst_fadd_d ¶
    Source

    inst_fadd_d :: inst_fadd_d_w_w_w

    inst_fadd_d_w_w_w ¶
    Source

    inst_fadd_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fadd_w ¶
    Source

    inst_fadd_w :: inst_fadd_w_w_w_w

    inst_fadd_w_w_w_w ¶
    Source

    inst_fadd_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fceq_d ¶
    Source

    inst_fceq_d :: inst_fceq_d_w_w_w

    inst_fceq_d_w_w_w ¶
    Source

    inst_fceq_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fceq_w ¶
    Source

    inst_fceq_w :: inst_fceq_w_w_w_w

    inst_fceq_w_w_w_w ¶
    Source

    inst_fceq_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fcle_d ¶
    Source

    inst_fcle_d :: inst_fcle_d_w_w_w

    inst_fcle_d_w_w_w ¶
    Source

    inst_fcle_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fcle_w ¶
    Source

    inst_fcle_w :: inst_fcle_w_w_w_w

    inst_fcle_w_w_w_w ¶
    Source

    inst_fcle_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fclt_d ¶
    Source

    inst_fclt_d :: inst_fclt_d_w_w_w

    inst_fclt_d_w_w_w ¶
    Source

    inst_fclt_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fclt_w ¶
    Source

    inst_fclt_w :: inst_fclt_w_w_w_w

    inst_fclt_w_w_w_w ¶
    Source

    inst_fclt_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fcne_d ¶
    Source

    inst_fcne_d :: inst_fcne_d_w_w_w

    inst_fcne_d_w_w_w ¶
    Source

    inst_fcne_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fcne_w ¶
    Source

    inst_fcne_w :: inst_fcne_w_w_w_w

    inst_fcne_w_w_w_w ¶
    Source

    inst_fcne_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fcvt_d_w ¶
    Source

    inst_fcvt_d_w :: inst_fcvt_d_w_f_f

    inst_fcvt_d_w_f_f ¶
    Source

    inst_fcvt_d_w_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_fcvt_s_d ¶
    Source

    inst_fcvt_s_d :: inst_fcvt_s_d_f_f

    inst_fcvt_s_d_f_f ¶
    Source

    inst_fcvt_s_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_fcvt_s_w ¶
    Source

    inst_fcvt_s_w :: inst_fcvt_s_w_f_f

    inst_fcvt_s_w_f_f ¶
    Source

    inst_fcvt_s_w_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_fdiv_d ¶
    Source

    inst_fdiv_d :: inst_fdiv_d_w_w_w

    inst_fdiv_d_w_w_w ¶
    Source

    inst_fdiv_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fdiv_w ¶
    Source

    inst_fdiv_w :: inst_fdiv_w_w_w_w

    inst_fdiv_w_w_w_w ¶
    Source

    inst_fdiv_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_ffint_s_d ¶
    Source

    inst_ffint_s_d :: inst_ffint_s_d_w_w

    inst_ffint_s_d_w_w ¶
    Source

    inst_ffint_s_d_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_ffint_s_w ¶
    Source

    inst_ffint_s_w :: inst_ffint_s_w_w_w

    inst_ffint_s_w_w_w ¶
    Source

    inst_ffint_s_w_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_ffint_u_d ¶
    Source

    inst_ffint_u_d :: inst_ffint_u_d_w_w

    inst_ffint_u_d_w_w ¶
    Source

    inst_ffint_u_d_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_ffint_u_w ¶
    Source

    inst_ffint_u_w :: inst_ffint_u_w_w_w

    inst_ffint_u_w_w_w ¶
    Source

    inst_ffint_u_w_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_floor_l_d ¶
    Source

    inst_floor_l_d :: inst_floor_l_d_f_f

    inst_floor_l_d_f_f ¶
    Source

    inst_floor_l_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_floor_l_s ¶
    Source

    inst_floor_l_s :: inst_floor_l_s_f_f

    inst_floor_l_s_f_f ¶
    Source

    inst_floor_l_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_floor_w_d ¶
    Source

    inst_floor_w_d :: inst_floor_w_d_f_f

    inst_floor_w_d_f_f ¶
    Source

    inst_floor_w_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_floor_w_s ¶
    Source

    inst_floor_w_s :: inst_floor_w_s_f_f

    inst_floor_w_s_f_f ¶
    Source

    inst_floor_w_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_fmax_d ¶
    Source

    inst_fmax_d :: inst_fmax_d_w_w_w

    inst_fmax_d_w_w_w ¶
    Source

    inst_fmax_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fmax_w ¶
    Source

    inst_fmax_w :: inst_fmax_w_w_w_w

    inst_fmax_w_w_w_w ¶
    Source

    inst_fmax_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fmin_d ¶
    Source

    inst_fmin_d :: inst_fmin_d_w_w_w

    inst_fmin_d_w_w_w ¶
    Source

    inst_fmin_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fmin_w ¶
    Source

    inst_fmin_w :: inst_fmin_w_w_w_w

    inst_fmin_w_w_w_w ¶
    Source

    inst_fmin_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fmul_d ¶
    Source

    inst_fmul_d :: inst_fmul_d_w_w_w

    inst_fmul_d_w_w_w ¶
    Source

    inst_fmul_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fmul_w ¶
    Source

    inst_fmul_w :: inst_fmul_w_w_w_w

    inst_fmul_w_w_w_w ¶
    Source

    inst_fmul_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_frcp_d ¶
    Source

    inst_frcp_d :: inst_frcp_d_w_w

    inst_frcp_d_w_w ¶
    Source

    inst_frcp_d_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_frcp_w ¶
    Source

    inst_frcp_w :: inst_frcp_w_w_w

    inst_frcp_w_w_w ¶
    Source

    inst_frcp_w_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_frint_d ¶
    Source

    inst_frint_d :: inst_frint_d_w_w

    inst_frint_d_w_w ¶
    Source

    inst_frint_d_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_frint_w ¶
    Source

    inst_frint_w :: inst_frint_w_w_w

    inst_frint_w_w_w ¶
    Source

    inst_frint_w_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_frsqrt_d ¶
    Source

    inst_frsqrt_d :: inst_frsqrt_d_w_w

    inst_frsqrt_d_w_w ¶
    Source

    inst_frsqrt_d_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_frsqrt_w ¶
    Source

    inst_frsqrt_w :: inst_frsqrt_w_w_w

    inst_frsqrt_w_w_w ¶
    Source

    inst_frsqrt_w_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_fsqrt_d ¶
    Source

    inst_fsqrt_d :: inst_fsqrt_d_w_w

    inst_fsqrt_d_w_w ¶
    Source

    inst_fsqrt_d_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_fsqrt_w ¶
    Source

    inst_fsqrt_w :: inst_fsqrt_w_w_w

    inst_fsqrt_w_w_w ¶
    Source

    inst_fsqrt_w_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_fsub_d ¶
    Source

    inst_fsub_d :: inst_fsub_d_w_w_w

    inst_fsub_d_w_w_w ¶
    Source

    inst_fsub_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_fsub_w ¶
    Source

    inst_fsub_w :: inst_fsub_w_w_w_w

    inst_fsub_w_w_w_w ¶
    Source

    inst_fsub_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_ftrunc_s_d ¶
    Source

    inst_ftrunc_s_d :: inst_ftrunc_s_d_w_w

    inst_ftrunc_s_d_w_w ¶
    Source

    inst_ftrunc_s_d_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_ftrunc_s_w ¶
    Source

    inst_ftrunc_s_w :: inst_ftrunc_s_w_w_w

    inst_ftrunc_s_w_w_w ¶
    Source

    inst_ftrunc_s_w_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_ftrunc_u_d ¶
    Source

    inst_ftrunc_u_d :: inst_ftrunc_u_d_w_w

    inst_ftrunc_u_d_w_w ¶
    Source

    inst_ftrunc_u_d_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_ftrunc_u_w ¶
    Source

    inst_ftrunc_u_w :: inst_ftrunc_u_w_w_w

    inst_ftrunc_u_w_w_w ¶
    Source

    inst_ftrunc_u_w_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_gpf ¶
    Source

    inst_gpf :: inst_gpf_none

    inst_gpf_none ¶
    Source

    inst_gpf_none :: proc "contextless" () -> Instruction {…}

    inst_gpl ¶
    Source

    inst_gpl :: inst_gpl_none

    inst_gpl_none ¶
    Source

    inst_gpl_none :: proc "contextless" () -> Instruction {…}

    inst_i ¶
    Source

    inst_i :: proc "contextless" (m: Mnemonic, imm: i64) -> Instruction {…}
     

    Single-operand: JR $rs, JALR $rd (with implicit RA), MFHI/MFLO/MTHI/MTLO, SYSCALL/BREAK take an imm code so they use inst_i below.

    inst_ins ¶
    Source

    inst_ins :: inst_ins_r_r_i5_i5

    inst_ins_r_r_i5_i5 ¶
    Source

    inst_ins_r_r_i5_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_insert_b ¶
    Source

    inst_insert_b :: inst_insert_b_w_r_i5

    inst_insert_b_w_r_i5 ¶
    Source

    inst_insert_b_w_r_i5 :: proc "contextless" (dst: Register, src: GPR, imm: i64) -> Instruction {…}

    inst_insert_d ¶
    Source

    inst_insert_d :: inst_insert_d_w_r_i5

    inst_insert_d_w_r_i5 ¶
    Source

    inst_insert_d_w_r_i5 :: proc "contextless" (dst: Register, src: GPR, imm: i64) -> Instruction {…}

    inst_insert_h ¶
    Source

    inst_insert_h :: inst_insert_h_w_r_i5

    inst_insert_h_w_r_i5 ¶
    Source

    inst_insert_h_w_r_i5 :: proc "contextless" (dst: Register, src: GPR, imm: i64) -> Instruction {…}

    inst_insert_w ¶
    Source

    inst_insert_w :: inst_insert_w_w_r_i5

    inst_insert_w_w_r_i5 ¶
    Source

    inst_insert_w_w_r_i5 :: proc "contextless" (dst: Register, src: GPR, imm: i64) -> Instruction {…}

    inst_insv ¶
    Source

    inst_insv :: inst_insv_r_r

    inst_insv_r_r ¶
    Source

    inst_insv_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_insve_b ¶
    Source

    inst_insve_b :: inst_insve_b_w_w_i5

    inst_insve_b_w_w_i5 ¶
    Source

    inst_insve_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_insve_d ¶
    Source

    inst_insve_d :: inst_insve_d_w_w_i5

    inst_insve_d_w_w_i5 ¶
    Source

    inst_insve_d_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_insve_h ¶
    Source

    inst_insve_h :: inst_insve_h_w_w_i5

    inst_insve_h_w_w_i5 ¶
    Source

    inst_insve_h_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_insve_w ¶
    Source

    inst_insve_w :: inst_insve_w_w_w_i5

    inst_insve_w_w_w_i5 ¶
    Source

    inst_insve_w_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_intpl ¶
    Source

    inst_intpl :: inst_intpl_none

    inst_intpl_none ¶
    Source

    inst_intpl_none :: proc "contextless" () -> Instruction {…}

    inst_j ¶
    Source

    inst_j :: inst_j_j

    inst_j_j ¶
    Source

    inst_j_j :: proc "contextless" (target: u32) -> Instruction {…}

    inst_jal ¶
    Source

    inst_jal :: inst_jal_j

    inst_jal_j ¶
    Source

    inst_jal_j :: proc "contextless" (target: u32) -> Instruction {…}

    inst_jalr ¶
    Source

    inst_jalr :: inst_jalr_r_r

    inst_jalr_r_r ¶
    Source

    inst_jalr_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_jialc ¶
    Source

    inst_jialc :: inst_jialc_r_i16

    inst_jialc_r_i16 ¶
    Source

    inst_jialc_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_jic ¶
    Source

    inst_jic :: inst_jic_r_i16

    inst_jic_r_i16 ¶
    Source

    inst_jic_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_jr ¶
    Source

    inst_jr :: inst_jr_r

    inst_jr_r ¶
    Source

    inst_jr_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_jump ¶
    Source

    inst_jump :: proc "contextless" (m: Mnemonic, label_id: u32) -> Instruction {…}
     

    J-type jump (J/JAL: target only).

    inst_lb ¶
    Source

    inst_lb :: inst_lb_r_m

    inst_lb_r_m ¶
    Source

    inst_lb_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_lbu ¶
    Source

    inst_lbu :: inst_lbu_r_m

    inst_lbu_r_m ¶
    Source

    inst_lbu_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_lbux ¶
    Source

    inst_lbux :: inst_lbux_r_r_r

    inst_lbux_r_r_r ¶
    Source

    inst_lbux_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_ld ¶
    Source

    inst_ld :: inst_ld_r_m

    inst_ld_b ¶
    Source

    inst_ld_b :: inst_ld_b_w_m

    inst_ld_b_w_m ¶
    Source

    inst_ld_b_w_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_ld_d ¶
    Source

    inst_ld_d :: inst_ld_d_w_m

    inst_ld_d_w_m ¶
    Source

    inst_ld_d_w_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_ld_h ¶
    Source

    inst_ld_h :: inst_ld_h_w_m

    inst_ld_h_w_m ¶
    Source

    inst_ld_h_w_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_ld_r_m ¶
    Source

    inst_ld_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_ld_w ¶
    Source

    inst_ld_w :: inst_ld_w_w_m

    inst_ld_w_w_m ¶
    Source

    inst_ld_w_w_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_ldc1 ¶
    Source

    inst_ldc1 :: inst_ldc1_f_m

    inst_ldc1_f_m ¶
    Source

    inst_ldc1_f_m :: proc "contextless" (dst: FPR, mem: Memory) -> Instruction {…}

    inst_ldc2 ¶
    Source

    inst_ldc2 :: inst_ldc2_c2_m

    inst_ldc2_c2_m ¶
    Source

    inst_ldc2_c2_m :: proc "contextless" (dst: GTE_DataReg, mem: Memory) -> Instruction {…}

    inst_ldi_b ¶
    Source

    inst_ldi_b :: inst_ldi_b_w_i5

    inst_ldi_b_w_i5 ¶
    Source

    inst_ldi_b_w_i5 :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

    inst_ldi_d ¶
    Source

    inst_ldi_d :: inst_ldi_d_w_i5

    inst_ldi_d_w_i5 ¶
    Source

    inst_ldi_d_w_i5 :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

    inst_ldi_h ¶
    Source

    inst_ldi_h :: inst_ldi_h_w_i5

    inst_ldi_h_w_i5 ¶
    Source

    inst_ldi_h_w_i5 :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

    inst_ldi_w ¶
    Source

    inst_ldi_w :: inst_ldi_w_w_i5

    inst_ldi_w_w_i5 ¶
    Source

    inst_ldi_w_w_i5 :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

    inst_ldl ¶
    Source

    inst_ldl :: inst_ldl_r_m

    inst_ldl_r_m ¶
    Source

    inst_ldl_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_ldpc ¶
    Source

    inst_ldpc :: inst_ldpc_r_rel

    inst_ldpc_r_rel ¶
    Source

    inst_ldpc_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_ldr ¶
    Source

    inst_ldr :: inst_ldr_r_m

    inst_ldr_r_m ¶
    Source

    inst_ldr_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_ldxc1 ¶
    Source

    inst_ldxc1 :: inst_ldxc1_f_r_r

    inst_ldxc1_f_r_r ¶
    Source

    inst_ldxc1_f_r_r :: proc "contextless" (dst: FPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_lh ¶
    Source

    inst_lh :: inst_lh_r_m

    inst_lh_r_m ¶
    Source

    inst_lh_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_lhu ¶
    Source

    inst_lhu :: inst_lhu_r_m

    inst_lhu_r_m ¶
    Source

    inst_lhu_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_lhx ¶
    Source

    inst_lhx :: inst_lhx_r_r_r

    inst_lhx_r_r_r ¶
    Source

    inst_lhx_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_ll ¶
    Source

    inst_ll :: inst_ll_r_m

    inst_ll_r_m ¶
    Source

    inst_ll_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_lld ¶
    Source

    inst_lld :: inst_lld_r_m

    inst_lld_r_m ¶
    Source

    inst_lld_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_lq ¶
    Source

    inst_lq :: inst_lq_r_m

    inst_lq_r_m ¶
    Source

    inst_lq_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_lqc2 ¶
    Source

    inst_lqc2 :: inst_lqc2_c2_m

    inst_lqc2_c2_m ¶
    Source

    inst_lqc2_c2_m :: proc "contextless" (dst: GTE_DataReg, mem: Memory) -> Instruction {…}

    inst_lsa ¶
    Source

    inst_lsa :: inst_lsa_r_r_r_i5

    inst_lsa_r_r_r_i5 ¶
    Source

    inst_lsa_r_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, src2: GPR, imm: i64) -> Instruction {…}

    inst_lui ¶
    Source

    inst_lui :: inst_lui_r_u16

    inst_lui_r_u16 ¶
    Source

    inst_lui_r_u16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_lv_q ¶
    Source

    inst_lv_q :: inst_lv_q_vq_m

    inst_lv_q_vq_m ¶
    Source

    inst_lv_q_vq_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_lv_s ¶
    Source

    inst_lv_s :: inst_lv_s_vs_m

    inst_lv_s_vs_m ¶
    Source

    inst_lv_s_vs_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_lvl_q ¶
    Source

    inst_lvl_q :: inst_lvl_q_vq_m

    inst_lvl_q_vq_m ¶
    Source

    inst_lvl_q_vq_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_lvr_q ¶
    Source

    inst_lvr_q :: inst_lvr_q_vq_m

    inst_lvr_q_vq_m ¶
    Source

    inst_lvr_q_vq_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_lw ¶
    Source

    inst_lw :: inst_lw_r_m

    inst_lw_r_m ¶
    Source

    inst_lw_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_lwc1 ¶
    Source

    inst_lwc1 :: inst_lwc1_f_m

    inst_lwc1_f_m ¶
    Source

    inst_lwc1_f_m :: proc "contextless" (dst: FPR, mem: Memory) -> Instruction {…}

    inst_lwc2 ¶
    Source

    inst_lwc2 :: inst_lwc2_c2_m

    inst_lwc2_c2_m ¶
    Source

    inst_lwc2_c2_m :: proc "contextless" (dst: GTE_DataReg, mem: Memory) -> Instruction {…}

    inst_lwl ¶
    Source

    inst_lwl :: inst_lwl_r_m

    inst_lwl_r_m ¶
    Source

    inst_lwl_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_lwpc ¶
    Source

    inst_lwpc :: inst_lwpc_r_rel

    inst_lwpc_r_rel ¶
    Source

    inst_lwpc_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_lwr ¶
    Source

    inst_lwr :: inst_lwr_r_m

    inst_lwr_r_m ¶
    Source

    inst_lwr_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_lwu ¶
    Source

    inst_lwu :: inst_lwu_r_m

    inst_lwu_r_m ¶
    Source

    inst_lwu_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_lwupc ¶
    Source

    inst_lwupc :: inst_lwupc_r_rel

    inst_lwupc_r_rel ¶
    Source

    inst_lwupc_r_rel :: proc "contextless" (dst: GPR, target: u32) -> Instruction {…}

    inst_lwx ¶
    Source

    inst_lwx :: inst_lwx_r_r_r

    inst_lwx_r_r_r ¶
    Source

    inst_lwx_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_lwxc1 ¶
    Source

    inst_lwxc1 :: inst_lwxc1_f_r_r

    inst_lwxc1_f_r_r ¶
    Source

    inst_lwxc1_f_r_r :: proc "contextless" (dst: FPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_madd ¶
    Source

    inst_madd :: inst_madd_r_r

    inst_madd1 ¶
    Source

    inst_madd1 :: inst_madd1_r_r

    inst_madd1_r_r ¶
    Source

    inst_madd1_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_madd_d ¶
    Source

    inst_madd_d :: inst_madd_d_f_f_f_f

    inst_madd_d_f_f_f_f ¶
    Source

    inst_madd_d_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_madd_ee ¶
    Source

    inst_madd_ee :: inst_madd_ee_r_r_r

    inst_madd_ee_r_r_r ¶
    Source

    inst_madd_ee_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_madd_ps ¶
    Source

    inst_madd_ps :: inst_madd_ps_f_f_f_f

    inst_madd_ps_f_f_f_f ¶
    Source

    inst_madd_ps_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_madd_r_r ¶
    Source

    inst_madd_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_madd_s ¶
    Source

    inst_madd_s :: inst_madd_s_f_f_f_f

    inst_madd_s_f_f_f_f ¶
    Source

    inst_madd_s_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_maddu ¶
    Source

    inst_maddu :: inst_maddu_r_r

    inst_maddu1 ¶
    Source

    inst_maddu1 :: inst_maddu1_r_r

    inst_maddu1_r_r ¶
    Source

    inst_maddu1_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_maddu_ee ¶
    Source

    inst_maddu_ee :: inst_maddu_ee_r_r_r

    inst_maddu_ee_r_r_r ¶
    Source

    inst_maddu_ee_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_maddu_r_r ¶
    Source

    inst_maddu_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_maddv_b ¶
    Source

    inst_maddv_b :: inst_maddv_b_w_w_w

    inst_maddv_b_w_w_w ¶
    Source

    inst_maddv_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_maddv_d ¶
    Source

    inst_maddv_d :: inst_maddv_d_w_w_w

    inst_maddv_d_w_w_w ¶
    Source

    inst_maddv_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_maddv_h ¶
    Source

    inst_maddv_h :: inst_maddv_h_w_w_w

    inst_maddv_h_w_w_w ¶
    Source

    inst_maddv_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_maddv_w ¶
    Source

    inst_maddv_w :: inst_maddv_w_w_w_w

    inst_maddv_w_w_w_w ¶
    Source

    inst_maddv_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_maq_s_w_phl ¶
    Source

    inst_maq_s_w_phl :: inst_maq_s_w_phl_i5_r_r

    inst_maq_s_w_phl_i5_r_r ¶
    Source

    inst_maq_s_w_phl_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_maq_s_w_phr ¶
    Source

    inst_maq_s_w_phr :: inst_maq_s_w_phr_i5_r_r

    inst_maq_s_w_phr_i5_r_r ¶
    Source

    inst_maq_s_w_phr_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_maq_sa_w_phl ¶
    Source

    inst_maq_sa_w_phl :: inst_maq_sa_w_phl_i5_r_r

    inst_maq_sa_w_phl_i5_r_r ¶
    Source

    inst_maq_sa_w_phl_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_maq_sa_w_phr ¶
    Source

    inst_maq_sa_w_phr :: inst_maq_sa_w_phr_i5_r_r

    inst_maq_sa_w_phr_i5_r_r ¶
    Source

    inst_maq_sa_w_phr_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_max_s_b ¶
    Source

    inst_max_s_b :: inst_max_s_b_w_w_w

    inst_max_s_b_w_w_w ¶
    Source

    inst_max_s_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_max_s_d ¶
    Source

    inst_max_s_d :: inst_max_s_d_w_w_w

    inst_max_s_d_w_w_w ¶
    Source

    inst_max_s_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_max_s_h ¶
    Source

    inst_max_s_h :: inst_max_s_h_w_w_w

    inst_max_s_h_w_w_w ¶
    Source

    inst_max_s_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_max_s_w ¶
    Source

    inst_max_s_w :: inst_max_s_w_w_w_w

    inst_max_s_w_w_w_w ¶
    Source

    inst_max_s_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_max_u_b ¶
    Source

    inst_max_u_b :: inst_max_u_b_w_w_w

    inst_max_u_b_w_w_w ¶
    Source

    inst_max_u_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_max_u_d ¶
    Source

    inst_max_u_d :: inst_max_u_d_w_w_w

    inst_max_u_d_w_w_w ¶
    Source

    inst_max_u_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_max_u_h ¶
    Source

    inst_max_u_h :: inst_max_u_h_w_w_w

    inst_max_u_h_w_w_w ¶
    Source

    inst_max_u_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_max_u_w ¶
    Source

    inst_max_u_w :: inst_max_u_w_w_w_w

    inst_max_u_w_w_w_w ¶
    Source

    inst_max_u_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mfc0 ¶
    Source

    inst_mfc0 :: inst_mfc0_r_c0_sel

    inst_mfc0_r_c0_sel ¶
    Source

    inst_mfc0_r_c0_sel :: proc "contextless" (dst: GPR, src: CP0_Reg, imm: i64) -> Instruction {…}

    inst_mfc1 ¶
    Source

    inst_mfc1 :: inst_mfc1_r_f

    inst_mfc1_r_f ¶
    Source

    inst_mfc1_r_f :: proc "contextless" (dst: GPR, src: FPR) -> Instruction {…}

    inst_mfc2 ¶
    Source

    inst_mfc2 :: inst_mfc2_r_c2

    inst_mfc2_r_c2 ¶
    Source

    inst_mfc2_r_c2 :: proc "contextless" (dst: GPR, src: GTE_DataReg) -> Instruction {…}

    inst_mfhc0 ¶
    Source

    inst_mfhc0 :: inst_mfhc0_r_c0_sel

    inst_mfhc0_r_c0_sel ¶
    Source

    inst_mfhc0_r_c0_sel :: proc "contextless" (dst: GPR, src: CP0_Reg, imm: i64) -> Instruction {…}

    inst_mfhc1 ¶
    Source

    inst_mfhc1 :: inst_mfhc1_r_f

    inst_mfhc1_r_f ¶
    Source

    inst_mfhc1_r_f :: proc "contextless" (dst: GPR, src: FPR) -> Instruction {…}

    inst_mfhi ¶
    Source

    inst_mfhi :: inst_mfhi_r

    inst_mfhi1 ¶
    Source

    inst_mfhi1 :: inst_mfhi1_r

    inst_mfhi1_r ¶
    Source

    inst_mfhi1_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_mfhi_r ¶
    Source

    inst_mfhi_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_mflo ¶
    Source

    inst_mflo :: inst_mflo_r

    inst_mflo1 ¶
    Source

    inst_mflo1 :: inst_mflo1_r

    inst_mflo1_r ¶
    Source

    inst_mflo1_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_mflo_r ¶
    Source

    inst_mflo_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_mfsa ¶
    Source

    inst_mfsa :: inst_mfsa_r

    inst_mfsa_r ¶
    Source

    inst_mfsa_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_mfv ¶
    Source

    inst_mfv :: inst_mfv_r_vs

    inst_mfv_r_vs ¶
    Source

    inst_mfv_r_vs :: proc "contextless" (dst: GPR, src: Register) -> Instruction {…}

    inst_mfvc ¶
    Source

    inst_mfvc :: inst_mfvc_r_i5

    inst_mfvc_r_i5 ¶
    Source

    inst_mfvc_r_i5 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_min_s_b ¶
    Source

    inst_min_s_b :: inst_min_s_b_w_w_w

    inst_min_s_b_w_w_w ¶
    Source

    inst_min_s_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_min_s_d ¶
    Source

    inst_min_s_d :: inst_min_s_d_w_w_w

    inst_min_s_d_w_w_w ¶
    Source

    inst_min_s_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_min_s_h ¶
    Source

    inst_min_s_h :: inst_min_s_h_w_w_w

    inst_min_s_h_w_w_w ¶
    Source

    inst_min_s_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_min_s_w ¶
    Source

    inst_min_s_w :: inst_min_s_w_w_w_w

    inst_min_s_w_w_w_w ¶
    Source

    inst_min_s_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_min_u_b ¶
    Source

    inst_min_u_b :: inst_min_u_b_w_w_w

    inst_min_u_b_w_w_w ¶
    Source

    inst_min_u_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_min_u_d ¶
    Source

    inst_min_u_d :: inst_min_u_d_w_w_w

    inst_min_u_d_w_w_w ¶
    Source

    inst_min_u_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_min_u_h ¶
    Source

    inst_min_u_h :: inst_min_u_h_w_w_w

    inst_min_u_h_w_w_w ¶
    Source

    inst_min_u_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_min_u_w ¶
    Source

    inst_min_u_w :: inst_min_u_w_w_w_w

    inst_min_u_w_w_w_w ¶
    Source

    inst_min_u_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mod ¶
    Source

    inst_mod :: inst_mod_r_r_r

    inst_mod_r_r_r ¶
    Source

    inst_mod_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_mod_s_b ¶
    Source

    inst_mod_s_b :: inst_mod_s_b_w_w_w

    inst_mod_s_b_w_w_w ¶
    Source

    inst_mod_s_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mod_s_d ¶
    Source

    inst_mod_s_d :: inst_mod_s_d_w_w_w

    inst_mod_s_d_w_w_w ¶
    Source

    inst_mod_s_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mod_s_h ¶
    Source

    inst_mod_s_h :: inst_mod_s_h_w_w_w

    inst_mod_s_h_w_w_w ¶
    Source

    inst_mod_s_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mod_s_w ¶
    Source

    inst_mod_s_w :: inst_mod_s_w_w_w_w

    inst_mod_s_w_w_w_w ¶
    Source

    inst_mod_s_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mod_u_b ¶
    Source

    inst_mod_u_b :: inst_mod_u_b_w_w_w

    inst_mod_u_b_w_w_w ¶
    Source

    inst_mod_u_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mod_u_d ¶
    Source

    inst_mod_u_d :: inst_mod_u_d_w_w_w

    inst_mod_u_d_w_w_w ¶
    Source

    inst_mod_u_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mod_u_h ¶
    Source

    inst_mod_u_h :: inst_mod_u_h_w_w_w

    inst_mod_u_h_w_w_w ¶
    Source

    inst_mod_u_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mod_u_w ¶
    Source

    inst_mod_u_w :: inst_mod_u_w_w_w_w

    inst_mod_u_w_w_w_w ¶
    Source

    inst_mod_u_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_modu ¶
    Source

    inst_modu :: inst_modu_r_r_r

    inst_modu_r_r_r ¶
    Source

    inst_modu_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_mov_d ¶
    Source

    inst_mov_d :: inst_mov_d_f_f

    inst_mov_d_f_f ¶
    Source

    inst_mov_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_mov_ps ¶
    Source

    inst_mov_ps :: inst_mov_ps_f_f

    inst_mov_ps_f_f ¶
    Source

    inst_mov_ps_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_mov_s ¶
    Source

    inst_mov_s :: inst_mov_s_f_f

    inst_mov_s_f_f ¶
    Source

    inst_mov_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_movf ¶
    Source

    inst_movf :: inst_movf_r_r_cc

    inst_movf_d ¶
    Source

    inst_movf_d :: inst_movf_d_f_f_cc

    inst_movf_d_f_f_cc ¶
    Source

    inst_movf_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_movf_ps ¶
    Source

    inst_movf_ps :: inst_movf_ps_f_f_cc

    inst_movf_ps_f_f_cc ¶
    Source

    inst_movf_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_movf_r_r_cc ¶
    Source

    inst_movf_r_r_cc :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_movf_s ¶
    Source

    inst_movf_s :: inst_movf_s_f_f_cc

    inst_movf_s_f_f_cc ¶
    Source

    inst_movf_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_movn ¶
    Source

    inst_movn :: inst_movn_r_r_r

    inst_movn_d ¶
    Source

    inst_movn_d :: inst_movn_d_f_f_r

    inst_movn_d_f_f_r ¶
    Source

    inst_movn_d_f_f_r :: proc "contextless" (dst: FPR, src: FPR, src2: GPR) -> Instruction {…}

    inst_movn_ps ¶
    Source

    inst_movn_ps :: inst_movn_ps_f_f_r

    inst_movn_ps_f_f_r ¶
    Source

    inst_movn_ps_f_f_r :: proc "contextless" (dst: FPR, src: FPR, src2: GPR) -> Instruction {…}

    inst_movn_r_r_r ¶
    Source

    inst_movn_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_movn_s ¶
    Source

    inst_movn_s :: inst_movn_s_f_f_r

    inst_movn_s_f_f_r ¶
    Source

    inst_movn_s_f_f_r :: proc "contextless" (dst: FPR, src: FPR, src2: GPR) -> Instruction {…}

    inst_movt ¶
    Source

    inst_movt :: inst_movt_r_r_cc

    inst_movt_d ¶
    Source

    inst_movt_d :: inst_movt_d_f_f_cc

    inst_movt_d_f_f_cc ¶
    Source

    inst_movt_d_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_movt_ps ¶
    Source

    inst_movt_ps :: inst_movt_ps_f_f_cc

    inst_movt_ps_f_f_cc ¶
    Source

    inst_movt_ps_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_movt_r_r_cc ¶
    Source

    inst_movt_r_r_cc :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_movt_s ¶
    Source

    inst_movt_s :: inst_movt_s_f_f_cc

    inst_movt_s_f_f_cc ¶
    Source

    inst_movt_s_f_f_cc :: proc "contextless" (dst: FPR, src: FPR, imm: i64) -> Instruction {…}

    inst_movz ¶
    Source

    inst_movz :: inst_movz_r_r_r

    inst_movz_d ¶
    Source

    inst_movz_d :: inst_movz_d_f_f_r

    inst_movz_d_f_f_r ¶
    Source

    inst_movz_d_f_f_r :: proc "contextless" (dst: FPR, src: FPR, src2: GPR) -> Instruction {…}

    inst_movz_ps ¶
    Source

    inst_movz_ps :: inst_movz_ps_f_f_r

    inst_movz_ps_f_f_r ¶
    Source

    inst_movz_ps_f_f_r :: proc "contextless" (dst: FPR, src: FPR, src2: GPR) -> Instruction {…}

    inst_movz_r_r_r ¶
    Source

    inst_movz_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_movz_s ¶
    Source

    inst_movz_s :: inst_movz_s_f_f_r

    inst_movz_s_f_f_r ¶
    Source

    inst_movz_s_f_f_r :: proc "contextless" (dst: FPR, src: FPR, src2: GPR) -> Instruction {…}

    inst_msub ¶
    Source

    inst_msub :: inst_msub_r_r

    inst_msub1 ¶
    Source

    inst_msub1 :: inst_msub1_r_r

    inst_msub1_r_r ¶
    Source

    inst_msub1_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_msub_d ¶
    Source

    inst_msub_d :: inst_msub_d_f_f_f_f

    inst_msub_d_f_f_f_f ¶
    Source

    inst_msub_d_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_msub_ee ¶
    Source

    inst_msub_ee :: inst_msub_ee_r_r_r

    inst_msub_ee_r_r_r ¶
    Source

    inst_msub_ee_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_msub_ps ¶
    Source

    inst_msub_ps :: inst_msub_ps_f_f_f_f

    inst_msub_ps_f_f_f_f ¶
    Source

    inst_msub_ps_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_msub_r_r ¶
    Source

    inst_msub_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_msub_s ¶
    Source

    inst_msub_s :: inst_msub_s_f_f_f_f

    inst_msub_s_f_f_f_f ¶
    Source

    inst_msub_s_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_msubu ¶
    Source

    inst_msubu :: inst_msubu_r_r

    inst_msubu1 ¶
    Source

    inst_msubu1 :: inst_msubu1_r_r

    inst_msubu1_r_r ¶
    Source

    inst_msubu1_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_msubu_ee ¶
    Source

    inst_msubu_ee :: inst_msubu_ee_r_r_r

    inst_msubu_ee_r_r_r ¶
    Source

    inst_msubu_ee_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_msubu_r_r ¶
    Source

    inst_msubu_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_msubv_b ¶
    Source

    inst_msubv_b :: inst_msubv_b_w_w_w

    inst_msubv_b_w_w_w ¶
    Source

    inst_msubv_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_msubv_d ¶
    Source

    inst_msubv_d :: inst_msubv_d_w_w_w

    inst_msubv_d_w_w_w ¶
    Source

    inst_msubv_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_msubv_h ¶
    Source

    inst_msubv_h :: inst_msubv_h_w_w_w

    inst_msubv_h_w_w_w ¶
    Source

    inst_msubv_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_msubv_w ¶
    Source

    inst_msubv_w :: inst_msubv_w_w_w_w

    inst_msubv_w_w_w_w ¶
    Source

    inst_msubv_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mtc0 ¶
    Source

    inst_mtc0 :: inst_mtc0_r_c0_sel

    inst_mtc0_r_c0_sel ¶
    Source

    inst_mtc0_r_c0_sel :: proc "contextless" (dst: GPR, src: CP0_Reg, imm: i64) -> Instruction {…}

    inst_mtc1 ¶
    Source

    inst_mtc1 :: inst_mtc1_r_f

    inst_mtc1_r_f ¶
    Source

    inst_mtc1_r_f :: proc "contextless" (dst: GPR, src: FPR) -> Instruction {…}

    inst_mtc2 ¶
    Source

    inst_mtc2 :: inst_mtc2_r_c2

    inst_mtc2_r_c2 ¶
    Source

    inst_mtc2_r_c2 :: proc "contextless" (dst: GPR, src: GTE_DataReg) -> Instruction {…}

    inst_mthc0 ¶
    Source

    inst_mthc0 :: inst_mthc0_r_c0_sel

    inst_mthc0_r_c0_sel ¶
    Source

    inst_mthc0_r_c0_sel :: proc "contextless" (dst: GPR, src: CP0_Reg, imm: i64) -> Instruction {…}

    inst_mthc1 ¶
    Source

    inst_mthc1 :: inst_mthc1_r_f

    inst_mthc1_r_f ¶
    Source

    inst_mthc1_r_f :: proc "contextless" (dst: GPR, src: FPR) -> Instruction {…}

    inst_mthi ¶
    Source

    inst_mthi :: inst_mthi_r

    inst_mthi1 ¶
    Source

    inst_mthi1 :: inst_mthi1_r

    inst_mthi1_r ¶
    Source

    inst_mthi1_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_mthi_r ¶
    Source

    inst_mthi_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_mthlip ¶
    Source

    inst_mthlip :: inst_mthlip_r_i5

    inst_mthlip_r_i5 ¶
    Source

    inst_mthlip_r_i5 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_mtlo ¶
    Source

    inst_mtlo :: inst_mtlo_r

    inst_mtlo1 ¶
    Source

    inst_mtlo1 :: inst_mtlo1_r

    inst_mtlo1_r ¶
    Source

    inst_mtlo1_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_mtlo_r ¶
    Source

    inst_mtlo_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_mtsa ¶
    Source

    inst_mtsa :: inst_mtsa_r

    inst_mtsa_r ¶
    Source

    inst_mtsa_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_mtsab ¶
    Source

    inst_mtsab :: inst_mtsab_r_i16

    inst_mtsab_r_i16 ¶
    Source

    inst_mtsab_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_mtsah ¶
    Source

    inst_mtsah :: inst_mtsah_r_i16

    inst_mtsah_r_i16 ¶
    Source

    inst_mtsah_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_mtv ¶
    Source

    inst_mtv :: inst_mtv_r_vs

    inst_mtv_r_vs ¶
    Source

    inst_mtv_r_vs :: proc "contextless" (dst: GPR, src: Register) -> Instruction {…}

    inst_mtvc ¶
    Source

    inst_mtvc :: inst_mtvc_r_i5

    inst_mtvc_r_i5 ¶
    Source

    inst_mtvc_r_i5 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_muh ¶
    Source

    inst_muh :: inst_muh_r_r_r

    inst_muh_r_r_r ¶
    Source

    inst_muh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_muhu ¶
    Source

    inst_muhu :: inst_muhu_r_r_r

    inst_muhu_r_r_r ¶
    Source

    inst_muhu_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_mul ¶
    Source

    inst_mul :: inst_mul_r_r_r

    inst_mul_d ¶
    Source

    inst_mul_d :: inst_mul_d_f_f_f

    inst_mul_d_f_f_f ¶
    Source

    inst_mul_d_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_mul_ps ¶
    Source

    inst_mul_ps :: inst_mul_ps_f_f_f

    inst_mul_ps_f_f_f ¶
    Source

    inst_mul_ps_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_mul_r_r_r ¶
    Source

    inst_mul_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_mul_s ¶
    Source

    inst_mul_s :: inst_mul_s_f_f_f

    inst_mul_s_f_f_f ¶
    Source

    inst_mul_s_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_muleq_s_w_phl ¶
    Source

    inst_muleq_s_w_phl :: inst_muleq_s_w_phl_r_r_r

    inst_muleq_s_w_phl_r_r_r ¶
    Source

    inst_muleq_s_w_phl_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_muleq_s_w_phr ¶
    Source

    inst_muleq_s_w_phr :: inst_muleq_s_w_phr_r_r_r

    inst_muleq_s_w_phr_r_r_r ¶
    Source

    inst_muleq_s_w_phr_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_muleu_s_ph_qbl ¶
    Source

    inst_muleu_s_ph_qbl :: inst_muleu_s_ph_qbl_r_r_r

    inst_muleu_s_ph_qbl_r_r_r ¶
    Source

    inst_muleu_s_ph_qbl_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_muleu_s_ph_qbr ¶
    Source

    inst_muleu_s_ph_qbr :: inst_muleu_s_ph_qbr_r_r_r

    inst_muleu_s_ph_qbr_r_r_r ¶
    Source

    inst_muleu_s_ph_qbr_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_mulq_rs_ph ¶
    Source

    inst_mulq_rs_ph :: inst_mulq_rs_ph_r_r_r

    inst_mulq_rs_ph_r_r_r ¶
    Source

    inst_mulq_rs_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_mulq_s_ph ¶
    Source

    inst_mulq_s_ph :: inst_mulq_s_ph_r_r_r

    inst_mulq_s_ph_r_r_r ¶
    Source

    inst_mulq_s_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_mulsaq_s_w_ph ¶
    Source

    inst_mulsaq_s_w_ph :: inst_mulsaq_s_w_ph_i5_r_r

    inst_mulsaq_s_w_ph_i5_r_r ¶
    Source

    inst_mulsaq_s_w_ph_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_mult ¶
    Source

    inst_mult :: inst_mult_r_r

    inst_mult1 ¶
    Source

    inst_mult1 :: inst_mult1_r_r

    inst_mult1_r_r ¶
    Source

    inst_mult1_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_mult_r_r ¶
    Source

    inst_mult_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_multu ¶
    Source

    inst_multu :: inst_multu_r_r

    inst_multu1 ¶
    Source

    inst_multu1 :: inst_multu1_r_r

    inst_multu1_r_r ¶
    Source

    inst_multu1_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_multu_r_r ¶
    Source

    inst_multu_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_mulu ¶
    Source

    inst_mulu :: inst_mulu_r_r_r

    inst_mulu_r_r_r ¶
    Source

    inst_mulu_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_mulv_b ¶
    Source

    inst_mulv_b :: inst_mulv_b_w_w_w

    inst_mulv_b_w_w_w ¶
    Source

    inst_mulv_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mulv_d ¶
    Source

    inst_mulv_d :: inst_mulv_d_w_w_w

    inst_mulv_d_w_w_w ¶
    Source

    inst_mulv_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mulv_h ¶
    Source

    inst_mulv_h :: inst_mulv_h_w_w_w

    inst_mulv_h_w_w_w ¶
    Source

    inst_mulv_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mulv_w ¶
    Source

    inst_mulv_w :: inst_mulv_w_w_w_w

    inst_mulv_w_w_w_w ¶
    Source

    inst_mulv_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_mvmva ¶
    Source

    inst_mvmva :: inst_mvmva_none

    inst_mvmva_none ¶
    Source

    inst_mvmva_none :: proc "contextless" () -> Instruction {…}

    inst_nccs ¶
    Source

    inst_nccs :: inst_nccs_none

    inst_nccs_none ¶
    Source

    inst_nccs_none :: proc "contextless" () -> Instruction {…}

    inst_ncct ¶
    Source

    inst_ncct :: inst_ncct_none

    inst_ncct_none ¶
    Source

    inst_ncct_none :: proc "contextless" () -> Instruction {…}

    inst_ncds ¶
    Source

    inst_ncds :: inst_ncds_none

    inst_ncds_none ¶
    Source

    inst_ncds_none :: proc "contextless" () -> Instruction {…}

    inst_ncdt ¶
    Source

    inst_ncdt :: inst_ncdt_none

    inst_ncdt_none ¶
    Source

    inst_ncdt_none :: proc "contextless" () -> Instruction {…}

    inst_nclip ¶
    Source

    inst_nclip :: inst_nclip_none

    inst_nclip_none ¶
    Source

    inst_nclip_none :: proc "contextless" () -> Instruction {…}

    inst_ncs ¶
    Source

    inst_ncs :: inst_ncs_none

    inst_ncs_none ¶
    Source

    inst_ncs_none :: proc "contextless" () -> Instruction {…}

    inst_nct ¶
    Source

    inst_nct :: inst_nct_none

    inst_nct_none ¶
    Source

    inst_nct_none :: proc "contextless" () -> Instruction {…}

    inst_neg_d ¶
    Source

    inst_neg_d :: inst_neg_d_f_f

    inst_neg_d_f_f ¶
    Source

    inst_neg_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_neg_ps ¶
    Source

    inst_neg_ps :: inst_neg_ps_f_f

    inst_neg_ps_f_f ¶
    Source

    inst_neg_ps_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_neg_s ¶
    Source

    inst_neg_s :: inst_neg_s_f_f

    inst_neg_s_f_f ¶
    Source

    inst_neg_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_nloc_b ¶
    Source

    inst_nloc_b :: inst_nloc_b_w_w

    inst_nloc_b_w_w ¶
    Source

    inst_nloc_b_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_nloc_d ¶
    Source

    inst_nloc_d :: inst_nloc_d_w_w

    inst_nloc_d_w_w ¶
    Source

    inst_nloc_d_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_nloc_h ¶
    Source

    inst_nloc_h :: inst_nloc_h_w_w

    inst_nloc_h_w_w ¶
    Source

    inst_nloc_h_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_nloc_w ¶
    Source

    inst_nloc_w :: inst_nloc_w_w_w

    inst_nloc_w_w_w ¶
    Source

    inst_nloc_w_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_nlzc_b ¶
    Source

    inst_nlzc_b :: inst_nlzc_b_w_w

    inst_nlzc_b_w_w ¶
    Source

    inst_nlzc_b_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_nlzc_d ¶
    Source

    inst_nlzc_d :: inst_nlzc_d_w_w

    inst_nlzc_d_w_w ¶
    Source

    inst_nlzc_d_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_nlzc_h ¶
    Source

    inst_nlzc_h :: inst_nlzc_h_w_w

    inst_nlzc_h_w_w ¶
    Source

    inst_nlzc_h_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_nlzc_w ¶
    Source

    inst_nlzc_w :: inst_nlzc_w_w_w

    inst_nlzc_w_w_w ¶
    Source

    inst_nlzc_w_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_nmadd_d ¶
    Source

    inst_nmadd_d :: inst_nmadd_d_f_f_f_f

    inst_nmadd_d_f_f_f_f ¶
    Source

    inst_nmadd_d_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_nmadd_ps ¶
    Source

    inst_nmadd_ps :: inst_nmadd_ps_f_f_f_f

    inst_nmadd_ps_f_f_f_f ¶
    Source

    inst_nmadd_ps_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_nmadd_s ¶
    Source

    inst_nmadd_s :: inst_nmadd_s_f_f_f_f

    inst_nmadd_s_f_f_f_f ¶
    Source

    inst_nmadd_s_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_nmsub_d ¶
    Source

    inst_nmsub_d :: inst_nmsub_d_f_f_f_f

    inst_nmsub_d_f_f_f_f ¶
    Source

    inst_nmsub_d_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_nmsub_ps ¶
    Source

    inst_nmsub_ps :: inst_nmsub_ps_f_f_f_f

    inst_nmsub_ps_f_f_f_f ¶
    Source

    inst_nmsub_ps_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_nmsub_s ¶
    Source

    inst_nmsub_s :: inst_nmsub_s_f_f_f_f

    inst_nmsub_s_f_f_f_f ¶
    Source

    inst_nmsub_s_f_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR, src3: FPR) -> Instruction {…}

    inst_none ¶
    Source

    inst_none :: proc "contextless" (m: Mnemonic) -> Instruction {…}

    inst_nop ¶
    Source

    inst_nop :: inst_nop_none

    inst_nop_none ¶
    Source

    inst_nop_none :: proc "contextless" () -> Instruction {…}

    inst_nor ¶
    Source

    inst_nor :: inst_nor_r_r_r

    inst_nor_r_r_r ¶
    Source

    inst_nor_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_nor_v ¶
    Source

    inst_nor_v :: inst_nor_v_w_w_w

    inst_nor_v_w_w_w ¶
    Source

    inst_nor_v_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_nori_b ¶
    Source

    inst_nori_b :: inst_nori_b_w_w_i5

    inst_nori_b_w_w_i5 ¶
    Source

    inst_nori_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_op_gte ¶
    Source

    inst_op_gte :: inst_op_gte_none

    inst_op_gte_none ¶
    Source

    inst_op_gte_none :: proc "contextless" () -> Instruction {…}

    inst_or ¶
    Source

    inst_or :: inst_or_r_r_r

    inst_or_r_r_r ¶
    Source

    inst_or_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_or_v ¶
    Source

    inst_or_v :: inst_or_v_w_w_w

    inst_or_v_w_w_w ¶
    Source

    inst_or_v_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_ori ¶
    Source

    inst_ori :: inst_ori_r_r_u16

    inst_ori_b ¶
    Source

    inst_ori_b :: inst_ori_b_w_w_i5

    inst_ori_b_w_w_i5 ¶
    Source

    inst_ori_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_ori_r_r_u16 ¶
    Source

    inst_ori_r_r_u16 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_pabsh ¶
    Source

    inst_pabsh :: inst_pabsh_r_r

    inst_pabsh_r_r ¶
    Source

    inst_pabsh_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_pabsw ¶
    Source

    inst_pabsw :: inst_pabsw_r_r

    inst_pabsw_r_r ¶
    Source

    inst_pabsw_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_paddb ¶
    Source

    inst_paddb :: inst_paddb_r_r_r

    inst_paddb_r_r_r ¶
    Source

    inst_paddb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_paddh ¶
    Source

    inst_paddh :: inst_paddh_r_r_r

    inst_paddh_r_r_r ¶
    Source

    inst_paddh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_paddsb ¶
    Source

    inst_paddsb :: inst_paddsb_r_r_r

    inst_paddsb_r_r_r ¶
    Source

    inst_paddsb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_paddsh ¶
    Source

    inst_paddsh :: inst_paddsh_r_r_r

    inst_paddsh_r_r_r ¶
    Source

    inst_paddsh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_paddsw ¶
    Source

    inst_paddsw :: inst_paddsw_r_r_r

    inst_paddsw_r_r_r ¶
    Source

    inst_paddsw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_paddub ¶
    Source

    inst_paddub :: inst_paddub_r_r_r

    inst_paddub_r_r_r ¶
    Source

    inst_paddub_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_padduh ¶
    Source

    inst_padduh :: inst_padduh_r_r_r

    inst_padduh_r_r_r ¶
    Source

    inst_padduh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_padduw ¶
    Source

    inst_padduw :: inst_padduw_r_r_r

    inst_padduw_r_r_r ¶
    Source

    inst_padduw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_paddw ¶
    Source

    inst_paddw :: inst_paddw_r_r_r

    inst_paddw_r_r_r ¶
    Source

    inst_paddw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pand ¶
    Source

    inst_pand :: inst_pand_r_r_r

    inst_pand_r_r_r ¶
    Source

    inst_pand_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pause ¶
    Source

    inst_pause :: inst_pause_none

    inst_pause_none ¶
    Source

    inst_pause_none :: proc "contextless" () -> Instruction {…}

    inst_pceqb ¶
    Source

    inst_pceqb :: inst_pceqb_r_r_r

    inst_pceqb_r_r_r ¶
    Source

    inst_pceqb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pceqh ¶
    Source

    inst_pceqh :: inst_pceqh_r_r_r

    inst_pceqh_r_r_r ¶
    Source

    inst_pceqh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pceqw ¶
    Source

    inst_pceqw :: inst_pceqw_r_r_r

    inst_pceqw_r_r_r ¶
    Source

    inst_pceqw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pcgtb ¶
    Source

    inst_pcgtb :: inst_pcgtb_r_r_r

    inst_pcgtb_r_r_r ¶
    Source

    inst_pcgtb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pcgth ¶
    Source

    inst_pcgth :: inst_pcgth_r_r_r

    inst_pcgth_r_r_r ¶
    Source

    inst_pcgth_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pcgtw ¶
    Source

    inst_pcgtw :: inst_pcgtw_r_r_r

    inst_pcgtw_r_r_r ¶
    Source

    inst_pcgtw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pcnt_b ¶
    Source

    inst_pcnt_b :: inst_pcnt_b_w_w

    inst_pcnt_b_w_w ¶
    Source

    inst_pcnt_b_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_pcnt_d ¶
    Source

    inst_pcnt_d :: inst_pcnt_d_w_w

    inst_pcnt_d_w_w ¶
    Source

    inst_pcnt_d_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_pcnt_h ¶
    Source

    inst_pcnt_h :: inst_pcnt_h_w_w

    inst_pcnt_h_w_w ¶
    Source

    inst_pcnt_h_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_pcnt_w ¶
    Source

    inst_pcnt_w :: inst_pcnt_w_w_w

    inst_pcnt_w_w_w ¶
    Source

    inst_pcnt_w_w_w :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_pcpyh ¶
    Source

    inst_pcpyh :: inst_pcpyh_r_r

    inst_pcpyh_r_r ¶
    Source

    inst_pcpyh_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_pcpyld ¶
    Source

    inst_pcpyld :: inst_pcpyld_r_r_r

    inst_pcpyld_r_r_r ¶
    Source

    inst_pcpyld_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pcpyud ¶
    Source

    inst_pcpyud :: inst_pcpyud_r_r_r

    inst_pcpyud_r_r_r ¶
    Source

    inst_pcpyud_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pdivbw ¶
    Source

    inst_pdivbw :: inst_pdivbw_r_r

    inst_pdivbw_r_r ¶
    Source

    inst_pdivbw_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_pdivuw ¶
    Source

    inst_pdivuw :: inst_pdivuw_r_r

    inst_pdivuw_r_r ¶
    Source

    inst_pdivuw_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_pdivw ¶
    Source

    inst_pdivw :: inst_pdivw_r_r

    inst_pdivw_r_r ¶
    Source

    inst_pdivw_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_pexch ¶
    Source

    inst_pexch :: inst_pexch_r_r

    inst_pexch_r_r ¶
    Source

    inst_pexch_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_pexcw ¶
    Source

    inst_pexcw :: inst_pexcw_r_r

    inst_pexcw_r_r ¶
    Source

    inst_pexcw_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_pexeh ¶
    Source

    inst_pexeh :: inst_pexeh_r_r

    inst_pexeh_r_r ¶
    Source

    inst_pexeh_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_pexew ¶
    Source

    inst_pexew :: inst_pexew_r_r

    inst_pexew_r_r ¶
    Source

    inst_pexew_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_pext5 ¶
    Source

    inst_pext5 :: inst_pext5_r_r_r

    inst_pext5_r_r_r ¶
    Source

    inst_pext5_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pextlb ¶
    Source

    inst_pextlb :: inst_pextlb_r_r_r

    inst_pextlb_r_r_r ¶
    Source

    inst_pextlb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pextlh ¶
    Source

    inst_pextlh :: inst_pextlh_r_r_r

    inst_pextlh_r_r_r ¶
    Source

    inst_pextlh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pextlw ¶
    Source

    inst_pextlw :: inst_pextlw_r_r_r

    inst_pextlw_r_r_r ¶
    Source

    inst_pextlw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pextub ¶
    Source

    inst_pextub :: inst_pextub_r_r_r

    inst_pextub_r_r_r ¶
    Source

    inst_pextub_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pextuh ¶
    Source

    inst_pextuh :: inst_pextuh_r_r_r

    inst_pextuh_r_r_r ¶
    Source

    inst_pextuh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pextuw ¶
    Source

    inst_pextuw :: inst_pextuw_r_r_r

    inst_pextuw_r_r_r ¶
    Source

    inst_pextuw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_phmadh ¶
    Source

    inst_phmadh :: inst_phmadh_r_r_r

    inst_phmadh_r_r_r ¶
    Source

    inst_phmadh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_phmsbh ¶
    Source

    inst_phmsbh :: inst_phmsbh_r_r_r

    inst_phmsbh_r_r_r ¶
    Source

    inst_phmsbh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pick_ph ¶
    Source

    inst_pick_ph :: inst_pick_ph_r_r_r

    inst_pick_ph_r_r_r ¶
    Source

    inst_pick_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pick_qb ¶
    Source

    inst_pick_qb :: inst_pick_qb_r_r_r

    inst_pick_qb_r_r_r ¶
    Source

    inst_pick_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pinth ¶
    Source

    inst_pinth :: inst_pinth_r_r_r

    inst_pinth_r_r_r ¶
    Source

    inst_pinth_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pintoh ¶
    Source

    inst_pintoh :: inst_pintoh_r_r_r

    inst_pintoh_r_r_r ¶
    Source

    inst_pintoh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pll_ps ¶
    Source

    inst_pll_ps :: inst_pll_ps_f_f_f

    inst_pll_ps_f_f_f ¶
    Source

    inst_pll_ps_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_plu_ps ¶
    Source

    inst_plu_ps :: inst_plu_ps_f_f_f

    inst_plu_ps_f_f_f ¶
    Source

    inst_plu_ps_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_plzcw ¶
    Source

    inst_plzcw :: inst_plzcw_r_r

    inst_plzcw_r_r ¶
    Source

    inst_plzcw_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_pmaddh ¶
    Source

    inst_pmaddh :: inst_pmaddh_r_r_r

    inst_pmaddh_r_r_r ¶
    Source

    inst_pmaddh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pmadduw ¶
    Source

    inst_pmadduw :: inst_pmadduw_r_r_r

    inst_pmadduw_r_r_r ¶
    Source

    inst_pmadduw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pmaddw ¶
    Source

    inst_pmaddw :: inst_pmaddw_r_r_r

    inst_pmaddw_r_r_r ¶
    Source

    inst_pmaddw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pmaxh ¶
    Source

    inst_pmaxh :: inst_pmaxh_r_r_r

    inst_pmaxh_r_r_r ¶
    Source

    inst_pmaxh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pmaxw ¶
    Source

    inst_pmaxw :: inst_pmaxw_r_r_r

    inst_pmaxw_r_r_r ¶
    Source

    inst_pmaxw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pmfhi ¶
    Source

    inst_pmfhi :: inst_pmfhi_r

    inst_pmfhi_r ¶
    Source

    inst_pmfhi_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_pmfhl_lh ¶
    Source

    inst_pmfhl_lh :: inst_pmfhl_lh_r

    inst_pmfhl_lh_r ¶
    Source

    inst_pmfhl_lh_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_pmfhl_lw ¶
    Source

    inst_pmfhl_lw :: inst_pmfhl_lw_r

    inst_pmfhl_lw_r ¶
    Source

    inst_pmfhl_lw_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_pmfhl_sh ¶
    Source

    inst_pmfhl_sh :: inst_pmfhl_sh_r

    inst_pmfhl_sh_r ¶
    Source

    inst_pmfhl_sh_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_pmfhl_slw ¶
    Source

    inst_pmfhl_slw :: inst_pmfhl_slw_r

    inst_pmfhl_slw_r ¶
    Source

    inst_pmfhl_slw_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_pmfhl_uw ¶
    Source

    inst_pmfhl_uw :: inst_pmfhl_uw_r

    inst_pmfhl_uw_r ¶
    Source

    inst_pmfhl_uw_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_pmflo ¶
    Source

    inst_pmflo :: inst_pmflo_r

    inst_pmflo_r ¶
    Source

    inst_pmflo_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_pminh ¶
    Source

    inst_pminh :: inst_pminh_r_r_r

    inst_pminh_r_r_r ¶
    Source

    inst_pminh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pminw ¶
    Source

    inst_pminw :: inst_pminw_r_r_r

    inst_pminw_r_r_r ¶
    Source

    inst_pminw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pmsubh ¶
    Source

    inst_pmsubh :: inst_pmsubh_r_r_r

    inst_pmsubh_r_r_r ¶
    Source

    inst_pmsubh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pmsubw ¶
    Source

    inst_pmsubw :: inst_pmsubw_r_r_r

    inst_pmsubw_r_r_r ¶
    Source

    inst_pmsubw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pmthi ¶
    Source

    inst_pmthi :: inst_pmthi_r

    inst_pmthi_r ¶
    Source

    inst_pmthi_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_pmthl_lw ¶
    Source

    inst_pmthl_lw :: inst_pmthl_lw_r

    inst_pmthl_lw_r ¶
    Source

    inst_pmthl_lw_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_pmtlo ¶
    Source

    inst_pmtlo :: inst_pmtlo_r

    inst_pmtlo_r ¶
    Source

    inst_pmtlo_r :: proc "contextless" (dst: GPR) -> Instruction {…}

    inst_pmulth ¶
    Source

    inst_pmulth :: inst_pmulth_r_r_r

    inst_pmulth_r_r_r ¶
    Source

    inst_pmulth_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pmultuw ¶
    Source

    inst_pmultuw :: inst_pmultuw_r_r_r

    inst_pmultuw_r_r_r ¶
    Source

    inst_pmultuw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pmultw ¶
    Source

    inst_pmultw :: inst_pmultw_r_r_r

    inst_pmultw_r_r_r ¶
    Source

    inst_pmultw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pnor ¶
    Source

    inst_pnor :: inst_pnor_r_r_r

    inst_pnor_r_r_r ¶
    Source

    inst_pnor_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_por ¶
    Source

    inst_por :: inst_por_r_r_r

    inst_por_r_r_r ¶
    Source

    inst_por_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_ppac5 ¶
    Source

    inst_ppac5 :: inst_ppac5_r_r_r

    inst_ppac5_r_r_r ¶
    Source

    inst_ppac5_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_ppacb ¶
    Source

    inst_ppacb :: inst_ppacb_r_r_r

    inst_ppacb_r_r_r ¶
    Source

    inst_ppacb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_ppach ¶
    Source

    inst_ppach :: inst_ppach_r_r_r

    inst_ppach_r_r_r ¶
    Source

    inst_ppach_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_ppacw ¶
    Source

    inst_ppacw :: inst_ppacw_r_r_r

    inst_ppacw_r_r_r ¶
    Source

    inst_ppacw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_preceq_w_phl ¶
    Source

    inst_preceq_w_phl :: inst_preceq_w_phl_r_r

    inst_preceq_w_phl_r_r ¶
    Source

    inst_preceq_w_phl_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_preceq_w_phr ¶
    Source

    inst_preceq_w_phr :: inst_preceq_w_phr_r_r

    inst_preceq_w_phr_r_r ¶
    Source

    inst_preceq_w_phr_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_precequ_ph_qbl ¶
    Source

    inst_precequ_ph_qbl :: inst_precequ_ph_qbl_r_r

    inst_precequ_ph_qbl_r_r ¶
    Source

    inst_precequ_ph_qbl_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_precequ_ph_qbla ¶
    Source

    inst_precequ_ph_qbla :: inst_precequ_ph_qbla_r_r

    inst_precequ_ph_qbla_r_r ¶
    Source

    inst_precequ_ph_qbla_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_precequ_ph_qbr ¶
    Source

    inst_precequ_ph_qbr :: inst_precequ_ph_qbr_r_r

    inst_precequ_ph_qbr_r_r ¶
    Source

    inst_precequ_ph_qbr_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_precequ_ph_qbra ¶
    Source

    inst_precequ_ph_qbra :: inst_precequ_ph_qbra_r_r

    inst_precequ_ph_qbra_r_r ¶
    Source

    inst_precequ_ph_qbra_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_preceu_ph_qbl ¶
    Source

    inst_preceu_ph_qbl :: inst_preceu_ph_qbl_r_r

    inst_preceu_ph_qbl_r_r ¶
    Source

    inst_preceu_ph_qbl_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_preceu_ph_qbla ¶
    Source

    inst_preceu_ph_qbla :: inst_preceu_ph_qbla_r_r

    inst_preceu_ph_qbla_r_r ¶
    Source

    inst_preceu_ph_qbla_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_preceu_ph_qbr ¶
    Source

    inst_preceu_ph_qbr :: inst_preceu_ph_qbr_r_r

    inst_preceu_ph_qbr_r_r ¶
    Source

    inst_preceu_ph_qbr_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_preceu_ph_qbra ¶
    Source

    inst_preceu_ph_qbra :: inst_preceu_ph_qbra_r_r

    inst_preceu_ph_qbra_r_r ¶
    Source

    inst_preceu_ph_qbra_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_precrq_ph_w ¶
    Source

    inst_precrq_ph_w :: inst_precrq_ph_w_r_r_r

    inst_precrq_ph_w_r_r_r ¶
    Source

    inst_precrq_ph_w_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_precrq_qb_ph ¶
    Source

    inst_precrq_qb_ph :: inst_precrq_qb_ph_r_r_r

    inst_precrq_qb_ph_r_r_r ¶
    Source

    inst_precrq_qb_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_precrq_rs_ph_w ¶
    Source

    inst_precrq_rs_ph_w :: inst_precrq_rs_ph_w_r_r_r

    inst_precrq_rs_ph_w_r_r_r ¶
    Source

    inst_precrq_rs_ph_w_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_precrqu_s_qb_ph ¶
    Source

    inst_precrqu_s_qb_ph :: inst_precrqu_s_qb_ph_r_r_r

    inst_precrqu_s_qb_ph_r_r_r ¶
    Source

    inst_precrqu_s_qb_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pref ¶
    Source

    inst_pref :: inst_pref_i5_m

    inst_pref_i5_m ¶
    Source

    inst_pref_i5_m :: proc "contextless" (imm: i64, mem: Memory) -> Instruction {…}

    inst_prefx ¶
    Source

    inst_prefx :: inst_prefx_i5_r_r

    inst_prefx_i5_r_r ¶
    Source

    inst_prefx_i5_r_r :: proc "contextless" (imm: i64, dst: GPR, src: GPR) -> Instruction {…}

    inst_prot3w ¶
    Source

    inst_prot3w :: inst_prot3w_r_r

    inst_prot3w_r_r ¶
    Source

    inst_prot3w_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_psllh ¶
    Source

    inst_psllh :: inst_psllh_r_r_i5

    inst_psllh_r_r_i5 ¶
    Source

    inst_psllh_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_psllvw ¶
    Source

    inst_psllvw :: inst_psllvw_r_r_r

    inst_psllvw_r_r_r ¶
    Source

    inst_psllvw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_psllw ¶
    Source

    inst_psllw :: inst_psllw_r_r_i5

    inst_psllw_r_r_i5 ¶
    Source

    inst_psllw_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_psrah ¶
    Source

    inst_psrah :: inst_psrah_r_r_i5

    inst_psrah_r_r_i5 ¶
    Source

    inst_psrah_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_psravw ¶
    Source

    inst_psravw :: inst_psravw_r_r_r

    inst_psravw_r_r_r ¶
    Source

    inst_psravw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_psraw ¶
    Source

    inst_psraw :: inst_psraw_r_r_i5

    inst_psraw_r_r_i5 ¶
    Source

    inst_psraw_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_psrlh ¶
    Source

    inst_psrlh :: inst_psrlh_r_r_i5

    inst_psrlh_r_r_i5 ¶
    Source

    inst_psrlh_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_psrlvw ¶
    Source

    inst_psrlvw :: inst_psrlvw_r_r_r

    inst_psrlvw_r_r_r ¶
    Source

    inst_psrlvw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_psrlw ¶
    Source

    inst_psrlw :: inst_psrlw_r_r_i5

    inst_psrlw_r_r_i5 ¶
    Source

    inst_psrlw_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_psubb ¶
    Source

    inst_psubb :: inst_psubb_r_r_r

    inst_psubb_r_r_r ¶
    Source

    inst_psubb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_psubh ¶
    Source

    inst_psubh :: inst_psubh_r_r_r

    inst_psubh_r_r_r ¶
    Source

    inst_psubh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_psubsb ¶
    Source

    inst_psubsb :: inst_psubsb_r_r_r

    inst_psubsb_r_r_r ¶
    Source

    inst_psubsb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_psubsh ¶
    Source

    inst_psubsh :: inst_psubsh_r_r_r

    inst_psubsh_r_r_r ¶
    Source

    inst_psubsh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_psubsw ¶
    Source

    inst_psubsw :: inst_psubsw_r_r_r

    inst_psubsw_r_r_r ¶
    Source

    inst_psubsw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_psubub ¶
    Source

    inst_psubub :: inst_psubub_r_r_r

    inst_psubub_r_r_r ¶
    Source

    inst_psubub_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_psubuh ¶
    Source

    inst_psubuh :: inst_psubuh_r_r_r

    inst_psubuh_r_r_r ¶
    Source

    inst_psubuh_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_psubuw ¶
    Source

    inst_psubuw :: inst_psubuw_r_r_r

    inst_psubuw_r_r_r ¶
    Source

    inst_psubuw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_psubw ¶
    Source

    inst_psubw :: inst_psubw_r_r_r

    inst_psubw_r_r_r ¶
    Source

    inst_psubw_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_pul_ps ¶
    Source

    inst_pul_ps :: inst_pul_ps_f_f_f

    inst_pul_ps_f_f_f ¶
    Source

    inst_pul_ps_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_puu_ps ¶
    Source

    inst_puu_ps :: inst_puu_ps_f_f_f

    inst_puu_ps_f_f_f ¶
    Source

    inst_puu_ps_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_pxor ¶
    Source

    inst_pxor :: inst_pxor_r_r_r

    inst_pxor_r_r_r ¶
    Source

    inst_pxor_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_qfsrv ¶
    Source

    inst_qfsrv :: inst_qfsrv_r_r_r

    inst_qfsrv_r_r_r ¶
    Source

    inst_qfsrv_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_r ¶
    Source

    inst_r :: proc "contextless" (m: Mnemonic, a: Register) -> Instruction {…}

    inst_r_i ¶
    Source

    inst_r_i :: proc "contextless" (m: Mnemonic, rt: Register, imm: i64) -> Instruction {…}
     

    Two-operand immediate (e.g. LUI rt, imm; LI variants).

    inst_r_m ¶
    Source

    inst_r_m :: proc "contextless" (m: Mnemonic, r: Register, mm: Memory, size: u8 = 4) -> Instruction {…}
     

    Load/store: reg + memory (LW $rt, disp($rs)).

    inst_r_r ¶
    Source

    inst_r_r :: proc "contextless" (m: Mnemonic, dst, src: Register) -> Instruction {…}

    inst_r_r_i ¶
    Source

    inst_r_r_i :: proc "contextless" (m: Mnemonic, rt, rs: Register, imm: i64) -> Instruction {…}
     

    MIPS three-operand immediate: $rt, $rs, imm (e.g. ADDI rt, rs, imm).

    inst_r_r_r ¶
    Source

    inst_r_r_r :: proc "contextless" (m: Mnemonic, dst, s1, s2: Register) -> Instruction {…}

    inst_rddsp ¶
    Source

    inst_rddsp :: inst_rddsp_r_i5

    inst_rddsp_r_i5 ¶
    Source

    inst_rddsp_r_i5 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_rdhwr ¶
    Source

    inst_rdhwr :: inst_rdhwr_r_r

    inst_rdhwr_r_r ¶
    Source

    inst_rdhwr_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_rdpgpr ¶
    Source

    inst_rdpgpr :: inst_rdpgpr_r_r

    inst_rdpgpr_r_r ¶
    Source

    inst_rdpgpr_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_recip_d ¶
    Source

    inst_recip_d :: inst_recip_d_f_f

    inst_recip_d_f_f ¶
    Source

    inst_recip_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_recip_s ¶
    Source

    inst_recip_s :: inst_recip_s_f_f

    inst_recip_s_f_f ¶
    Source

    inst_recip_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_repl_ph ¶
    Source

    inst_repl_ph :: inst_repl_ph_r_i5

    inst_repl_ph_r_i5 ¶
    Source

    inst_repl_ph_r_i5 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_repl_qb ¶
    Source

    inst_repl_qb :: inst_repl_qb_r_i5

    inst_repl_qb_r_i5 ¶
    Source

    inst_repl_qb_r_i5 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_replv_ph ¶
    Source

    inst_replv_ph :: inst_replv_ph_r_r

    inst_replv_ph_r_r ¶
    Source

    inst_replv_ph_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_replv_qb ¶
    Source

    inst_replv_qb :: inst_replv_qb_r_r

    inst_replv_qb_r_r ¶
    Source

    inst_replv_qb_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_rotr ¶
    Source

    inst_rotr :: inst_rotr_r_r_i5

    inst_rotr_r_r_i5 ¶
    Source

    inst_rotr_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_rotrv ¶
    Source

    inst_rotrv :: inst_rotrv_r_r_r

    inst_rotrv_r_r_r ¶
    Source

    inst_rotrv_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_round_l_d ¶
    Source

    inst_round_l_d :: inst_round_l_d_f_f

    inst_round_l_d_f_f ¶
    Source

    inst_round_l_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_round_l_s ¶
    Source

    inst_round_l_s :: inst_round_l_s_f_f

    inst_round_l_s_f_f ¶
    Source

    inst_round_l_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_round_w_d ¶
    Source

    inst_round_w_d :: inst_round_w_d_f_f

    inst_round_w_d_f_f ¶
    Source

    inst_round_w_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_round_w_s ¶
    Source

    inst_round_w_s :: inst_round_w_s_f_f

    inst_round_w_s_f_f ¶
    Source

    inst_round_w_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_rsqrt_d ¶
    Source

    inst_rsqrt_d :: inst_rsqrt_d_f_f

    inst_rsqrt_d_f_f ¶
    Source

    inst_rsqrt_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_rsqrt_s ¶
    Source

    inst_rsqrt_s :: inst_rsqrt_s_f_f

    inst_rsqrt_s_f_f ¶
    Source

    inst_rsqrt_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_rtps ¶
    Source

    inst_rtps :: inst_rtps_none

    inst_rtps_none ¶
    Source

    inst_rtps_none :: proc "contextless" () -> Instruction {…}

    inst_rtpt ¶
    Source

    inst_rtpt :: inst_rtpt_none

    inst_rtpt_none ¶
    Source

    inst_rtpt_none :: proc "contextless" () -> Instruction {…}

    inst_sb ¶
    Source

    inst_sb :: inst_sb_r_m

    inst_sb_r_m ¶
    Source

    inst_sb_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_sc ¶
    Source

    inst_sc :: inst_sc_r_m

    inst_sc_r_m ¶
    Source

    inst_sc_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_scd ¶
    Source

    inst_scd :: inst_scd_r_m

    inst_scd_r_m ¶
    Source

    inst_scd_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_sd ¶
    Source

    inst_sd :: inst_sd_r_m

    inst_sd_r_m ¶
    Source

    inst_sd_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_sdbbp ¶
    Source

    inst_sdbbp :: inst_sdbbp_i20

    inst_sdbbp_i20 ¶
    Source

    inst_sdbbp_i20 :: proc "contextless" (imm: i64) -> Instruction {…}

    inst_sdc1 ¶
    Source

    inst_sdc1 :: inst_sdc1_f_m

    inst_sdc1_f_m ¶
    Source

    inst_sdc1_f_m :: proc "contextless" (dst: FPR, mem: Memory) -> Instruction {…}

    inst_sdc2 ¶
    Source

    inst_sdc2 :: inst_sdc2_c2_m

    inst_sdc2_c2_m ¶
    Source

    inst_sdc2_c2_m :: proc "contextless" (dst: GTE_DataReg, mem: Memory) -> Instruction {…}

    inst_sdl ¶
    Source

    inst_sdl :: inst_sdl_r_m

    inst_sdl_r_m ¶
    Source

    inst_sdl_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_sdr ¶
    Source

    inst_sdr :: inst_sdr_r_m

    inst_sdr_r_m ¶
    Source

    inst_sdr_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_sdxc1 ¶
    Source

    inst_sdxc1 :: inst_sdxc1_f_r_r

    inst_sdxc1_f_r_r ¶
    Source

    inst_sdxc1_f_r_r :: proc "contextless" (dst: FPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_seb ¶
    Source

    inst_seb :: inst_seb_r_r

    inst_seb_r_r ¶
    Source

    inst_seb_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_seh ¶
    Source

    inst_seh :: inst_seh_r_r

    inst_seh_r_r ¶
    Source

    inst_seh_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_seleqz ¶
    Source

    inst_seleqz :: inst_seleqz_r_r_r

    inst_seleqz_r_r_r ¶
    Source

    inst_seleqz_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_selnez ¶
    Source

    inst_selnez :: inst_selnez_r_r_r

    inst_selnez_r_r_r ¶
    Source

    inst_selnez_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_sh ¶
    Source

    inst_sh :: inst_sh_r_m

    inst_sh_r_m ¶
    Source

    inst_sh_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_shf_b ¶
    Source

    inst_shf_b :: inst_shf_b_w_w_i5

    inst_shf_b_w_w_i5 ¶
    Source

    inst_shf_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_shf_h ¶
    Source

    inst_shf_h :: inst_shf_h_w_w_i5

    inst_shf_h_w_w_i5 ¶
    Source

    inst_shf_h_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_shf_w ¶
    Source

    inst_shf_w :: inst_shf_w_w_w_i5

    inst_shf_w_w_w_i5 ¶
    Source

    inst_shf_w_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_shift ¶
    Source

    inst_shift :: proc "contextless" (m: Mnemonic, rd, rt: Register, shamt: u8) -> Instruction {…}
     

    Shift by immediate: $rd, $rt, shamt (SLL/SRL/SRA).

    inst_shift_v ¶
    Source

    inst_shift_v :: inst_r_r_r

    inst_shilo ¶
    Source

    inst_shilo :: inst_shilo_i5_i5

    inst_shilo_i5_i5 ¶
    Source

    inst_shilo_i5_i5 :: proc "contextless" (imm: i64, imm2: i64) -> Instruction {…}

    inst_shilov ¶
    Source

    inst_shilov :: inst_shilov_i5_r

    inst_shilov_i5_r ¶
    Source

    inst_shilov_i5_r :: proc "contextless" (imm: i64, dst: GPR) -> Instruction {…}

    inst_shll_ph ¶
    Source

    inst_shll_ph :: inst_shll_ph_r_r_i5

    inst_shll_ph_r_r_i5 ¶
    Source

    inst_shll_ph_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_shll_qb ¶
    Source

    inst_shll_qb :: inst_shll_qb_r_r_i5

    inst_shll_qb_r_r_i5 ¶
    Source

    inst_shll_qb_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_shll_s_ph ¶
    Source

    inst_shll_s_ph :: inst_shll_s_ph_r_r_i5

    inst_shll_s_ph_r_r_i5 ¶
    Source

    inst_shll_s_ph_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_shll_s_w ¶
    Source

    inst_shll_s_w :: inst_shll_s_w_r_r_i5

    inst_shll_s_w_r_r_i5 ¶
    Source

    inst_shll_s_w_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_shllv_ph ¶
    Source

    inst_shllv_ph :: inst_shllv_ph_r_r_r

    inst_shllv_ph_r_r_r ¶
    Source

    inst_shllv_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_shllv_qb ¶
    Source

    inst_shllv_qb :: inst_shllv_qb_r_r_r

    inst_shllv_qb_r_r_r ¶
    Source

    inst_shllv_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_shllv_s_ph ¶
    Source

    inst_shllv_s_ph :: inst_shllv_s_ph_r_r_r

    inst_shllv_s_ph_r_r_r ¶
    Source

    inst_shllv_s_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_shllv_s_w ¶
    Source

    inst_shllv_s_w :: inst_shllv_s_w_r_r_r

    inst_shllv_s_w_r_r_r ¶
    Source

    inst_shllv_s_w_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_shra_ph ¶
    Source

    inst_shra_ph :: inst_shra_ph_r_r_i5

    inst_shra_ph_r_r_i5 ¶
    Source

    inst_shra_ph_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_shra_qb ¶
    Source

    inst_shra_qb :: inst_shra_qb_r_r_i5

    inst_shra_qb_r_r_i5 ¶
    Source

    inst_shra_qb_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_shra_r_ph ¶
    Source

    inst_shra_r_ph :: inst_shra_r_ph_r_r_i5

    inst_shra_r_ph_r_r_i5 ¶
    Source

    inst_shra_r_ph_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_shra_r_qb ¶
    Source

    inst_shra_r_qb :: inst_shra_r_qb_r_r_i5

    inst_shra_r_qb_r_r_i5 ¶
    Source

    inst_shra_r_qb_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_shra_r_w ¶
    Source

    inst_shra_r_w :: inst_shra_r_w_r_r_i5

    inst_shra_r_w_r_r_i5 ¶
    Source

    inst_shra_r_w_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_shrav_ph ¶
    Source

    inst_shrav_ph :: inst_shrav_ph_r_r_r

    inst_shrav_ph_r_r_r ¶
    Source

    inst_shrav_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_shrav_qb ¶
    Source

    inst_shrav_qb :: inst_shrav_qb_r_r_r

    inst_shrav_qb_r_r_r ¶
    Source

    inst_shrav_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_shrav_r_ph ¶
    Source

    inst_shrav_r_ph :: inst_shrav_r_ph_r_r_r

    inst_shrav_r_ph_r_r_r ¶
    Source

    inst_shrav_r_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_shrav_r_qb ¶
    Source

    inst_shrav_r_qb :: inst_shrav_r_qb_r_r_r

    inst_shrav_r_qb_r_r_r ¶
    Source

    inst_shrav_r_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_shrav_r_w ¶
    Source

    inst_shrav_r_w :: inst_shrav_r_w_r_r_r

    inst_shrav_r_w_r_r_r ¶
    Source

    inst_shrav_r_w_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_shrl_ph ¶
    Source

    inst_shrl_ph :: inst_shrl_ph_r_r_i5

    inst_shrl_ph_r_r_i5 ¶
    Source

    inst_shrl_ph_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_shrl_qb ¶
    Source

    inst_shrl_qb :: inst_shrl_qb_r_r_i5

    inst_shrl_qb_r_r_i5 ¶
    Source

    inst_shrl_qb_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_shrlv_ph ¶
    Source

    inst_shrlv_ph :: inst_shrlv_ph_r_r_r

    inst_shrlv_ph_r_r_r ¶
    Source

    inst_shrlv_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_shrlv_qb ¶
    Source

    inst_shrlv_qb :: inst_shrlv_qb_r_r_r

    inst_shrlv_qb_r_r_r ¶
    Source

    inst_shrlv_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_sigrie ¶
    Source

    inst_sigrie :: inst_sigrie_u16

    inst_sigrie_u16 ¶
    Source

    inst_sigrie_u16 :: proc "contextless" (imm: i64) -> Instruction {…}

    inst_sld_b ¶
    Source

    inst_sld_b :: inst_sld_b_w_w_r

    inst_sld_b_w_w_r ¶
    Source

    inst_sld_b_w_w_r :: proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction {…}

    inst_sld_d ¶
    Source

    inst_sld_d :: inst_sld_d_w_w_r

    inst_sld_d_w_w_r ¶
    Source

    inst_sld_d_w_w_r :: proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction {…}

    inst_sld_h ¶
    Source

    inst_sld_h :: inst_sld_h_w_w_r

    inst_sld_h_w_w_r ¶
    Source

    inst_sld_h_w_w_r :: proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction {…}

    inst_sld_w ¶
    Source

    inst_sld_w :: inst_sld_w_w_w_r

    inst_sld_w_w_w_r ¶
    Source

    inst_sld_w_w_w_r :: proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction {…}

    inst_sldi_b ¶
    Source

    inst_sldi_b :: inst_sldi_b_w_w_i5

    inst_sldi_b_w_w_i5 ¶
    Source

    inst_sldi_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_sldi_d ¶
    Source

    inst_sldi_d :: inst_sldi_d_w_w_i5

    inst_sldi_d_w_w_i5 ¶
    Source

    inst_sldi_d_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_sldi_h ¶
    Source

    inst_sldi_h :: inst_sldi_h_w_w_i5

    inst_sldi_h_w_w_i5 ¶
    Source

    inst_sldi_h_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_sldi_w ¶
    Source

    inst_sldi_w :: inst_sldi_w_w_w_i5

    inst_sldi_w_w_w_i5 ¶
    Source

    inst_sldi_w_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_sll ¶
    Source

    inst_sll :: inst_sll_r_r_i5

    inst_sll_b ¶
    Source

    inst_sll_b :: inst_sll_b_w_w_w

    inst_sll_b_w_w_w ¶
    Source

    inst_sll_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_sll_d ¶
    Source

    inst_sll_d :: inst_sll_d_w_w_w

    inst_sll_d_w_w_w ¶
    Source

    inst_sll_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_sll_h ¶
    Source

    inst_sll_h :: inst_sll_h_w_w_w

    inst_sll_h_w_w_w ¶
    Source

    inst_sll_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_sll_r_r_i5 ¶
    Source

    inst_sll_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_sll_w ¶
    Source

    inst_sll_w :: inst_sll_w_w_w_w

    inst_sll_w_w_w_w ¶
    Source

    inst_sll_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_slli_b ¶
    Source

    inst_slli_b :: inst_slli_b_w_w_i5

    inst_slli_b_w_w_i5 ¶
    Source

    inst_slli_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_slli_d ¶
    Source

    inst_slli_d :: inst_slli_d_w_w_i5

    inst_slli_d_w_w_i5 ¶
    Source

    inst_slli_d_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_slli_h ¶
    Source

    inst_slli_h :: inst_slli_h_w_w_i5

    inst_slli_h_w_w_i5 ¶
    Source

    inst_slli_h_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_slli_w ¶
    Source

    inst_slli_w :: inst_slli_w_w_w_i5

    inst_slli_w_w_w_i5 ¶
    Source

    inst_slli_w_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_sllv ¶
    Source

    inst_sllv :: inst_sllv_r_r_r

    inst_sllv_r_r_r ¶
    Source

    inst_sllv_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_slt ¶
    Source

    inst_slt :: inst_slt_r_r_r

    inst_slt_r_r_r ¶
    Source

    inst_slt_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_slti ¶
    Source

    inst_slti :: inst_slti_r_r_i16

    inst_slti_r_r_i16 ¶
    Source

    inst_slti_r_r_i16 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_sltiu ¶
    Source

    inst_sltiu :: inst_sltiu_r_r_i16

    inst_sltiu_r_r_i16 ¶
    Source

    inst_sltiu_r_r_i16 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_sltu ¶
    Source

    inst_sltu :: inst_sltu_r_r_r

    inst_sltu_r_r_r ¶
    Source

    inst_sltu_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_splat_b ¶
    Source

    inst_splat_b :: inst_splat_b_w_w_r

    inst_splat_b_w_w_r ¶
    Source

    inst_splat_b_w_w_r :: proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction {…}

    inst_splat_d ¶
    Source

    inst_splat_d :: inst_splat_d_w_w_r

    inst_splat_d_w_w_r ¶
    Source

    inst_splat_d_w_w_r :: proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction {…}

    inst_splat_h ¶
    Source

    inst_splat_h :: inst_splat_h_w_w_r

    inst_splat_h_w_w_r ¶
    Source

    inst_splat_h_w_w_r :: proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction {…}

    inst_splat_w ¶
    Source

    inst_splat_w :: inst_splat_w_w_w_r

    inst_splat_w_w_w_r ¶
    Source

    inst_splat_w_w_w_r :: proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction {…}

    inst_splati_b ¶
    Source

    inst_splati_b :: inst_splati_b_w_w_i5

    inst_splati_b_w_w_i5 ¶
    Source

    inst_splati_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_splati_d ¶
    Source

    inst_splati_d :: inst_splati_d_w_w_i5

    inst_splati_d_w_w_i5 ¶
    Source

    inst_splati_d_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_splati_h ¶
    Source

    inst_splati_h :: inst_splati_h_w_w_i5

    inst_splati_h_w_w_i5 ¶
    Source

    inst_splati_h_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_splati_w ¶
    Source

    inst_splati_w :: inst_splati_w_w_w_i5

    inst_splati_w_w_w_i5 ¶
    Source

    inst_splati_w_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_sq ¶
    Source

    inst_sq :: inst_sq_r_m

    inst_sq_r_m ¶
    Source

    inst_sq_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_sqc2 ¶
    Source

    inst_sqc2 :: inst_sqc2_c2_m

    inst_sqc2_c2_m ¶
    Source

    inst_sqc2_c2_m :: proc "contextless" (dst: GTE_DataReg, mem: Memory) -> Instruction {…}

    inst_sqr_gte ¶
    Source

    inst_sqr_gte :: inst_sqr_gte_none

    inst_sqr_gte_none ¶
    Source

    inst_sqr_gte_none :: proc "contextless" () -> Instruction {…}

    inst_sqrt_d ¶
    Source

    inst_sqrt_d :: inst_sqrt_d_f_f

    inst_sqrt_d_f_f ¶
    Source

    inst_sqrt_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_sqrt_s ¶
    Source

    inst_sqrt_s :: inst_sqrt_s_f_f

    inst_sqrt_s_f_f ¶
    Source

    inst_sqrt_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_sra ¶
    Source

    inst_sra :: inst_sra_r_r_i5

    inst_sra_b ¶
    Source

    inst_sra_b :: inst_sra_b_w_w_w

    inst_sra_b_w_w_w ¶
    Source

    inst_sra_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_sra_d ¶
    Source

    inst_sra_d :: inst_sra_d_w_w_w

    inst_sra_d_w_w_w ¶
    Source

    inst_sra_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_sra_h ¶
    Source

    inst_sra_h :: inst_sra_h_w_w_w

    inst_sra_h_w_w_w ¶
    Source

    inst_sra_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_sra_r_r_i5 ¶
    Source

    inst_sra_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_sra_w ¶
    Source

    inst_sra_w :: inst_sra_w_w_w_w

    inst_sra_w_w_w_w ¶
    Source

    inst_sra_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_srai_b ¶
    Source

    inst_srai_b :: inst_srai_b_w_w_i5

    inst_srai_b_w_w_i5 ¶
    Source

    inst_srai_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_srai_d ¶
    Source

    inst_srai_d :: inst_srai_d_w_w_i5

    inst_srai_d_w_w_i5 ¶
    Source

    inst_srai_d_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_srai_h ¶
    Source

    inst_srai_h :: inst_srai_h_w_w_i5

    inst_srai_h_w_w_i5 ¶
    Source

    inst_srai_h_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_srai_w ¶
    Source

    inst_srai_w :: inst_srai_w_w_w_i5

    inst_srai_w_w_w_i5 ¶
    Source

    inst_srai_w_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_srav ¶
    Source

    inst_srav :: inst_srav_r_r_r

    inst_srav_r_r_r ¶
    Source

    inst_srav_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_srl ¶
    Source

    inst_srl :: inst_srl_r_r_i5

    inst_srl_b ¶
    Source

    inst_srl_b :: inst_srl_b_w_w_w

    inst_srl_b_w_w_w ¶
    Source

    inst_srl_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_srl_d ¶
    Source

    inst_srl_d :: inst_srl_d_w_w_w

    inst_srl_d_w_w_w ¶
    Source

    inst_srl_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_srl_h ¶
    Source

    inst_srl_h :: inst_srl_h_w_w_w

    inst_srl_h_w_w_w ¶
    Source

    inst_srl_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_srl_r_r_i5 ¶
    Source

    inst_srl_r_r_i5 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    inst_srl_w ¶
    Source

    inst_srl_w :: inst_srl_w_w_w_w

    inst_srl_w_w_w_w ¶
    Source

    inst_srl_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_srli_b ¶
    Source

    inst_srli_b :: inst_srli_b_w_w_i5

    inst_srli_b_w_w_i5 ¶
    Source

    inst_srli_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_srli_d ¶
    Source

    inst_srli_d :: inst_srli_d_w_w_i5

    inst_srli_d_w_w_i5 ¶
    Source

    inst_srli_d_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_srli_h ¶
    Source

    inst_srli_h :: inst_srli_h_w_w_i5

    inst_srli_h_w_w_i5 ¶
    Source

    inst_srli_h_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_srli_w ¶
    Source

    inst_srli_w :: inst_srli_w_w_w_i5

    inst_srli_w_w_w_i5 ¶
    Source

    inst_srli_w_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_srlv ¶
    Source

    inst_srlv :: inst_srlv_r_r_r

    inst_srlv_r_r_r ¶
    Source

    inst_srlv_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_ssnop ¶
    Source

    inst_ssnop :: inst_ssnop_none

    inst_ssnop_none ¶
    Source

    inst_ssnop_none :: proc "contextless" () -> Instruction {…}

    inst_st_b ¶
    Source

    inst_st_b :: inst_st_b_w_m

    inst_st_b_w_m ¶
    Source

    inst_st_b_w_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_st_d ¶
    Source

    inst_st_d :: inst_st_d_w_m

    inst_st_d_w_m ¶
    Source

    inst_st_d_w_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_st_h ¶
    Source

    inst_st_h :: inst_st_h_w_m

    inst_st_h_w_m ¶
    Source

    inst_st_h_w_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_st_w ¶
    Source

    inst_st_w :: inst_st_w_w_m

    inst_st_w_w_m ¶
    Source

    inst_st_w_w_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_sub ¶
    Source

    inst_sub :: inst_sub_r_r_r

    inst_sub_d ¶
    Source

    inst_sub_d :: inst_sub_d_f_f_f

    inst_sub_d_f_f_f ¶
    Source

    inst_sub_d_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_sub_ps ¶
    Source

    inst_sub_ps :: inst_sub_ps_f_f_f

    inst_sub_ps_f_f_f ¶
    Source

    inst_sub_ps_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_sub_r_r_r ¶
    Source

    inst_sub_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_sub_s ¶
    Source

    inst_sub_s :: inst_sub_s_f_f_f

    inst_sub_s_f_f_f ¶
    Source

    inst_sub_s_f_f_f :: proc "contextless" (dst: FPR, src: FPR, src2: FPR) -> Instruction {…}

    inst_subq_ph ¶
    Source

    inst_subq_ph :: inst_subq_ph_r_r_r

    inst_subq_ph_r_r_r ¶
    Source

    inst_subq_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_subq_s_ph ¶
    Source

    inst_subq_s_ph :: inst_subq_s_ph_r_r_r

    inst_subq_s_ph_r_r_r ¶
    Source

    inst_subq_s_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_subq_s_w ¶
    Source

    inst_subq_s_w :: inst_subq_s_w_r_r_r

    inst_subq_s_w_r_r_r ¶
    Source

    inst_subq_s_w_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_subs_s_b ¶
    Source

    inst_subs_s_b :: inst_subs_s_b_w_w_w

    inst_subs_s_b_w_w_w ¶
    Source

    inst_subs_s_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_subs_s_d ¶
    Source

    inst_subs_s_d :: inst_subs_s_d_w_w_w

    inst_subs_s_d_w_w_w ¶
    Source

    inst_subs_s_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_subs_s_h ¶
    Source

    inst_subs_s_h :: inst_subs_s_h_w_w_w

    inst_subs_s_h_w_w_w ¶
    Source

    inst_subs_s_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_subs_s_w ¶
    Source

    inst_subs_s_w :: inst_subs_s_w_w_w_w

    inst_subs_s_w_w_w_w ¶
    Source

    inst_subs_s_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_subs_u_b ¶
    Source

    inst_subs_u_b :: inst_subs_u_b_w_w_w

    inst_subs_u_b_w_w_w ¶
    Source

    inst_subs_u_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_subs_u_d ¶
    Source

    inst_subs_u_d :: inst_subs_u_d_w_w_w

    inst_subs_u_d_w_w_w ¶
    Source

    inst_subs_u_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_subs_u_h ¶
    Source

    inst_subs_u_h :: inst_subs_u_h_w_w_w

    inst_subs_u_h_w_w_w ¶
    Source

    inst_subs_u_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_subs_u_w ¶
    Source

    inst_subs_u_w :: inst_subs_u_w_w_w_w

    inst_subs_u_w_w_w_w ¶
    Source

    inst_subs_u_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_subu ¶
    Source

    inst_subu :: inst_subu_r_r_r

    inst_subu_ph ¶
    Source

    inst_subu_ph :: inst_subu_ph_r_r_r

    inst_subu_ph_r_r_r ¶
    Source

    inst_subu_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_subu_qb ¶
    Source

    inst_subu_qb :: inst_subu_qb_r_r_r

    inst_subu_qb_r_r_r ¶
    Source

    inst_subu_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_subu_r_r_r ¶
    Source

    inst_subu_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_subu_s_ph ¶
    Source

    inst_subu_s_ph :: inst_subu_s_ph_r_r_r

    inst_subu_s_ph_r_r_r ¶
    Source

    inst_subu_s_ph_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_subu_s_qb ¶
    Source

    inst_subu_s_qb :: inst_subu_s_qb_r_r_r

    inst_subu_s_qb_r_r_r ¶
    Source

    inst_subu_s_qb_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_subv_b ¶
    Source

    inst_subv_b :: inst_subv_b_w_w_w

    inst_subv_b_w_w_w ¶
    Source

    inst_subv_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_subv_d ¶
    Source

    inst_subv_d :: inst_subv_d_w_w_w

    inst_subv_d_w_w_w ¶
    Source

    inst_subv_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_subv_h ¶
    Source

    inst_subv_h :: inst_subv_h_w_w_w

    inst_subv_h_w_w_w ¶
    Source

    inst_subv_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_subv_w ¶
    Source

    inst_subv_w :: inst_subv_w_w_w_w

    inst_subv_w_w_w_w ¶
    Source

    inst_subv_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_sv_q ¶
    Source

    inst_sv_q :: inst_sv_q_vq_m

    inst_sv_q_vq_m ¶
    Source

    inst_sv_q_vq_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_sv_s ¶
    Source

    inst_sv_s :: inst_sv_s_vs_m

    inst_sv_s_vs_m ¶
    Source

    inst_sv_s_vs_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_svl_q ¶
    Source

    inst_svl_q :: inst_svl_q_vq_m

    inst_svl_q_vq_m ¶
    Source

    inst_svl_q_vq_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_svr_q ¶
    Source

    inst_svr_q :: inst_svr_q_vq_m

    inst_svr_q_vq_m ¶
    Source

    inst_svr_q_vq_m :: proc "contextless" (dst: Register, mem: Memory) -> Instruction {…}

    inst_sw ¶
    Source

    inst_sw :: inst_sw_r_m

    inst_sw_r_m ¶
    Source

    inst_sw_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_swc1 ¶
    Source

    inst_swc1 :: inst_swc1_f_m

    inst_swc1_f_m ¶
    Source

    inst_swc1_f_m :: proc "contextless" (dst: FPR, mem: Memory) -> Instruction {…}

    inst_swc2 ¶
    Source

    inst_swc2 :: inst_swc2_c2_m

    inst_swc2_c2_m ¶
    Source

    inst_swc2_c2_m :: proc "contextless" (dst: GTE_DataReg, mem: Memory) -> Instruction {…}

    inst_swl ¶
    Source

    inst_swl :: inst_swl_r_m

    inst_swl_r_m ¶
    Source

    inst_swl_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_swr ¶
    Source

    inst_swr :: inst_swr_r_m

    inst_swr_r_m ¶
    Source

    inst_swr_r_m :: proc "contextless" (dst: GPR, mem: Memory) -> Instruction {…}

    inst_swxc1 ¶
    Source

    inst_swxc1 :: inst_swxc1_f_r_r

    inst_swxc1_f_r_r ¶
    Source

    inst_swxc1_f_r_r :: proc "contextless" (dst: FPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_sync ¶
    Source

    inst_sync :: inst_sync_i5

    inst_sync_i5 ¶
    Source

    inst_sync_i5 :: proc "contextless" (imm: i64) -> Instruction {…}

    inst_syscall ¶
    Source

    inst_syscall :: inst_syscall_i20

    inst_syscall_i20 ¶
    Source

    inst_syscall_i20 :: proc "contextless" (imm: i64) -> Instruction {…}

    inst_teq ¶
    Source

    inst_teq :: inst_teq_r_r

    inst_teq_r_r ¶
    Source

    inst_teq_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_teqi ¶
    Source

    inst_teqi :: inst_teqi_r_i16

    inst_teqi_r_i16 ¶
    Source

    inst_teqi_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_tge ¶
    Source

    inst_tge :: inst_tge_r_r

    inst_tge_r_r ¶
    Source

    inst_tge_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_tgei ¶
    Source

    inst_tgei :: inst_tgei_r_i16

    inst_tgei_r_i16 ¶
    Source

    inst_tgei_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_tgeiu ¶
    Source

    inst_tgeiu :: inst_tgeiu_r_i16

    inst_tgeiu_r_i16 ¶
    Source

    inst_tgeiu_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_tgeu ¶
    Source

    inst_tgeu :: inst_tgeu_r_r

    inst_tgeu_r_r ¶
    Source

    inst_tgeu_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_tlbp ¶
    Source

    inst_tlbp :: inst_tlbp_none

    inst_tlbp_none ¶
    Source

    inst_tlbp_none :: proc "contextless" () -> Instruction {…}

    inst_tlbr ¶
    Source

    inst_tlbr :: inst_tlbr_none

    inst_tlbr_none ¶
    Source

    inst_tlbr_none :: proc "contextless" () -> Instruction {…}

    inst_tlbwi ¶
    Source

    inst_tlbwi :: inst_tlbwi_none

    inst_tlbwi_none ¶
    Source

    inst_tlbwi_none :: proc "contextless" () -> Instruction {…}

    inst_tlbwr ¶
    Source

    inst_tlbwr :: inst_tlbwr_none

    inst_tlbwr_none ¶
    Source

    inst_tlbwr_none :: proc "contextless" () -> Instruction {…}

    inst_tlt ¶
    Source

    inst_tlt :: inst_tlt_r_r

    inst_tlt_r_r ¶
    Source

    inst_tlt_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_tlti ¶
    Source

    inst_tlti :: inst_tlti_r_i16

    inst_tlti_r_i16 ¶
    Source

    inst_tlti_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_tltiu ¶
    Source

    inst_tltiu :: inst_tltiu_r_i16

    inst_tltiu_r_i16 ¶
    Source

    inst_tltiu_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_tltu ¶
    Source

    inst_tltu :: inst_tltu_r_r

    inst_tltu_r_r ¶
    Source

    inst_tltu_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_tne ¶
    Source

    inst_tne :: inst_tne_r_r

    inst_tne_r_r ¶
    Source

    inst_tne_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_tnei ¶
    Source

    inst_tnei :: inst_tnei_r_i16

    inst_tnei_r_i16 ¶
    Source

    inst_tnei_r_i16 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_trunc_l_d ¶
    Source

    inst_trunc_l_d :: inst_trunc_l_d_f_f

    inst_trunc_l_d_f_f ¶
    Source

    inst_trunc_l_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_trunc_l_s ¶
    Source

    inst_trunc_l_s :: inst_trunc_l_s_f_f

    inst_trunc_l_s_f_f ¶
    Source

    inst_trunc_l_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_trunc_w_d ¶
    Source

    inst_trunc_w_d :: inst_trunc_w_d_f_f

    inst_trunc_w_d_f_f ¶
    Source

    inst_trunc_w_d_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_trunc_w_s ¶
    Source

    inst_trunc_w_s :: inst_trunc_w_s_f_f

    inst_trunc_w_s_f_f ¶
    Source

    inst_trunc_w_s_f_f :: proc "contextless" (dst: FPR, src: FPR) -> Instruction {…}

    inst_vabs_p ¶
    Source

    inst_vabs_p :: inst_vabs_p_vp_vp

    inst_vabs_p_vp_vp ¶
    Source

    inst_vabs_p_vp_vp :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vabs_q ¶
    Source

    inst_vabs_q :: inst_vabs_q_vq_vq

    inst_vabs_q_vq_vq ¶
    Source

    inst_vabs_q_vq_vq :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vabs_s ¶
    Source

    inst_vabs_s :: inst_vabs_s_vs_vs

    inst_vabs_s_vs_vs ¶
    Source

    inst_vabs_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vabs_t ¶
    Source

    inst_vabs_t :: inst_vabs_t_vt_vt

    inst_vabs_t_vt_vt ¶
    Source

    inst_vabs_t_vt_vt :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vadd_p ¶
    Source

    inst_vadd_p :: inst_vadd_p_vp_vp_vp

    inst_vadd_p_vp_vp_vp ¶
    Source

    inst_vadd_p_vp_vp_vp :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vadd_q ¶
    Source

    inst_vadd_q :: inst_vadd_q_vq_vq_vq

    inst_vadd_q_vq_vq_vq ¶
    Source

    inst_vadd_q_vq_vq_vq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vadd_s ¶
    Source

    inst_vadd_s :: inst_vadd_s_vs_vs_vs

    inst_vadd_s_vs_vs_vs ¶
    Source

    inst_vadd_s_vs_vs_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vadd_t ¶
    Source

    inst_vadd_t :: inst_vadd_t_vt_vt_vt

    inst_vadd_t_vt_vt_vt ¶
    Source

    inst_vadd_t_vt_vt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vasin_s ¶
    Source

    inst_vasin_s :: inst_vasin_s_vs_vs

    inst_vasin_s_vs_vs ¶
    Source

    inst_vasin_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vavg_p ¶
    Source

    inst_vavg_p :: inst_vavg_p_vs_vp

    inst_vavg_p_vs_vp ¶
    Source

    inst_vavg_p_vs_vp :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vavg_q ¶
    Source

    inst_vavg_q :: inst_vavg_q_vs_vq

    inst_vavg_q_vs_vq ¶
    Source

    inst_vavg_q_vs_vq :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vavg_t ¶
    Source

    inst_vavg_t :: inst_vavg_t_vs_vt

    inst_vavg_t_vs_vt ¶
    Source

    inst_vavg_t_vs_vt :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vcmp_p ¶
    Source

    inst_vcmp_p :: inst_vcmp_p_i5_vp_vp

    inst_vcmp_p_i5_vp_vp ¶
    Source

    inst_vcmp_p_i5_vp_vp :: proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction {…}

    inst_vcmp_q ¶
    Source

    inst_vcmp_q :: inst_vcmp_q_i5_vq_vq

    inst_vcmp_q_i5_vq_vq ¶
    Source

    inst_vcmp_q_i5_vq_vq :: proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction {…}

    inst_vcmp_s ¶
    Source

    inst_vcmp_s :: inst_vcmp_s_i5_vs_vs

    inst_vcmp_s_i5_vs_vs ¶
    Source

    inst_vcmp_s_i5_vs_vs :: proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction {…}

    inst_vcmp_t ¶
    Source

    inst_vcmp_t :: inst_vcmp_t_i5_vt_vt

    inst_vcmp_t_i5_vt_vt ¶
    Source

    inst_vcmp_t_i5_vt_vt :: proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction {…}

    inst_vcos_s ¶
    Source

    inst_vcos_s :: inst_vcos_s_vs_vs

    inst_vcos_s_vs_vs ¶
    Source

    inst_vcos_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vcrs_t ¶
    Source

    inst_vcrs_t :: inst_vcrs_t_vt_vt_vt

    inst_vcrs_t_vt_vt_vt ¶
    Source

    inst_vcrs_t_vt_vt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vcrsp_t ¶
    Source

    inst_vcrsp_t :: inst_vcrsp_t_vt_vt_vt

    inst_vcrsp_t_vt_vt_vt ¶
    Source

    inst_vcrsp_t_vt_vt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vcst_p ¶
    Source

    inst_vcst_p :: inst_vcst_p_vp_i5

    inst_vcst_p_vp_i5 ¶
    Source

    inst_vcst_p_vp_i5 :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

    inst_vcst_q ¶
    Source

    inst_vcst_q :: inst_vcst_q_vq_i5

    inst_vcst_q_vq_i5 ¶
    Source

    inst_vcst_q_vq_i5 :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

    inst_vcst_s ¶
    Source

    inst_vcst_s :: inst_vcst_s_vs_i5

    inst_vcst_s_vs_i5 ¶
    Source

    inst_vcst_s_vs_i5 :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

    inst_vcst_t ¶
    Source

    inst_vcst_t :: inst_vcst_t_vt_i5

    inst_vcst_t_vt_i5 ¶
    Source

    inst_vcst_t_vt_i5 :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

    inst_vdiv_p ¶
    Source

    inst_vdiv_p :: inst_vdiv_p_vp_vp_vp

    inst_vdiv_p_vp_vp_vp ¶
    Source

    inst_vdiv_p_vp_vp_vp :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vdiv_q ¶
    Source

    inst_vdiv_q :: inst_vdiv_q_vq_vq_vq

    inst_vdiv_q_vq_vq_vq ¶
    Source

    inst_vdiv_q_vq_vq_vq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vdiv_s ¶
    Source

    inst_vdiv_s :: inst_vdiv_s_vs_vs_vs

    inst_vdiv_s_vs_vs_vs ¶
    Source

    inst_vdiv_s_vs_vs_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vdiv_t ¶
    Source

    inst_vdiv_t :: inst_vdiv_t_vt_vt_vt

    inst_vdiv_t_vt_vt_vt ¶
    Source

    inst_vdiv_t_vt_vt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vdot_p ¶
    Source

    inst_vdot_p :: inst_vdot_p_vs_vp_vp

    inst_vdot_p_vs_vp_vp ¶
    Source

    inst_vdot_p_vs_vp_vp :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vdot_q ¶
    Source

    inst_vdot_q :: inst_vdot_q_vs_vq_vq

    inst_vdot_q_vs_vq_vq ¶
    Source

    inst_vdot_q_vs_vq_vq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vdot_t ¶
    Source

    inst_vdot_t :: inst_vdot_t_vs_vt_vt

    inst_vdot_t_vs_vt_vt ¶
    Source

    inst_vdot_t_vs_vt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vexp2_s ¶
    Source

    inst_vexp2_s :: inst_vexp2_s_vs_vs

    inst_vexp2_s_vs_vs ¶
    Source

    inst_vexp2_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vf2h_p ¶
    Source

    inst_vf2h_p :: inst_vf2h_p_vs_vp

    inst_vf2h_p_vs_vp ¶
    Source

    inst_vf2h_p_vs_vp :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vf2id_p ¶
    Source

    inst_vf2id_p :: inst_vf2id_p_vp_vp_i5

    inst_vf2id_p_vp_vp_i5 ¶
    Source

    inst_vf2id_p_vp_vp_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2id_q ¶
    Source

    inst_vf2id_q :: inst_vf2id_q_vq_vq_i5

    inst_vf2id_q_vq_vq_i5 ¶
    Source

    inst_vf2id_q_vq_vq_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2id_s ¶
    Source

    inst_vf2id_s :: inst_vf2id_s_vs_vs_i5

    inst_vf2id_s_vs_vs_i5 ¶
    Source

    inst_vf2id_s_vs_vs_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2id_t ¶
    Source

    inst_vf2id_t :: inst_vf2id_t_vt_vt_i5

    inst_vf2id_t_vt_vt_i5 ¶
    Source

    inst_vf2id_t_vt_vt_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2in_p ¶
    Source

    inst_vf2in_p :: inst_vf2in_p_vp_vp_i5

    inst_vf2in_p_vp_vp_i5 ¶
    Source

    inst_vf2in_p_vp_vp_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2in_q ¶
    Source

    inst_vf2in_q :: inst_vf2in_q_vq_vq_i5

    inst_vf2in_q_vq_vq_i5 ¶
    Source

    inst_vf2in_q_vq_vq_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2in_s ¶
    Source

    inst_vf2in_s :: inst_vf2in_s_vs_vs_i5

    inst_vf2in_s_vs_vs_i5 ¶
    Source

    inst_vf2in_s_vs_vs_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2in_t ¶
    Source

    inst_vf2in_t :: inst_vf2in_t_vt_vt_i5

    inst_vf2in_t_vt_vt_i5 ¶
    Source

    inst_vf2in_t_vt_vt_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2iu_p ¶
    Source

    inst_vf2iu_p :: inst_vf2iu_p_vp_vp_i5

    inst_vf2iu_p_vp_vp_i5 ¶
    Source

    inst_vf2iu_p_vp_vp_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2iu_q ¶
    Source

    inst_vf2iu_q :: inst_vf2iu_q_vq_vq_i5

    inst_vf2iu_q_vq_vq_i5 ¶
    Source

    inst_vf2iu_q_vq_vq_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2iu_s ¶
    Source

    inst_vf2iu_s :: inst_vf2iu_s_vs_vs_i5

    inst_vf2iu_s_vs_vs_i5 ¶
    Source

    inst_vf2iu_s_vs_vs_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2iu_t ¶
    Source

    inst_vf2iu_t :: inst_vf2iu_t_vt_vt_i5

    inst_vf2iu_t_vt_vt_i5 ¶
    Source

    inst_vf2iu_t_vt_vt_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2iz_p ¶
    Source

    inst_vf2iz_p :: inst_vf2iz_p_vp_vp_i5

    inst_vf2iz_p_vp_vp_i5 ¶
    Source

    inst_vf2iz_p_vp_vp_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2iz_q ¶
    Source

    inst_vf2iz_q :: inst_vf2iz_q_vq_vq_i5

    inst_vf2iz_q_vq_vq_i5 ¶
    Source

    inst_vf2iz_q_vq_vq_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2iz_s ¶
    Source

    inst_vf2iz_s :: inst_vf2iz_s_vs_vs_i5

    inst_vf2iz_s_vs_vs_i5 ¶
    Source

    inst_vf2iz_s_vs_vs_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vf2iz_t ¶
    Source

    inst_vf2iz_t :: inst_vf2iz_t_vt_vt_i5

    inst_vf2iz_t_vt_vt_i5 ¶
    Source

    inst_vf2iz_t_vt_vt_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vfad_p ¶
    Source

    inst_vfad_p :: inst_vfad_p_vs_vp

    inst_vfad_p_vs_vp ¶
    Source

    inst_vfad_p_vs_vp :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vfad_q ¶
    Source

    inst_vfad_q :: inst_vfad_q_vs_vq

    inst_vfad_q_vs_vq ¶
    Source

    inst_vfad_q_vs_vq :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vfad_t ¶
    Source

    inst_vfad_t :: inst_vfad_t_vs_vt

    inst_vfad_t_vs_vt ¶
    Source

    inst_vfad_t_vs_vt :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vfim_s ¶
    Source

    inst_vfim_s :: inst_vfim_s_vs_i16

    inst_vfim_s_vs_i16 ¶
    Source

    inst_vfim_s_vs_i16 :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

    inst_vflush ¶
    Source

    inst_vflush :: inst_vflush_none

    inst_vflush_none ¶
    Source

    inst_vflush_none :: proc "contextless" () -> Instruction {…}

    inst_vh2f_s ¶
    Source

    inst_vh2f_s :: inst_vh2f_s_vp_vs

    inst_vh2f_s_vp_vs ¶
    Source

    inst_vh2f_s_vp_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vhdp_p ¶
    Source

    inst_vhdp_p :: inst_vhdp_p_vs_vp_vp

    inst_vhdp_p_vs_vp_vp ¶
    Source

    inst_vhdp_p_vs_vp_vp :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vhdp_q ¶
    Source

    inst_vhdp_q :: inst_vhdp_q_vs_vq_vq

    inst_vhdp_q_vs_vq_vq ¶
    Source

    inst_vhdp_q_vs_vq_vq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vhdp_t ¶
    Source

    inst_vhdp_t :: inst_vhdp_t_vs_vt_vt

    inst_vhdp_t_vs_vt_vt ¶
    Source

    inst_vhdp_t_vs_vt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vhtfm2_p ¶
    Source

    inst_vhtfm2_p :: inst_vhtfm2_p_vp_vmp_vp

    inst_vhtfm2_p_vp_vmp_vp ¶
    Source

    inst_vhtfm2_p_vp_vmp_vp :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vhtfm3_t ¶
    Source

    inst_vhtfm3_t :: inst_vhtfm3_t_vt_vmt_vt

    inst_vhtfm3_t_vt_vmt_vt ¶
    Source

    inst_vhtfm3_t_vt_vmt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vhtfm4_q ¶
    Source

    inst_vhtfm4_q :: inst_vhtfm4_q_vq_vmq_vq

    inst_vhtfm4_q_vq_vmq_vq ¶
    Source

    inst_vhtfm4_q_vq_vmq_vq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vi2f_p ¶
    Source

    inst_vi2f_p :: inst_vi2f_p_vp_vp_i5

    inst_vi2f_p_vp_vp_i5 ¶
    Source

    inst_vi2f_p_vp_vp_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vi2f_q ¶
    Source

    inst_vi2f_q :: inst_vi2f_q_vq_vq_i5

    inst_vi2f_q_vq_vq_i5 ¶
    Source

    inst_vi2f_q_vq_vq_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vi2f_s ¶
    Source

    inst_vi2f_s :: inst_vi2f_s_vs_vs_i5

    inst_vi2f_s_vs_vs_i5 ¶
    Source

    inst_vi2f_s_vs_vs_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_vi2f_t ¶
    Source

    inst_vi2f_t :: inst_vi2f_t_vt_vt_i5

    inst_vi2f_t_vt_vt_i5 ¶
    Source

    inst_vi2f_t_vt_vt_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_viim_s ¶
    Source

    inst_viim_s :: inst_viim_s_vs_i16

    inst_viim_s_vs_i16 ¶
    Source

    inst_viim_s_vs_i16 :: proc "contextless" (dst: Register, imm: i64) -> Instruction {…}

    inst_vlog2_s ¶
    Source

    inst_vlog2_s :: inst_vlog2_s_vs_vs

    inst_vlog2_s_vs_vs ¶
    Source

    inst_vlog2_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vmax_p ¶
    Source

    inst_vmax_p :: inst_vmax_p_vp_vp_vp

    inst_vmax_p_vp_vp_vp ¶
    Source

    inst_vmax_p_vp_vp_vp :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmax_q ¶
    Source

    inst_vmax_q :: inst_vmax_q_vq_vq_vq

    inst_vmax_q_vq_vq_vq ¶
    Source

    inst_vmax_q_vq_vq_vq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmax_s ¶
    Source

    inst_vmax_s :: inst_vmax_s_vs_vs_vs

    inst_vmax_s_vs_vs_vs ¶
    Source

    inst_vmax_s_vs_vs_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmax_t ¶
    Source

    inst_vmax_t :: inst_vmax_t_vt_vt_vt

    inst_vmax_t_vt_vt_vt ¶
    Source

    inst_vmax_t_vt_vt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmidt_p ¶
    Source

    inst_vmidt_p :: inst_vmidt_p_vmp

    inst_vmidt_p_vmp ¶
    Source

    inst_vmidt_p_vmp :: proc "contextless" (dst: Register) -> Instruction {…}

    inst_vmidt_q ¶
    Source

    inst_vmidt_q :: inst_vmidt_q_vmq

    inst_vmidt_q_vmq ¶
    Source

    inst_vmidt_q_vmq :: proc "contextless" (dst: Register) -> Instruction {…}

    inst_vmidt_t ¶
    Source

    inst_vmidt_t :: inst_vmidt_t_vmt

    inst_vmidt_t_vmt ¶
    Source

    inst_vmidt_t_vmt :: proc "contextless" (dst: Register) -> Instruction {…}

    inst_vmin_p ¶
    Source

    inst_vmin_p :: inst_vmin_p_vp_vp_vp

    inst_vmin_p_vp_vp_vp ¶
    Source

    inst_vmin_p_vp_vp_vp :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmin_q ¶
    Source

    inst_vmin_q :: inst_vmin_q_vq_vq_vq

    inst_vmin_q_vq_vq_vq ¶
    Source

    inst_vmin_q_vq_vq_vq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmin_s ¶
    Source

    inst_vmin_s :: inst_vmin_s_vs_vs_vs

    inst_vmin_s_vs_vs_vs ¶
    Source

    inst_vmin_s_vs_vs_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmin_t ¶
    Source

    inst_vmin_t :: inst_vmin_t_vt_vt_vt

    inst_vmin_t_vt_vt_vt ¶
    Source

    inst_vmin_t_vt_vt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmmov_p ¶
    Source

    inst_vmmov_p :: inst_vmmov_p_vmp_vmp

    inst_vmmov_p_vmp_vmp ¶
    Source

    inst_vmmov_p_vmp_vmp :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vmmov_q ¶
    Source

    inst_vmmov_q :: inst_vmmov_q_vmq_vmq

    inst_vmmov_q_vmq_vmq ¶
    Source

    inst_vmmov_q_vmq_vmq :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vmmov_t ¶
    Source

    inst_vmmov_t :: inst_vmmov_t_vmt_vmt

    inst_vmmov_t_vmt_vmt ¶
    Source

    inst_vmmov_t_vmt_vmt :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vmmul_p ¶
    Source

    inst_vmmul_p :: inst_vmmul_p_vmp_vmp_vmp

    inst_vmmul_p_vmp_vmp_vmp ¶
    Source

    inst_vmmul_p_vmp_vmp_vmp :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmmul_q ¶
    Source

    inst_vmmul_q :: inst_vmmul_q_vmq_vmq_vmq

    inst_vmmul_q_vmq_vmq_vmq ¶
    Source

    inst_vmmul_q_vmq_vmq_vmq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmmul_t ¶
    Source

    inst_vmmul_t :: inst_vmmul_t_vmt_vmt_vmt

    inst_vmmul_t_vmt_vmt_vmt ¶
    Source

    inst_vmmul_t_vmt_vmt_vmt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmone_p ¶
    Source

    inst_vmone_p :: inst_vmone_p_vmp

    inst_vmone_p_vmp ¶
    Source

    inst_vmone_p_vmp :: proc "contextless" (dst: Register) -> Instruction {…}

    inst_vmone_q ¶
    Source

    inst_vmone_q :: inst_vmone_q_vmq

    inst_vmone_q_vmq ¶
    Source

    inst_vmone_q_vmq :: proc "contextless" (dst: Register) -> Instruction {…}

    inst_vmone_t ¶
    Source

    inst_vmone_t :: inst_vmone_t_vmt

    inst_vmone_t_vmt ¶
    Source

    inst_vmone_t_vmt :: proc "contextless" (dst: Register) -> Instruction {…}

    inst_vmov_p ¶
    Source

    inst_vmov_p :: inst_vmov_p_vp_vp

    inst_vmov_p_vp_vp ¶
    Source

    inst_vmov_p_vp_vp :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vmov_q ¶
    Source

    inst_vmov_q :: inst_vmov_q_vq_vq

    inst_vmov_q_vq_vq ¶
    Source

    inst_vmov_q_vq_vq :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vmov_s ¶
    Source

    inst_vmov_s :: inst_vmov_s_vs_vs

    inst_vmov_s_vs_vs ¶
    Source

    inst_vmov_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vmov_t ¶
    Source

    inst_vmov_t :: inst_vmov_t_vt_vt

    inst_vmov_t_vt_vt ¶
    Source

    inst_vmov_t_vt_vt :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vmscl_p ¶
    Source

    inst_vmscl_p :: inst_vmscl_p_vmp_vmp_vs

    inst_vmscl_p_vmp_vmp_vs ¶
    Source

    inst_vmscl_p_vmp_vmp_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmscl_q ¶
    Source

    inst_vmscl_q :: inst_vmscl_q_vmq_vmq_vs

    inst_vmscl_q_vmq_vmq_vs ¶
    Source

    inst_vmscl_q_vmq_vmq_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmscl_t ¶
    Source

    inst_vmscl_t :: inst_vmscl_t_vmt_vmt_vs

    inst_vmscl_t_vmt_vmt_vs ¶
    Source

    inst_vmscl_t_vmt_vmt_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmul_p ¶
    Source

    inst_vmul_p :: inst_vmul_p_vp_vp_vp

    inst_vmul_p_vp_vp_vp ¶
    Source

    inst_vmul_p_vp_vp_vp :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmul_q ¶
    Source

    inst_vmul_q :: inst_vmul_q_vq_vq_vq

    inst_vmul_q_vq_vq_vq ¶
    Source

    inst_vmul_q_vq_vq_vq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmul_s ¶
    Source

    inst_vmul_s :: inst_vmul_s_vs_vs_vs

    inst_vmul_s_vs_vs_vs ¶
    Source

    inst_vmul_s_vs_vs_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmul_t ¶
    Source

    inst_vmul_t :: inst_vmul_t_vt_vt_vt

    inst_vmul_t_vt_vt_vt ¶
    Source

    inst_vmul_t_vt_vt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vmzero_p ¶
    Source

    inst_vmzero_p :: inst_vmzero_p_vmp

    inst_vmzero_p_vmp ¶
    Source

    inst_vmzero_p_vmp :: proc "contextless" (dst: Register) -> Instruction {…}

    inst_vmzero_q ¶
    Source

    inst_vmzero_q :: inst_vmzero_q_vmq

    inst_vmzero_q_vmq ¶
    Source

    inst_vmzero_q_vmq :: proc "contextless" (dst: Register) -> Instruction {…}

    inst_vmzero_t ¶
    Source

    inst_vmzero_t :: inst_vmzero_t_vmt

    inst_vmzero_t_vmt ¶
    Source

    inst_vmzero_t_vmt :: proc "contextless" (dst: Register) -> Instruction {…}

    inst_vneg_p ¶
    Source

    inst_vneg_p :: inst_vneg_p_vp_vp

    inst_vneg_p_vp_vp ¶
    Source

    inst_vneg_p_vp_vp :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vneg_q ¶
    Source

    inst_vneg_q :: inst_vneg_q_vq_vq

    inst_vneg_q_vq_vq ¶
    Source

    inst_vneg_q_vq_vq :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vneg_s ¶
    Source

    inst_vneg_s :: inst_vneg_s_vs_vs

    inst_vneg_s_vs_vs ¶
    Source

    inst_vneg_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vneg_t ¶
    Source

    inst_vneg_t :: inst_vneg_t_vt_vt

    inst_vneg_t_vt_vt ¶
    Source

    inst_vneg_t_vt_vt :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vnop ¶
    Source

    inst_vnop :: inst_vnop_none

    inst_vnop_none ¶
    Source

    inst_vnop_none :: proc "contextless" () -> Instruction {…}

    inst_vnrcp_s ¶
    Source

    inst_vnrcp_s :: inst_vnrcp_s_vs_vs

    inst_vnrcp_s_vs_vs ¶
    Source

    inst_vnrcp_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vnsin_s ¶
    Source

    inst_vnsin_s :: inst_vnsin_s_vs_vs

    inst_vnsin_s_vs_vs ¶
    Source

    inst_vnsin_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vpfxd ¶
    Source

    inst_vpfxd :: inst_vpfxd_i20

    inst_vpfxd_i20 ¶
    Source

    inst_vpfxd_i20 :: proc "contextless" (imm: i64) -> Instruction {…}

    inst_vpfxs ¶
    Source

    inst_vpfxs :: inst_vpfxs_i20

    inst_vpfxs_i20 ¶
    Source

    inst_vpfxs_i20 :: proc "contextless" (imm: i64) -> Instruction {…}

    inst_vpfxt ¶
    Source

    inst_vpfxt :: inst_vpfxt_i20

    inst_vpfxt_i20 ¶
    Source

    inst_vpfxt_i20 :: proc "contextless" (imm: i64) -> Instruction {…}

    inst_vqmul_q ¶
    Source

    inst_vqmul_q :: inst_vqmul_q_vq_vq_vq

    inst_vqmul_q_vq_vq_vq ¶
    Source

    inst_vqmul_q_vq_vq_vq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vrcp_p ¶
    Source

    inst_vrcp_p :: inst_vrcp_p_vp_vp

    inst_vrcp_p_vp_vp ¶
    Source

    inst_vrcp_p_vp_vp :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vrcp_q ¶
    Source

    inst_vrcp_q :: inst_vrcp_q_vq_vq

    inst_vrcp_q_vq_vq ¶
    Source

    inst_vrcp_q_vq_vq :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vrcp_s ¶
    Source

    inst_vrcp_s :: inst_vrcp_s_vs_vs

    inst_vrcp_s_vs_vs ¶
    Source

    inst_vrcp_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vrcp_t ¶
    Source

    inst_vrcp_t :: inst_vrcp_t_vt_vt

    inst_vrcp_t_vt_vt ¶
    Source

    inst_vrcp_t_vt_vt :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vrexp2_s ¶
    Source

    inst_vrexp2_s :: inst_vrexp2_s_vs_vs

    inst_vrexp2_s_vs_vs ¶
    Source

    inst_vrexp2_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vrsq_p ¶
    Source

    inst_vrsq_p :: inst_vrsq_p_vp_vp

    inst_vrsq_p_vp_vp ¶
    Source

    inst_vrsq_p_vp_vp :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vrsq_q ¶
    Source

    inst_vrsq_q :: inst_vrsq_q_vq_vq

    inst_vrsq_q_vq_vq ¶
    Source

    inst_vrsq_q_vq_vq :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vrsq_s ¶
    Source

    inst_vrsq_s :: inst_vrsq_s_vs_vs

    inst_vrsq_s_vs_vs ¶
    Source

    inst_vrsq_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vrsq_t ¶
    Source

    inst_vrsq_t :: inst_vrsq_t_vt_vt

    inst_vrsq_t_vt_vt ¶
    Source

    inst_vrsq_t_vt_vt :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vscl_p ¶
    Source

    inst_vscl_p :: inst_vscl_p_vp_vp_vs

    inst_vscl_p_vp_vp_vs ¶
    Source

    inst_vscl_p_vp_vp_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vscl_q ¶
    Source

    inst_vscl_q :: inst_vscl_q_vq_vq_vs

    inst_vscl_q_vq_vq_vs ¶
    Source

    inst_vscl_q_vq_vq_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vscl_t ¶
    Source

    inst_vscl_t :: inst_vscl_t_vt_vt_vs

    inst_vscl_t_vt_vt_vs ¶
    Source

    inst_vscl_t_vt_vt_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vsgn_s ¶
    Source

    inst_vsgn_s :: inst_vsgn_s_vs_vs

    inst_vsgn_s_vs_vs ¶
    Source

    inst_vsgn_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vshf_b ¶
    Source

    inst_vshf_b :: inst_vshf_b_w_w_w

    inst_vshf_b_w_w_w ¶
    Source

    inst_vshf_b_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vshf_d ¶
    Source

    inst_vshf_d :: inst_vshf_d_w_w_w

    inst_vshf_d_w_w_w ¶
    Source

    inst_vshf_d_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vshf_h ¶
    Source

    inst_vshf_h :: inst_vshf_h_w_w_w

    inst_vshf_h_w_w_w ¶
    Source

    inst_vshf_h_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vshf_w ¶
    Source

    inst_vshf_w :: inst_vshf_w_w_w_w

    inst_vshf_w_w_w_w ¶
    Source

    inst_vshf_w_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vsin_s ¶
    Source

    inst_vsin_s :: inst_vsin_s_vs_vs

    inst_vsin_s_vs_vs ¶
    Source

    inst_vsin_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vsqrt_s ¶
    Source

    inst_vsqrt_s :: inst_vsqrt_s_vs_vs

    inst_vsqrt_s_vs_vs ¶
    Source

    inst_vsqrt_s_vs_vs :: proc "contextless" (dst: Register, src: Register) -> Instruction {…}

    inst_vsub_p ¶
    Source

    inst_vsub_p :: inst_vsub_p_vp_vp_vp

    inst_vsub_p_vp_vp_vp ¶
    Source

    inst_vsub_p_vp_vp_vp :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vsub_q ¶
    Source

    inst_vsub_q :: inst_vsub_q_vq_vq_vq

    inst_vsub_q_vq_vq_vq ¶
    Source

    inst_vsub_q_vq_vq_vq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vsub_s ¶
    Source

    inst_vsub_s :: inst_vsub_s_vs_vs_vs

    inst_vsub_s_vs_vs_vs ¶
    Source

    inst_vsub_s_vs_vs_vs :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vsub_t ¶
    Source

    inst_vsub_t :: inst_vsub_t_vt_vt_vt

    inst_vsub_t_vt_vt_vt ¶
    Source

    inst_vsub_t_vt_vt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vsync ¶
    Source

    inst_vsync :: inst_vsync_none

    inst_vsync_none ¶
    Source

    inst_vsync_none :: proc "contextless" () -> Instruction {…}

    inst_vtfm2_p ¶
    Source

    inst_vtfm2_p :: inst_vtfm2_p_vp_vmp_vp

    inst_vtfm2_p_vp_vmp_vp ¶
    Source

    inst_vtfm2_p_vp_vmp_vp :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vtfm3_t ¶
    Source

    inst_vtfm3_t :: inst_vtfm3_t_vt_vmt_vt

    inst_vtfm3_t_vt_vmt_vt ¶
    Source

    inst_vtfm3_t_vt_vmt_vt :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_vtfm4_q ¶
    Source

    inst_vtfm4_q :: inst_vtfm4_q_vq_vmq_vq

    inst_vtfm4_q_vq_vmq_vq ¶
    Source

    inst_vtfm4_q_vq_vmq_vq :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_wait ¶
    Source

    inst_wait :: inst_wait_none

    inst_wait_none ¶
    Source

    inst_wait_none :: proc "contextless" () -> Instruction {…}

    inst_wrdsp ¶
    Source

    inst_wrdsp :: inst_wrdsp_r_i5

    inst_wrdsp_r_i5 ¶
    Source

    inst_wrdsp_r_i5 :: proc "contextless" (dst: GPR, imm: i64) -> Instruction {…}

    inst_wrpgpr ¶
    Source

    inst_wrpgpr :: inst_wrpgpr_r_r

    inst_wrpgpr_r_r ¶
    Source

    inst_wrpgpr_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_wsbh ¶
    Source

    inst_wsbh :: inst_wsbh_r_r

    inst_wsbh_r_r ¶
    Source

    inst_wsbh_r_r :: proc "contextless" (dst: GPR, src: GPR) -> Instruction {…}

    inst_xor ¶
    Source

    inst_xor :: inst_xor_r_r_r

    inst_xor_r_r_r ¶
    Source

    inst_xor_r_r_r :: proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction {…}

    inst_xor_v ¶
    Source

    inst_xor_v :: inst_xor_v_w_w_w

    inst_xor_v_w_w_w ¶
    Source

    inst_xor_v_w_w_w :: proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction {…}

    inst_xori ¶
    Source

    inst_xori :: inst_xori_r_r_u16

    inst_xori_b ¶
    Source

    inst_xori_b :: inst_xori_b_w_w_i5

    inst_xori_b_w_w_i5 ¶
    Source

    inst_xori_b_w_w_i5 :: proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction {…}

    inst_xori_r_r_u16 ¶
    Source

    inst_xori_r_r_u16 :: proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction {…}

    mem ¶
    Source

    mem :: proc "contextless" (base: Register, disp: i32) -> Memory {…}

    mem_base ¶
    Source

    mem_base :: proc "contextless" (m: Memory) -> Register {…}

    mem_base_disp ¶
    Source

    mem_base_disp :: mem

    mem_base_only ¶
    Source

    mem_base_only :: proc "contextless" (base: Register) -> Memory {…}

    mem_disp ¶
    Source

    mem_disp :: proc "contextless" (m: Memory) -> i32 {…}

    mnemonic_to_string ¶
    Source

    mnemonic_to_string :: proc(m: Mnemonic, lowercase: bool = true, allocator := context.temp_allocator) -> string {…}
     

    Canonical mnemonic spelling (lowercase, with _ mapped to .). The few enum names that carry a disambiguator suffix get a hand mapping.

    msa_from_num ¶
    Source

    msa_from_num :: proc "contextless" (num: u8) -> Register {…}

    op_cp0 ¶
    Source

    op_cp0 :: proc "contextless" (c: CP0_Reg) -> Operand {…}

    op_fpr ¶
    Source

    op_fpr :: proc "contextless" (f: FPR) -> Operand {…}

    op_gpr ¶
    Source

    op_gpr :: proc "contextless" (g: GPR) -> Operand {…}

    op_gte_ctrl ¶
    Source

    op_gte_ctrl :: proc "contextless" (r: GTE_CtrlReg) -> Operand {…}

    op_gte_data ¶
    Source

    op_gte_data :: proc "contextless" (r: GTE_DataReg) -> Operand {…}

    op_imm ¶
    Source

    op_imm :: proc "contextless" (v: i64, size: u8) -> Operand {…}

    op_label ¶
    Source

    op_label :: proc "contextless" (label_id: u32) -> Operand {…}
     

    Branch/jump target operand. label_id indexes a Label_Definition array (resolved by the encoder during pass 2 -- same model as x86).

    op_mem ¶
    Source

    op_mem :: proc "contextless" (m: Memory, size: u8) -> Operand {…}

    op_reg ¶
    Source

    op_reg :: proc "contextless" (r: Register) -> Operand {…}

    op_reg_sized ¶
    Source

    op_reg_sized :: proc "contextless" (r: Register, size: u8) -> Operand {…}

    op_rel_offset ¶
    Source

    op_rel_offset :: proc "contextless" (offset: i64) -> Operand {…}
     

    Raw offset (skip label resolution).

    opcode_bits ¶
    Source

    opcode_bits :: proc "contextless" (op: u32) -> u32 {…}
     

    Convenience constructor for a 6-bit primary opcode at bits 31-26.

    print ¶
    Source

    print :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    println ¶
    Source

    println :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    read_u32 ¶
    Source

    read_u32 :: proc "contextless" (code: []u8, offset: u32, endianness: Endianness) -> u32 {…}

    reg_class ¶
    Source

    reg_class :: proc "contextless" (r: Register) -> u16 {…}

    reg_hw ¶
    Source

    reg_hw :: proc "contextless" (r: Register) -> u8 {…}

    reg_is_fpr ¶
    Source

    reg_is_fpr :: proc "contextless" (r: Register) -> bool {…}

    reg_is_gpr ¶
    Source

    reg_is_gpr :: proc "contextless" (r: Register) -> bool {…}

    reg_is_msa ¶
    Source

    reg_is_msa :: proc "contextless" (r: Register) -> bool {…}

    reg_is_vfpu ¶
    Source

    reg_is_vfpu :: proc "contextless" (r: Register) -> bool {…}

    reg_vfpu_hw ¶
    Source

    reg_vfpu_hw :: proc "contextless" (r: Register) -> u8 {…}
     

    VFPU hardware-id accessor (7 bits vs the standard reg_hw's 5).

    register_name ¶
    Source

    register_name :: proc(r: Register, lowercase: bool = true, allocator := context.temp_allocator) -> string {…}
     

    Canonical register name with leading $.

    sbprint ¶
    Source

    sbprint :: proc(
	sb:           ^strings.Builder, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    sbprintln ¶
    Source

    sbprintln :: proc(
	sb:           ^strings.Builder, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    swap_bytes_u32_inplace ¶
    Source

    swap_bytes_u32_inplace :: proc(code: []u8) {…}
     

    In-place 32-bit byte-swap of code. Length must be a multiple of 4. Useful for switching a freshly-encoded buffer from native to wire endian when the consumer wants a single endian-conversion sweep after encoding.

    tprint ¶
    Source

    tprint :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

    tprintln ¶
    Source

    tprintln :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

    vfpu_from_num ¶
    Source

    vfpu_from_num :: proc "contextless" (num: u8) -> Register {…}
     

    VFPU register builder. 7-bit hardware index (0..127); the high bit of the byte (bit 7) is reserved for future use as an orientation flag if needed. Callers requesting a VFPU.s/.p/.t/.q operand bake the format into the mnemonic.

    wprint ¶
    Source

    wprint :: proc(
	w:            io.Stream, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    wprintln ¶
    Source

    wprintln :: proc(
	w:            io.Stream, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    write_u32 ¶
    Source

    write_u32 :: proc "contextless" (code: []u8, offset: u32, word: u32, endianness: Endianness) {…}

    Procedure Groups

    This section is empty.

    Source Files

    Generation Information

    Generated with odin version dev-2026-07 (vendor "odin") Windows_amd64 @ 2026-07-20 21:55:33.401587400 +0000 UTC