package core:rexcode/isa/mips

Source

CP0_Reg :: enum u8 {
	INDEX    = 0, 
	RANDOM   = 1, 
	ENTRYLO0 = 2, 
	ENTRYLO1 = 3, 
	CONTEXT  = 4, 
	PAGEMASK = 5, 
	WIRED    = 6, 
	HWRENA   = 7, 
	BADVADDR = 8, 
	COUNT    = 9, 
	ENTRYHI  = 10, 
	COMPARE  = 11, 
	STATUS   = 12, 
	CAUSE    = 13, 
	EPC      = 14, 
	PRID     = 15, 
	CONFIG   = 16, 
	LLADDR   = 17, 
	WATCHLO  = 18, 
	WATCHHI  = 19, 
	XCONTEXT = 20, 
	DEBUG    = 23, 
	DEPC     = 24, 
	PERFCNT  = 25, 
	ERRCTL   = 26, 
	CACHEERR = 27, 
	TAGLO    = 28, 
	TAGHI    = 29, 
	ERROREPC = 30, 
	DESAVE   = 31, 
}

Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	flags:    Encoding_Flags,
}

Decode_Index :: struct #packed {
	start: u16,
	count: u16,
}

Encode_Run :: struct {
	start: u32,
	count: u32,
}

Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	flags:    Encoding_Flags,
}

Encoding_Flags :: distinct bit_field u8 {
	delay_slot:  bool | 1,
	likely:      bool | 1,
	only_64:     bool | 1,
	writes_hilo: bool | 1,
	compact:     bool | 1,
	_:           u8 | 3,
}

Endianness :: enum u8 {
	LITTLE = 0, 
	BIG    = 1, 
}

Error :: rexcode_isa.Error

Error_Code :: rexcode_isa.Error_Code

FPR :: enum u8 {
	F0  = 0, 
	F1  = 1, 
	F2  = 2, 
	F3  = 3, 
	F4  = 4, 
	F5  = 5, 
	F6  = 6, 
	F7  = 7, 
	F8  = 8, 
	F9  = 9, 
	F10 = 10, 
	F11 = 11, 
	F12 = 12, 
	F13 = 13, 
	F14 = 14, 
	F15 = 15, 
	F16 = 16, 
	F17 = 17, 
	F18 = 18, 
	F19 = 19, 
	F20 = 20, 
	F21 = 21, 
	F22 = 22, 
	F23 = 23, 
	F24 = 24, 
	F25 = 25, 
	F26 = 26, 
	F27 = 27, 
	F28 = 28, 
	F29 = 29, 
	F30 = 30, 
	F31 = 31, 
}

Feature :: enum u8 {
	MIPS_I, 
	MIPS_II, 
	MIPS_III, 
	MIPS_IV, 
	MIPS_V, 
	MIPS32_R1, 
	MIPS32_R2, 
	MIPS32_R5, 
	MIPS32_R6, 
	MIPS64_R1, 
	MIPS64_R2, 
	MIPS64_R5, 
	MIPS64_R6, 
	COP0,      // system control coprocessor
	FPU,       // COP1 (any MIPS with FPU)
	DSP_R1, 
	DSP_R2, 
	MSA,       // MIPS SIMD
	GTE_PS1,   // PS1 R3000A Geometry Transformation Engine (COP2)
	MMI_PS2,   // PS2 R5900 Multimedia Instructions
	VU_PS2,    // PS2 VU0 macro-mode COP2 ops
	VFPU_PSP,  // PSP Allegrex Vector FPU
}

Feature_Set :: distinct bit_set[Feature; u32]

GPR :: enum u8 {
	ZERO = 0, 
	AT   = 1, 
	V0   = 2, 
	V1   = 3, 
	A0   = 4, 
	A1   = 5, 
	A2   = 6, 
	A3   = 7, 
	T0   = 8, 
	T1   = 9, 
	T2   = 10, 
	T3   = 11, 
	T4   = 12, 
	T5   = 13, 
	T6   = 14, 
	T7   = 15, 
	S0   = 16, 
	S1   = 17, 
	S2   = 18, 
	S3   = 19, 
	S4   = 20, 
	S5   = 21, 
	S6   = 22, 
	S7   = 23, 
	T8   = 24, 
	T9   = 25, 
	K0   = 26, 
	K1   = 27, 
	GP   = 28, 
	SP   = 29, 
	FP   = 30, 
	RA   = 31, 
}

GTE_CtrlReg :: enum u8 {
	R11R12 = 0, 
	R13R21 = 1, 
	R22R23 = 2, 
	R31R32 = 3, 
	R33    = 4, 
	TRX    = 5, 
	TRY    = 6, 
	TRZ    = 7, 
	L11L12 = 8, 
	L13L21 = 9, 
	L22L23 = 10, 
	L31L32 = 11, 
	L33    = 12, 
	RBK    = 13, 
	GBK    = 14, 
	BBK    = 15, 
	LR1LR2 = 16, 
	LR3LG1 = 17, 
	LG2LG3 = 18, 
	LB1LB2 = 19, 
	LB3    = 20, 
	RFC    = 21, 
	GFC    = 22, 
	BFC    = 23, 
	OFX    = 24, 
	OFY    = 25, 
	H      = 26, 
	DQA    = 27, 
	DQB    = 28, 
	ZSF3   = 29, 
	ZSF4   = 30, 
	FLAG   = 31, 
}

GTE_DataReg :: enum u8 {
	VXY0 = 0, 
	VZ0  = 1, 
	VXY1 = 2, 
	VZ1  = 3, 
	VXY2 = 4, 
	VZ2  = 5, 
	RGBC = 6, 
	OTZ  = 7, 
	IR0  = 8, 
	IR1  = 9, 
	IR2  = 10, 
	IR3  = 11, 
	SXY0 = 12, 
	SXY1 = 13, 
	SXY2 = 14, 
	SXYP = 15, 
	SZ0  = 16, 
	SZ1  = 17, 
	SZ2  = 18, 
	SZ3  = 19, 
	RGB0 = 20, 
	RGB1 = 21, 
	RGB2 = 22, 
	RES1 = 23, 
	MAC0 = 24, 
	MAC1 = 25, 
	MAC2 = 26, 
	MAC3 = 27, 
	IRGB = 28, 
	ORGB = 29, 
	LZCS = 30, 
	LZCR = 31, 
}

Instruction :: struct #packed {
	ops:           [4]Operand `fmt:"v,operand_count"`,
	// 64 bytes
	mnemonic:      Mnemonic,
	//  2 bytes
	operand_count: u8,
	//  1 byte
	flags:         Instruction_Flags,
	//  1 byte
	length:        u8,
	//  1 byte — always 4 for now; will be 2 for future μMIPS / MIPS16e
	_:             [3]u8,
}

Instruction_Flags :: distinct bit_field u8 {
	_: u8 | 8,
}

Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}

Label_Definition :: rexcode_isa.Label_Definition

Label_Map :: rexcode_isa.Label_Map

Label_Names :: map[rexcode_isa.Label_Offset]string

Label_Offset :: rexcode_isa.Label_Offset

Memory :: struct #packed {
	base: Register,
	// 2 bytes
	_:    u16,
	// 2 bytes pad (keeps the struct power-of-two)
	disp: i32,
}

Mnemonic :: enum u16 {
	INVALID         = 0, 
	// R-type arithmetic
	ADD, 
	ADDU, 
	SUB, 
	SUBU, 
	MULT, 
	MULTU, 
	DIV, 
	DIVU, 
	MFHI, 
	MFLO, 
	MTHI, 
	MTLO, 
	AND, 
	OR, 
	XOR, 
	NOR, 
	SLT, 
	SLTU, 
	// R-type shifts
	SLL, 
	SRL, 
	SRA, 
	SLLV, 
	SRLV, 
	SRAV, 
	// I-type arithmetic
	ADDI, 
	ADDIU, 
	SLTI, 
	SLTIU, 
	ANDI, 
	ORI, 
	XORI, 
	LUI, 
	// I-type branches
	BEQ, 
	BNE, 
	BLEZ, 
	BGTZ, 
	// REGIMM branches
	BLTZ, 
	BGEZ, 
	BLTZAL, 
	BGEZAL, 
	// J-type
	J, 
	JAL, 
	// R-type jumps
	JR, 
	JALR, 
	// Loads
	LB, 
	LH, 
	LW, 
	LBU, 
	LHU, 
	LWL, 
	LWR, 
	// Stores
	SB, 
	SH, 
	SW, 
	SWL, 
	SWR, 
	// System
	SYSCALL, 
	BREAK, 
	NOP, 
	// Atomic
	LL, 
	SC, 
	// Synchronization
	SYNC, 
	// Traps (immediate and register variants)
	TGEI, 
	TGEIU, 
	TLTI, 
	TLTIU, 
	TEQI, 
	TNEI, 
	TGE, 
	TGEU, 
	TLT, 
	TLTU, 
	TEQ, 
	TNE, 
	// Branch-likely (skip delay slot if not taken)
	BEQL, 
	BNEL, 
	BLEZL, 
	BGTZL, 
	BLTZL, 
	BGEZL, 
	BLTZALL, 
	BGEZALL, 
	DADD, 
	DADDU, 
	DSUB, 
	DSUBU, 
	DADDI, 
	DADDIU, 
	DMULT, 
	DMULTU, 
	DDIV, 
	DDIVU, 
	DSLL, 
	DSRL, 
	DSRA, 
	DSLLV, 
	DSRLV, 
	DSRAV, 
	DSLL32, 
	DSRL32, 
	DSRA32, 
	LD, 
	LDL, 
	LDR, 
	LWU, 
	SD, 
	SDL, 
	SDR, 
	LLD, 
	SCD, 
	MOVN, 
	MOVZ, 
	MOVF, 
	MOVT,                // FP-condition-based GPR move
	PREF, 
	PREFX, 
	LWXC1, 
	SWXC1, 
	LDXC1, 
	SDXC1,               // indexed FP load/store
	CLZ, 
	CLO, 
	DCLZ, 
	DCLO, 
	MUL,                 // SPECIAL2 multiply-to-rd (doesn't touch HI/LO)
	MADD, 
	MADDU, 
	MSUB, 
	MSUBU, 
	SDBBP, 
	SSNOP, 
	EHB, 
	PAUSE, 
	// R2 bitfield + shuffle
	EXT, 
	INS, 
	DEXT, 
	DEXTM, 
	DEXTU, 
	DINS, 
	DINSM, 
	DINSU, 
	ROTR, 
	ROTRV, 
	DROTR, 
	DROTRV, 
	DROTR32, 
	WSBH, 
	DSBH, 
	DSHD, 
	SEB, 
	SEH, 
	// R2 misc
	RDHWR, 
	RDPGPR, 
	WRPGPR, 
	DI, 
	EI, 
	ERET, 
	DERET, 
	WAIT, 
	// Compact (no delay slot)
	BC, 
	BALC,                // 26-bit
	BEQC, 
	BNEC, 
	BLTC, 
	BGEC, 
	BLTUC, 
	BGEUC, 
	BLEZC, 
	BGEZC, 
	BGTZC, 
	BLTZC, 
	BEQZC, 
	BNEZC, 
	BC1EQZ, 
	BC1NEZ, 
	BC2EQZ, 
	BC2NEZ, 
	JIC, 
	JIALC, 
	// R6 mul/div (replaces MULT/MULTU/DIV/DIVU; results in single GPR)
	MUH, 
	MULU, 
	MUHU, 
	MOD, 
	MODU, 
	DMUL, 
	DMUH, 
	DMULU, 
	DMUHU, 
	DMOD, 
	DMODU, 
	// R6 PC-relative immediates
	AUI, 
	AUIPC, 
	ALUIPC, 
	DAUI, 
	DAHI, 
	DATI, 
	// R6 misc
	ALIGN, 
	DALIGN, 
	BITSWAP, 
	DBITSWAP, 
	LSA, 
	DLSA, 
	LWPC, 
	LWUPC, 
	LDPC, 
	SELEQZ, 
	SELNEZ, 
	// R6 CRC32 (optional in MIPS32 R6)
	CRC32B, 
	CRC32H, 
	CRC32W, 
	CRC32D, 
	CRC32CB, 
	CRC32CH, 
	CRC32CW, 
	CRC32CD, 
	SIGRIE,              // signal reserved instruction exception
	MFC1, 
	MTC1, 
	DMFC1, 
	DMTC1, 
	CFC1, 
	CTC1, 
	MFHC1, 
	MTHC1,               // R2: high word of paired single
	LWC1, 
	SWC1, 
	LDC1, 
	SDC1, 
	ADD_S, 
	ADD_D, 
	ADD_PS, 
	SUB_S, 
	SUB_D, 
	SUB_PS, 
	MUL_S, 
	MUL_D, 
	MUL_PS, 
	DIV_S, 
	DIV_D, 
	SQRT_S, 
	SQRT_D, 
	ABS_S, 
	ABS_D, 
	ABS_PS, 
	NEG_S, 
	NEG_D, 
	NEG_PS, 
	MOV_S, 
	MOV_D, 
	MOV_PS, 
	RECIP_S, 
	RECIP_D, 
	RSQRT_S, 
	RSQRT_D, 
	// FMA family (MIPS IV+)
	MADD_S, 
	MADD_D, 
	MADD_PS, 
	MSUB_S, 
	MSUB_D, 
	MSUB_PS, 
	NMADD_S, 
	NMADD_D, 
	NMADD_PS, 
	NMSUB_S, 
	NMSUB_D, 
	NMSUB_PS, 
	// Conditional move (FPR by GPR / FCC)
	MOVN_S, 
	MOVN_D, 
	MOVN_PS, 
	MOVZ_S, 
	MOVZ_D, 
	MOVZ_PS, 
	MOVF_S, 
	MOVF_D, 
	MOVF_PS, 
	MOVT_S, 
	MOVT_D, 
	MOVT_PS, 
	CVT_S_D, 
	CVT_S_W, 
	CVT_S_L, 
	CVT_D_S, 
	CVT_D_W, 
	CVT_D_L, 
	CVT_W_S, 
	CVT_W_D, 
	CVT_L_S, 
	CVT_L_D, 
	CVT_PS_S, 
	CVT_S_PU, 
	CVT_S_PL, 
	PLL_PS, 
	PLU_PS, 
	PUL_PS, 
	PUU_PS, 
	// FPU round-to-fixed-point
	ROUND_W_S, 
	ROUND_W_D, 
	ROUND_L_S, 
	ROUND_L_D, 
	TRUNC_W_S, 
	TRUNC_W_D, 
	TRUNC_L_S, 
	TRUNC_L_D, 
	CEIL_W_S, 
	CEIL_W_D, 
	CEIL_L_S, 
	CEIL_L_D, 
	FLOOR_W_S, 
	FLOOR_W_D, 
	FLOOR_L_S, 
	FLOOR_L_D, 
	C_F_S, 
	C_F_D, 
	C_F_PS, 
	C_UN_S, 
	C_UN_D, 
	C_UN_PS, 
	C_EQ_S, 
	C_EQ_D, 
	C_EQ_PS, 
	C_UEQ_S, 
	C_UEQ_D, 
	C_UEQ_PS, 
	C_OLT_S, 
	C_OLT_D, 
	C_OLT_PS, 
	C_ULT_S, 
	C_ULT_D, 
	C_ULT_PS, 
	C_OLE_S, 
	C_OLE_D, 
	C_OLE_PS, 
	C_ULE_S, 
	C_ULE_D, 
	C_ULE_PS, 
	C_SF_S, 
	C_SF_D, 
	C_SF_PS, 
	C_NGLE_S, 
	C_NGLE_D, 
	C_NGLE_PS, 
	C_SEQ_S, 
	C_SEQ_D, 
	C_SEQ_PS, 
	C_NGL_S, 
	C_NGL_D, 
	C_NGL_PS, 
	C_LT_S, 
	C_LT_D, 
	C_LT_PS, 
	C_NGE_S, 
	C_NGE_D, 
	C_NGE_PS, 
	C_LE_S, 
	C_LE_D, 
	C_LE_PS, 
	C_NGT_S, 
	C_NGT_D, 
	C_NGT_PS, 
	// FPU branches
	BC1F, 
	BC1T, 
	BC1FL, 
	BC1TL, 
	MFC0, 
	MTC0, 
	DMFC0, 
	DMTC0, 
	MFHC0, 
	MTHC0,               // R5+ high half of 64-bit registers
	TLBP, 
	TLBR, 
	TLBWI, 
	TLBWR, 
	CACHE, 
	// Standard COP2 moves (GTE registers via these)
	MFC2, 
	MTC2, 
	CFC2, 
	CTC2, 
	LWC2, 
	SWC2, 
	LDC2, 
	SDC2,                // LDC2/SDC2 exist on MIPS II+; PS1 R3000A does not implement
	// GTE ops (cofun-encoded, no GPR operands)
	RTPS, 
	RTPT, 
	DPCS, 
	DPCT, 
	INTPL, 
	MVMVA, 
	NCDS, 
	NCDT, 
	NCCS, 
	NCCT, 
	NCS, 
	NCT, 
	CDP, 
	CC, 
	NCLIP, 
	AVSZ3, 
	AVSZ4, 
	OP,                  // "OP" (cross product) — disambiguated from MIPS R6 OP
	GPF, 
	GPL, 
	SQR,                 // "SQR" — disambiguated from generic
	DCPL,                // depth-cue per light
	// 128-bit GPR load/store
	LQ, 
	SQ, 
	// VU0 macro-mode 128-bit COP2 moves
	LQC2, 
	SQC2, 
	// Second HI/LO pair (R5900 dual MAC)
	MFHI1, 
	MFLO1, 
	MTHI1, 
	MTLO1, 
	MULT1, 
	MULTU1, 
	DIV1, 
	DIVU1, 
	MADD1, 
	MADDU1, 
	MSUB1, 
	MSUBU1, 
	// Packed pack/unpack HI:LO
	PMFHL_LW, 
	PMFHL_UW, 
	PMFHL_LH, 
	PMFHL_SH, 
	PMFHL_SLW, 
	PMTHL_LW, 
	// Parallel arithmetic (byte/halfword/word lanes)
	PADDB, 
	PADDH, 
	PADDW, 
	PADDSB, 
	PADDSH, 
	PADDSW, 
	PADDUB, 
	PADDUH, 
	PADDUW, 
	PSUBB, 
	PSUBH, 
	PSUBW, 
	PSUBSB, 
	PSUBSH, 
	PSUBSW, 
	PSUBUB, 
	PSUBUH, 
	PSUBUW, 
	// Parallel shifts
	PSLLH, 
	PSRLH, 
	PSRAH, 
	PSLLW, 
	PSRLW, 
	PSRAW, 
	PSLLVW, 
	PSRLVW, 
	PSRAVW, 
	QFSRV,               // quad funnel shift right (across 128 bits)
	// Parallel logical
	PAND, 
	POR, 
	PXOR, 
	PNOR, 
	// Parallel compare
	PCEQB, 
	PCEQH, 
	PCEQW, 
	PCGTB, 
	PCGTH, 
	PCGTW, 
	// Parallel multiply / divide
	PMULTW, 
	PMULTUW, 
	PMULTH, 
	PMADDW, 
	PMADDUW, 
	PMADDH, 
	PMSUBW, 
	PMSUBH, 
	PHMADH, 
	PHMSBH, 
	PDIVW, 
	PDIVUW, 
	PDIVBW, 
	// Pack / rearrange
	PCPYLD, 
	PCPYUD, 
	PCPYH, 
	PINTH, 
	PINTOH, 
	PEXEH, 
	PEXEW, 
	PEXCH, 
	PEXCW, 
	PROT3W, 
	PPACB, 
	PPACH, 
	PPACW, 
	PPAC5, 
	PEXT5, 
	PEXTLB, 
	PEXTLH, 
	PEXTLW, 
	PEXTUB, 
	PEXTUH, 
	PEXTUW, 
	// MMI HI/LO helpers
	PMFHI, 
	PMFLO, 
	PMTHI, 
	PMTLO, 
	// Misc MMI
	PLZCW, 
	PABSH, 
	PABSW, 
	PMAXH, 
	PMAXW, 
	PMINH, 
	PMINW, 
	// Shift-amount register
	MFSA, 
	MTSA, 
	MTSAB, 
	MTSAH, 
	// Packed add/sub (saturating)
	ADDQ_PH, 
	ADDQ_S_PH, 
	ADDQ_S_W, 
	SUBQ_PH, 
	SUBQ_S_PH, 
	SUBQ_S_W, 
	ADDU_QB, 
	ADDU_S_QB, 
	ADDU_PH, 
	ADDU_S_PH, 
	SUBU_QB, 
	SUBU_S_QB, 
	SUBU_PH, 
	SUBU_S_PH, 
	ADDSC, 
	ADDWC,               // 32-bit + carry/borrow
	// Packed multiply / dot-product / accumulate
	MULEU_S_PH_QBL, 
	MULEU_S_PH_QBR, 
	MULEQ_S_W_PHL, 
	MULEQ_S_W_PHR, 
	MULQ_RS_PH, 
	MULQ_S_PH, 
	MULSAQ_S_W_PH, 
	DPAQ_S_W_PH, 
	DPSQ_S_W_PH, 
	DPAQ_SA_L_W, 
	DPSQ_SA_L_W, 
	DPAU_H_QBL, 
	DPAU_H_QBR, 
	DPSU_H_QBL, 
	DPSU_H_QBR, 
	DPA_W_PH, 
	DPS_W_PH,            // R2
	DPAX_W_PH, 
	DPSX_W_PH,           // R2
	MAQ_S_W_PHL, 
	MAQ_S_W_PHR, 
	MAQ_SA_W_PHL, 
	MAQ_SA_W_PHR, 
	// Extract / position / accumulator helpers
	EXTR_W, 
	EXTR_R_W, 
	EXTR_RS_W, 
	EXTR_S_H, 
	EXTRV_W, 
	EXTRV_R_W, 
	EXTRV_RS_W, 
	EXTRV_S_H, 
	EXTP, 
	EXTPV, 
	EXTPDP, 
	EXTPDPV, 
	SHILO, 
	SHILOV, 
	MTHLIP, 
	WRDSP, 
	RDDSP, 
	// Pack / unpack
	PRECRQ_QB_PH, 
	PRECRQ_PH_W, 
	PRECRQU_S_QB_PH, 
	PRECEQ_W_PHL, 
	PRECEQ_W_PHR, 
	PRECEQU_PH_QBL, 
	PRECEQU_PH_QBR, 
	PRECEQU_PH_QBLA, 
	PRECEQU_PH_QBRA, 
	PRECEU_PH_QBL, 
	PRECEU_PH_QBR, 
	PRECEU_PH_QBLA, 
	PRECEU_PH_QBRA, 
	PRECRQ_RS_PH_W, 
	// Compare / pick
	CMPU_EQ_QB, 
	CMPU_LT_QB, 
	CMPU_LE_QB, 
	CMP_EQ_PH, 
	CMP_LT_PH, 
	CMP_LE_PH, 
	CMPGU_EQ_QB, 
	CMPGU_LT_QB, 
	CMPGU_LE_QB, 
	PICK_QB, 
	PICK_PH, 
	// Shift
	SHLL_QB, 
	SHLL_PH, 
	SHLL_S_PH, 
	SHLL_S_W, 
	SHLLV_QB, 
	SHLLV_PH, 
	SHLLV_S_PH, 
	SHLLV_S_W, 
	SHRL_QB, 
	SHRL_PH, 
	SHRLV_QB, 
	SHRLV_PH, 
	SHRA_QB, 
	SHRA_R_QB, 
	SHRA_PH, 
	SHRA_R_PH, 
	SHRA_R_W, 
	SHRAV_QB, 
	SHRAV_R_QB, 
	SHRAV_PH, 
	SHRAV_R_PH, 
	SHRAV_R_W, 
	// Indexed loads (rs+rt addressing) — register-register addressing.
	LBUX, 
	LHX, 
	LWX, 
	// DSP control / branch
	BPOSGE32,            // branch if DSPControl.pos >= 32
	INSV,                // insert variable position
	BITREV,              // R2 bit reversal
	ABSQ_S_PH, 
	ABSQ_S_W, 
	REPL_PH, 
	REPLV_PH, 
	REPL_QB, 
	REPLV_QB, 
	// Vector register-register integer arithmetic (.B/.H/.W/.D lane width)
	ADDV_B, 
	ADDV_H, 
	ADDV_W, 
	ADDV_D, 
	SUBV_B, 
	SUBV_H, 
	SUBV_W, 
	SUBV_D, 
	ADDS_S_B, 
	ADDS_S_H, 
	ADDS_S_W, 
	ADDS_S_D, 
	ADDS_U_B, 
	ADDS_U_H, 
	ADDS_U_W, 
	ADDS_U_D, 
	SUBS_S_B, 
	SUBS_S_H, 
	SUBS_S_W, 
	SUBS_S_D, 
	SUBS_U_B, 
	SUBS_U_H, 
	SUBS_U_W, 
	SUBS_U_D, 
	MULV_B, 
	MULV_H, 
	MULV_W, 
	MULV_D, 
	DIV_S_B, 
	DIV_S_H, 
	DIV_S_W, 
	DIV_S_D, 
	DIV_U_B, 
	DIV_U_H, 
	DIV_U_W, 
	DIV_U_D, 
	MOD_S_B, 
	MOD_S_H, 
	MOD_S_W, 
	MOD_S_D, 
	MOD_U_B, 
	MOD_U_H, 
	MOD_U_W, 
	MOD_U_D, 
	MADDV_B, 
	MADDV_H, 
	MADDV_W, 
	MADDV_D, 
	MSUBV_B, 
	MSUBV_H, 
	MSUBV_W, 
	MSUBV_D, 
	DOTP_S_H, 
	DOTP_S_W, 
	DOTP_S_D, 
	DOTP_U_H, 
	DOTP_U_W, 
	DOTP_U_D, 
	// Vector logical
	AND_V, 
	OR_V, 
	NOR_V, 
	XOR_V, 
	ANDI_B, 
	ORI_B, 
	NORI_B, 
	XORI_B, 
	BSEL_V, 
	BSELI_B, 
	BMNZ_V, 
	BMNZI_B, 
	BMZ_V, 
	BMZI_B, 
	// Vector compare
	CEQ_B, 
	CEQ_H, 
	CEQ_W, 
	CEQ_D, 
	CLT_S_B, 
	CLT_S_H, 
	CLT_S_W, 
	CLT_S_D, 
	CLT_U_B, 
	CLT_U_H, 
	CLT_U_W, 
	CLT_U_D, 
	CLE_S_B, 
	CLE_S_H, 
	CLE_S_W, 
	CLE_S_D, 
	CLE_U_B, 
	CLE_U_H, 
	CLE_U_W, 
	CLE_U_D, 
	// Vector min/max
	MIN_S_B, 
	MIN_S_H, 
	MIN_S_W, 
	MIN_S_D, 
	MIN_U_B, 
	MIN_U_H, 
	MIN_U_W, 
	MIN_U_D, 
	MAX_S_B, 
	MAX_S_H, 
	MAX_S_W, 
	MAX_S_D, 
	MAX_U_B, 
	MAX_U_H, 
	MAX_U_W, 
	MAX_U_D, 
	// Vector shifts
	SLL_B, 
	SLL_H, 
	SLL_W, 
	SLL_D, 
	SRL_B, 
	SRL_H, 
	SRL_W, 
	SRL_D, 
	SRA_B, 
	SRA_H, 
	SRA_W, 
	SRA_D, 
	SLLI_B, 
	SLLI_H, 
	SLLI_W, 
	SLLI_D, 
	SRLI_B, 
	SRLI_H, 
	SRLI_W, 
	SRLI_D, 
	SRAI_B, 
	SRAI_H, 
	SRAI_W, 
	SRAI_D, 
	// Vector FP arithmetic
	FADD_W, 
	FADD_D, 
	FSUB_W, 
	FSUB_D, 
	FMUL_W, 
	FMUL_D, 
	FDIV_W, 
	FDIV_D, 
	FSQRT_W, 
	FSQRT_D, 
	FRSQRT_W, 
	FRSQRT_D, 
	FRCP_W, 
	FRCP_D, 
	FRINT_W, 
	FRINT_D, 
	FMAX_W, 
	FMAX_D, 
	FMIN_W, 
	FMIN_D, 
	FCEQ_W, 
	FCEQ_D, 
	FCNE_W, 
	FCNE_D, 
	FCLT_W, 
	FCLT_D, 
	FCLE_W, 
	FCLE_D, 
	// Vector conversion
	FFINT_S_W, 
	FFINT_S_D, 
	FFINT_U_W, 
	FFINT_U_D, 
	FTRUNC_S_W, 
	FTRUNC_S_D, 
	FTRUNC_U_W, 
	FTRUNC_U_D, 
	FCVT_S_W, 
	FCVT_S_D, 
	FCVT_D_W, 
	// Vector load/store + immediate
	LD_B, 
	LD_H, 
	LD_W, 
	LD_D, 
	ST_B, 
	ST_H, 
	ST_W, 
	ST_D, 
	LDI_B, 
	LDI_H, 
	LDI_W, 
	LDI_D, 
	// Vector shuffle / copy / insert
	COPY_S_B, 
	COPY_S_H, 
	COPY_S_W, 
	COPY_U_B, 
	COPY_U_H, 
	COPY_U_W, 
	INSERT_B, 
	INSERT_H, 
	INSERT_W, 
	INSERT_D, 
	INSVE_B, 
	INSVE_H, 
	INSVE_W, 
	INSVE_D, 
	SHF_B, 
	SHF_H, 
	SHF_W, 
	VSHF_B, 
	VSHF_H, 
	VSHF_W, 
	VSHF_D, 
	SLD_B, 
	SLD_H, 
	SLD_W, 
	SLD_D, 
	SLDI_B, 
	SLDI_H, 
	SLDI_W, 
	SLDI_D, 
	SPLAT_B, 
	SPLAT_H, 
	SPLAT_W, 
	SPLAT_D, 
	SPLATI_B, 
	SPLATI_H, 
	SPLATI_W, 
	SPLATI_D, 
	// MSA branches (vector all-zero / any-non-zero across all lanes / per-lane)
	BZ_V, 
	BNZ_V, 
	BZ_B, 
	BZ_H, 
	BZ_W, 
	BZ_D, 
	BNZ_B, 
	BNZ_H, 
	BNZ_W, 
	BNZ_D, 
	// Element-permute / count / bit-ops
	NLOC_B, 
	NLOC_H, 
	NLOC_W, 
	NLOC_D, 
	NLZC_B, 
	NLZC_H, 
	NLZC_W, 
	NLZC_D, 
	PCNT_B, 
	PCNT_H, 
	PCNT_W, 
	PCNT_D, 
	// Move / load / store / immediates
	VMOV_S, 
	VMOV_P, 
	VMOV_T, 
	VMOV_Q, 
	LV_S, 
	LV_Q, 
	SV_S, 
	SV_Q, 
	LVL_Q, 
	LVR_Q, 
	SVL_Q, 
	SVR_Q, 
	VIIM_S, 
	VFIM_S, 
	// Arithmetic
	VADD_S, 
	VADD_P, 
	VADD_T, 
	VADD_Q, 
	VSUB_S, 
	VSUB_P, 
	VSUB_T, 
	VSUB_Q, 
	VMUL_S, 
	VMUL_P, 
	VMUL_T, 
	VMUL_Q, 
	VDIV_S, 
	VDIV_P, 
	VDIV_T, 
	VDIV_Q, 
	VABS_S, 
	VABS_P, 
	VABS_T, 
	VABS_Q, 
	VNEG_S, 
	VNEG_P, 
	VNEG_T, 
	VNEG_Q, 
	VSQRT_S, 
	VRCP_S, 
	VRCP_P, 
	VRCP_T, 
	VRCP_Q, 
	VRSQ_S, 
	VRSQ_P, 
	VRSQ_T, 
	VRSQ_Q, 
	// Reductions / dot / scale
	VDOT_P, 
	VDOT_T, 
	VDOT_Q, 
	VSCL_P, 
	VSCL_T, 
	VSCL_Q, 
	VHDP_P, 
	VHDP_T, 
	VHDP_Q, 
	VAVG_P, 
	VAVG_T, 
	VAVG_Q, 
	VFAD_P, 
	VFAD_T, 
	VFAD_Q, 
	// Matrix ops
	VMMUL_P, 
	VMMUL_T, 
	VMMUL_Q, 
	VTFM2_P, 
	VTFM3_T, 
	VTFM4_Q, 
	VHTFM2_P, 
	VHTFM3_T, 
	VHTFM4_Q, 
	VMSCL_P, 
	VMSCL_T, 
	VMSCL_Q, 
	VMMOV_P, 
	VMMOV_T, 
	VMMOV_Q, 
	VMIDT_P, 
	VMIDT_T, 
	VMIDT_Q, 
	VMZERO_P, 
	VMZERO_T, 
	VMZERO_Q, 
	VMONE_P, 
	VMONE_T, 
	VMONE_Q, 
	// Cross / quaternion
	VCRS_T, 
	VCRSP_T, 
	VQMUL_Q, 
	// Compares & sel
	VCMP_S, 
	VCMP_P, 
	VCMP_T, 
	VCMP_Q, 
	VMIN_S, 
	VMIN_P, 
	VMIN_T, 
	VMIN_Q, 
	VMAX_S, 
	VMAX_P, 
	VMAX_T, 
	VMAX_Q, 
	// Transcendentals
	VSIN_S, 
	VCOS_S, 
	VEXP2_S, 
	VLOG2_S, 
	VASIN_S, 
	VNRCP_S, 
	VNSIN_S, 
	VREXP2_S, 
	VSGN_S, 
	// Conversion
	VI2F_S, 
	VI2F_P, 
	VI2F_T, 
	VI2F_Q, 
	VF2IN_S, 
	VF2IN_P, 
	VF2IN_T, 
	VF2IN_Q, 
	VF2IZ_S, 
	VF2IZ_P, 
	VF2IZ_T, 
	VF2IZ_Q, 
	VF2IU_S, 
	VF2IU_P, 
	VF2IU_T, 
	VF2IU_Q, 
	VF2ID_S, 
	VF2ID_P, 
	VF2ID_T, 
	VF2ID_Q, 
	VF2H_P, 
	VH2F_S, 
	// Control / move-between
	VFLUSH, 
	VSYNC, 
	VNOP, 
	VPFXS, 
	VPFXT, 
	VPFXD, 
	VCST_S, 
	VCST_P, 
	VCST_T, 
	VCST_Q, 
	MFV, 
	MTV, 
	MFVC, 
	MTVC, 
	BVF, 
	BVT, 
	BVFL, 
	BVTL, 
}

Operand :: struct #packed {
	using _: struct #raw_union {
		reg:       Register,
		// 2 bytes
		mem:       Memory,
		// 8 bytes
		immediate: i64,
		// 8 bytes
		relative:  i64,
	},
	kind: Operand_Kind,
	// 1 byte
	size: u8,
}

Operand_Encoding :: enum u8 {
	NONE, 
	// Standard MIPS field placements (R/I-type)
	RS,                // bits 25-21
	RT,                // bits 20-16
	RD,                // bits 15-11
	SHAMT,             // bits 10-6
	// FP register placements (FR-format; overlap RS/RT/RD/SHAMT positions)
	FT,                // bits 20-16
	FS,                // bits 15-11
	FD,                // bits 10-6
	// Immediates
	IMM_16,            // bits 15-0
	IMM_5,             // bits 10-6 (same slot as SHAMT)
	IMM_20,            // bits 25-6 (SYSCALL/BREAK code)
	IMM_26,            // bits 25-0 (J-type target word)
	// Memory: implicit RS + IMM_16
	OFFSET_BASE, 
	// PC-relative
	BRANCH_16,         // bits 15-0 as PC-relative word offset (delay-slot adjusted)
	BRANCH_21,         // R6 compact branch: bits 20-0
	BRANCH_26,         // R6 compact branch: bits 25-0
	BRANCH_19,         // R6 PC-relative load: bits 18-0 (LWPC/LWUPC)
	BRANCH_18,         // R6 PC-relative load: bits 17-0 (LDPC)
	// FP condition code
	FCC_BC,            // bits 20-18 (FP branches, MOVF/MOVT)
	FCC_CC,            // bits 10-8 (C.cond compare results)
	// CP0 selector
	SEL,               // bits 2-0
	// Implicit (operand exists in the asm syntax but is not encoded;
	// e.g. $zero in branch-likely synthetic forms).
	IMPL, 
	// GTE cofun selectors (bit positions within the 25-bit cofun field)
	GTE_SF_BIT,        // bit 19
	GTE_MX_BITS,       // bits 18-17
	GTE_V_BITS,        // bits 16-15
	GTE_CV_BITS,       // bits 14-13
	GTE_LM_BIT,        // bit 10
	// ---- PSP VFPU register slots ------------------------------------------
	// 
	// VFPU registers use 7-bit IDs (0..127). The standard 3-operand layout:
	//   bits 22:16 = vt   (7-bit register ID)
	//   bits 14:8  = vs   (7-bit register ID)
	//   bits  6:0  = vd   (7-bit register ID)
	// The width-modifier bits (bit 15 + bit 7) are NOT operand-driven --
	// they're baked into the form's static `bits` per the .s/.p/.t/.q
	// mnemonic suffix, so:
	//   .s = bit15=0, bit7=0
	//   .p = bit15=0, bit7=1
	//   .t = bit15=1, bit7=0
	//   .q = bit15=1, bit7=1
	VFPU_VD, 
	VFPU_VS, 
	VFPU_VT, 
	// VFPU register for memory ops where the 7-bit ID is SPLIT:
	//   bits 20:16 = vt[6:2]   (top 5 bits at the rt position)
	//   bits  1:0  = vt[1:0]   (bottom 2 bits at the very low position)
	// Used by LV.S / SV.S / LV.Q / SV.Q.
	VFPU_VT_MEM, 
	// VFPU SP-style memory operand: base GPR at bits 25:21 + signed-16
	// displacement at bits 15:2 (low 2 bits forced 0 = multiple of 4 for S,
	// multiple of 16 for Q -- user responsible for alignment).
	VFPU_OFFSET_BASE, 
	// VFPU prefix immediate: 20-bit prefix mask at bits 19:0 (VPFXS/T/D).
	VFPU_PFX, 
	// VFPU constant selector / 5-bit immediate at bits 20:16 (VCST, VF2I*).
	VFPU_CONST, 
	// VFPU 4-bit condition code at bits 3:0 (VCMP).
	VFPU_COND4, 
	// VFPU 3-bit VCC selector at bits 18:16 (BVF / BVT / BVFL / BVTL).
	VFPU_CC3, 
	// MSA 3R-format register slots:
	//   wd at bits 10:6 (alias of RD/SHAMT bit positions)
	//   ws at bits 15:11 (alias of RD)
	//   wt at bits 20:16 (alias of RT)
	WD, 
	WS, 
	WT, 
	// MSA element-index / immediate fields used by some forms (ELM/I5/BIT)
	MSA_I5,            // 5-bit immediate at bits 20:16 (LDI/I5 forms)
	MSA_S10,           // signed 10-bit displacement at bits 25:16 (MI10 load/store)
	MSA_BIT5,          // bit position (5-bit) at bits 16:11 (BIT form)
	// The shift amount / element index sits at bits 22:16 / 21:16 with the data
	// format encoded by the high (marker) bits; the operand drives the low bits
	// (the marker is fixed in the entry `bits`). Decode infers df from the marker.
	MSA_BIT_SHIFT,     // BIT-format shift amount (.B m=0x70|sh, .H 0x60|sh, .W 0x40|sh, .D sh)
	MSA_ELM_IDX,       // ELM-format element index (.B n, .H 0x20|n, .W 0x30|n, .D 0x38|n)
	MSA_I8,            // 8-bit immediate at bits 23:16 (I8 forms: ANDI.B/SHF/...)
	FR,                // FP register at bits 25:21 (COP1X 4-register FMA: fr)
	GPR_AT_6,          // GPR at bits 10:6 (MSA COPY destination)
	GPR_AT_11,         // GPR at bits 15:11 (MSA INSERT source)
	DSP_SA,            // DSP shift amount at bits 24:21 (.PH 4-bit, .QB 3-bit)
	RS_RT,             // same GPR in both rs (25:21) and rt (20:16) (R6 BGEZC/BLTZC)
	AC_NUM,            // DSP accumulator number ac0..ac3 at bits 12:11 (immediate)
	SHILO_IMM,         // DSP SHILO signed 6-bit shift at bits 25:20
	EXT_SIZE,          // DSP EXTPDP extract size, 5-bit immediate at bits 25:21
	// MSA memory operand: base GPR at bits 15:11 + signed 10-bit disp at 25:16,
	// scaled by element size (1/2/4/8 for B/H/W/D).
	MSA_OFFSET_BASE_B, 
	MSA_OFFSET_BASE_H, 
	MSA_OFFSET_BASE_W, 
	MSA_OFFSET_BASE_D, 
}

Operand_Kind :: enum u8 {
	NONE, 
	REGISTER, 
	MEMORY, 
	IMMEDIATE, 
	RELATIVE,  // PC-relative target (label or raw offset)
}

Operand_Type :: enum u8 {
	NONE, 
	// Integer registers
	GPR, 
	GPR_ZERO, // implicit $zero (rare; for disambiguation)
	// FP register, format-tagged
	FPR_S, 
	FPR_D, 
	FPR_W, 
	FPR_L, 
	FPR_PS, 
	FCR,      // FP control reg ($fcr0/$fccr/$fexr/$fenr/$fcsr)
	// Coprocessor registers
	CP0_REG,  // CP0 register (0-31), with optional sel
	CP2_REG,  // COP2 data register (GTE V*/MAC*/SXY*; VU vf*)
	CP2_CTRL, // COP2 control register
	// VFPU registers (PSP) — single, pair, triple, quad
	VFPU_S, 
	VFPU_P, 
	VFPU_T, 
	VFPU_Q, 
	VFPU_M_P, 
	VFPU_M_T, 
	VFPU_M_Q, // matrix forms
	// MSA vector register (W0..W31). Format suffix (.B/.H/.W/.D) is baked
	// into the mnemonic, so a single operand-type is enough at match time.
	MSA_VEC, 
	// Immediates
	IMM5,     // 5-bit shift amount or small literal
	IMM16S,   // signed 16-bit
	IMM16U,   // unsigned (zero-extended) 16-bit
	IMM20,    // 20-bit SYSCALL/BREAK/SDBBP code
	IMM26,    // 26-bit J-type target word
	SEL,      // CP0 selector (3 bits, R2+)
	// PC-relative branch targets
	REL16,    // 16-bit signed offset (<<2), I-type branches
	REL_J26,  // 26-bit region jump (J / JAL)
	REL21,    // R6 21-bit compact branch (BC1EQZ/NEZ)
	REL26,    // R6 26-bit compact branch (BC/BALC)
	REL19,    // R6 PC-relative load (LWPC/LWUPC, 19-bit << 2)
	REL18,    // R6 PC-relative load (LDPC, 18-bit << 3)
	// Memory: base GPR + 16-bit signed displacement
	MEM, 
	// Condition codes / cofun selectors
	FCC,      // FP condition-code field (3 bits)
	// GTE-specific cofun selectors (the few that are user-visible)
	GTE_SF, 
	GTE_MX, 
	GTE_V, 
	GTE_CV, 
	GTE_LM, 
}

Print_Options :: rexcode_isa.Print_Options

Print_Result :: rexcode_isa.Print_Result

Register :: distinct u16

Relocation :: struct #packed {
	offset:   u32,
	label_id: u32,
	addend:   i32,
	type:     Relocation_Type,
	size:     u8,
	inst_idx: u16,
}

Relocation_Type :: enum u8 {
	NONE     = 0, 
	REL16,        // 16-bit signed PC-rel branch offset (BEQ/BNE/BLEZ/BGTZ/...)
	REL21,        // 21-bit signed PC-rel compact branch (R6 BEQZC/BNEZC)
	REL26,        // 26-bit signed PC-rel compact branch (R6 BC/BALC)
	REL_PC19,     // 19-bit R6 PC-relative load offset ((target - PC) >> 2)  (LWPC/LWUPC)
	REL_PC18,     // 18-bit R6 PC-relative load offset ((target - (PC & ~7)) >> 3)  (LDPC)
	J26,          // 26-bit J-type region target ((target_addr >> 2) & 0x3FFFFFF)
	HI16,         // upper 16 of 32-bit absolute (LUI rt, %hi(sym)+0x8000 if LO16 paired)
	LO16,         // lower 16 of 32-bit absolute (ADDIU rt, rt, %lo(sym))
}

Token :: rexcode_isa.Token

Token_Kind :: rexcode_isa.Token_Kind

@(rodata)
DECODE_ENTRIES: []Decode_Entry = …

@(rodata)
DECODE_INDEX_COP1: []Decode_Index = …

@(rodata)
DECODE_INDEX_PRIMARY: []Decode_Index = …

@(rodata)
DECODE_INDEX_REGIMM: []Decode_Index = …

@(rodata)
DECODE_INDEX_SPECIAL: []Decode_Index = …

@(rodata)
DECODE_INDEX_SPECIAL2: []Decode_Index = …

@(rodata)
DECODE_INDEX_SPECIAL3: []Decode_Index = …

@(rodata)
ENCODE_FORMS: []Encoding = …

@(rodata)
ENCODE_RUNS: []Encode_Run = …