package core:rexcode/isa/rsp

Source

CP0_Reg :: enum u8 {
	SP_MEM_ADDR  = 0,  // DMEM/IMEM offset for DMA
	SP_DRAM_ADDR = 1,  // RDRAM address for DMA
	SP_RD_LEN    = 2,  // DMA read length
	SP_WR_LEN    = 3,  // DMA write length
	SP_STATUS    = 4,  // RSP status (halt/broke/busy)
	SP_DMA_FULL  = 5, 
	SP_DMA_BUSY  = 6, 
	SP_SEMAPHORE = 7, 
	DP_START     = 8,  // RDP command buffer start
	DP_END       = 9, 
	DP_CURRENT   = 10, 
	DP_STATUS    = 11, 
	DP_CLOCK     = 12, 
	DP_BUFBUSY   = 13, 
	DP_PIPEBUSY  = 14, 
	DP_TMEM      = 15, 
}

Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	flags:    Encoding_Flags,
}

Decode_Index :: struct #packed {
	start: u16,
	count: u16,
}

Encode_Run :: struct {
	start: u32,
	count: u32,
}

Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	flags:    Encoding_Flags,
}

Encoding_Flags :: distinct bit_field u8 {
	delay_slot: bool | 1,
	likely:     bool | 1,
	_:          u8 | 6,
}

Endianness :: enum u8 {
	LITTLE = 0, 
	BIG    = 1, 
}

Error :: rexcode_isa.Error

Error_Code :: rexcode_isa.Error_Code

Feature :: enum u8 {
	RSP_SCALAR, // scalar MIPS subset on the RSP core
	RSP_VU,     // RSP vector unit (COP2 with CO=1)
	RSP_VLS,    // RSP vector load/store (op=0x32/0x3A)
}

GPR :: enum u8 {
	ZERO = 0, 
	AT   = 1, 
	V0   = 2, 
	V1   = 3, 
	A0   = 4, 
	A1   = 5, 
	A2   = 6, 
	A3   = 7, 
	T0   = 8, 
	T1   = 9, 
	T2   = 10, 
	T3   = 11, 
	T4   = 12, 
	T5   = 13, 
	T6   = 14, 
	T7   = 15, 
	S0   = 16, 
	S1   = 17, 
	S2   = 18, 
	S3   = 19, 
	S4   = 20, 
	S5   = 21, 
	S6   = 22, 
	S7   = 23, 
	T8   = 24, 
	T9   = 25, 
	K0   = 26, 
	K1   = 27, 
	GP   = 28, 
	SP   = 29, 
	FP   = 30, 
	RA   = 31, 
}

Instruction :: struct #packed {
	ops:           [4]Operand `fmt:"v,operand_count"`,
	// 48 bytes
	mnemonic:      Mnemonic,
	//  2 bytes
	operand_count: u8,
	//  1 byte
	flags:         Instruction_Flags,
	//  1 byte
	length:        u8,
	//  1 byte (always 4)
	_:             [11]u8,
}

Instruction_Flags :: distinct bit_field u8 {
	_: u8 | 8,
}

Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}

Label_Definition :: rexcode_isa.Label_Definition

Label_Map :: rexcode_isa.Label_Map

Label_Names :: map[rexcode_isa.Label_Offset]string

Label_Offset :: rexcode_isa.Label_Offset

Memory :: struct #packed {
	base: Register,
	// GPR base
	_:    u16,
	disp: i32,
}

Mnemonic :: enum u16 {
	INVALID = 0, 
	// R-type arithmetic / logical / shift
	ADD, 
	ADDU, 
	SUB, 
	SUBU, 
	AND, 
	OR, 
	XOR, 
	NOR, 
	SLT, 
	SLTU, 
	SLL, 
	SRL, 
	SRA, 
	SLLV, 
	SRLV, 
	SRAV, 
	// I-type
	ADDI, 
	ADDIU, 
	SLTI, 
	SLTIU, 
	ANDI, 
	ORI, 
	XORI, 
	LUI, 
	// Branches (with delay slot)
	BEQ, 
	BNE, 
	BLEZ, 
	BGTZ, 
	BLTZ, 
	BGEZ, 
	BLTZAL, 
	BGEZAL, 
	// Jumps
	J, 
	JAL, 
	JR, 
	JALR, 
	// Load / Store (no LWL/LWR/SWL/SWR on the RSP).
	LB, 
	LH, 
	LW, 
	LBU, 
	LHU, 
	SB, 
	SH, 
	SW, 
	// System
	BREAK, 
	NOP, 
	// Coprocessor moves
	MFC0, 
	MTC0, 
	MFC2, 
	MTC2, 
	CFC2, 
	CTC2, 
	VMULF, 
	VMULU, 
	VMUDL, 
	VMUDM, 
	VMUDN, 
	VMUDH, 
	VMACF, 
	VMACU, 
	VMADL, 
	VMADM, 
	VMADN, 
	VMADH, 
	VADD, 
	VSUB, 
	VABS, 
	VADDC, 
	VSUBC, 
	VSAR, 
	VLT, 
	VEQ, 
	VNE, 
	VGE, 
	VCL, 
	VCH, 
	VCR, 
	VMRG, 
	VAND, 
	VNAND, 
	VOR, 
	VNOR, 
	VXOR, 
	VNXOR, 
	VRCP, 
	VRCPL, 
	VRCPH, 
	VMOV, 
	VRSQ, 
	VRSQL, 
	VRSQH, 
	VNOP, 
	LBV, 
	LSV, 
	LLV, 
	LDV, 
	LQV, 
	LRV, 
	LPV, 
	LUV, 
	LHV, 
	LFV, 
	LWV, 
	LTV, 
	SBV, 
	SSV, 
	SLV, 
	SDV, 
	SQV, 
	SRV, 
	SPV, 
	SUV, 
	SHV, 
	SFV, 
	SWV, 
	STV, 
}

Operand :: struct #packed {
	using _: struct #raw_union {
		reg:       Register,
		// for REGISTER and VECTOR_REG
		mem:       Memory,
		vmem:      Vector_Mem,
		immediate: i64,
		relative:  i64,
	},
	kind:    Operand_Kind,
	// 1 byte
	size:    u8,
	// 1 byte
	element: u8,
	// 1 byte — for VECTOR_REG
	_:       [1]u8,
}

Operand_Encoding :: enum u8 {
	NONE, 
	RS,          // bits 25-21
	RT,          // bits 20-16
	RD,          // bits 15-11
	SHAMT,       // bits 10-6
	IMM_16,      // bits 15-0
	IMM_5,       // bits 10-6
	IMM_20,      // bits 25-6
	IMM_26,      // bits 25-0
	OFFSET_BASE, // scalar memory (rs + 16-bit offset)
	BRANCH_16, 
	IMPL, 
	// Vector-unit placements
	VT,          // bits 20-16 (vector source 2)
	VS,          // bits 15-11 (vector source 1)
	VD,          // bits 10-6  (vector destination)
	ELEM,        // bits 24-21 (element selector for vector ALU)
	// Vector L/S placements
	VT_LS,       // bits 20-16 (target vector reg)
	VOP,         // bits 15-11 (vector L/S op selector LBV..LTV)
	VELEM_LS,    // bits 10-7  (element offset for L/S)
	VOFFSET,     // bits  6-0  (signed 7-bit offset, element-scaled)
	VBASE,       // bits 25-21 (GPR base for vector L/S)
}

Operand_Kind :: enum u8 {
	NONE, 
	REGISTER, 
	VECTOR_REG, // vector register with element selector
	MEMORY, 
	VECTOR_MEM, // vector memory: base + 7-bit offset + element selector
	IMMEDIATE, 
	RELATIVE, 
}

Operand_Type :: enum u8 {
	NONE, 
	GPR,      // scalar GPR
	VR,       // vector register $v0..$v31
	VR_ELEM,  // vector register with element selector (e.g. $v3[4])
	CP0_REG,  // RSP CP0 (DMA/status registers)
	CP2_CTRL, // VCO / VCC / VCE
	IMM5, 
	IMM16S, 
	IMM16U, 
	IMM20, 
	IMM26, 
	REL16, 
	REL_J26, 
	MEM,      // scalar memory (base+disp16)
	VMEM,     // vector memory (base+offset7 with element)
}

Print_Options :: rexcode_isa.Print_Options

Print_Result :: rexcode_isa.Print_Result

Register :: distinct u16

Relocation :: struct #packed {
	offset:   u32,
	label_id: u32,
	addend:   i32,
	type:     Relocation_Type,
	size:     u8,
	inst_idx: u16,
}

Relocation_Type :: enum u8 {
	NONE  = 0, 
	REL16,     // 16-bit signed PC-rel branch (BEQ/BNE/BLEZ/BGTZ/...)
	J26,       // 26-bit J-type region target ((target_addr >> 2) & 0x3FFFFFF)
}

Token :: rexcode_isa.Token

Token_Kind :: rexcode_isa.Token_Kind

VR :: enum u8 {
	V0  = 0, 
	V1  = 1, 
	V2  = 2, 
	V3  = 3, 
	V4  = 4, 
	V5  = 5, 
	V6  = 6, 
	V7  = 7, 
	V8  = 8, 
	V9  = 9, 
	V10 = 10, 
	V11 = 11, 
	V12 = 12, 
	V13 = 13, 
	V14 = 14, 
	V15 = 15, 
	V16 = 16, 
	V17 = 17, 
	V18 = 18, 
	V19 = 19, 
	V20 = 20, 
	V21 = 21, 
	V22 = 22, 
	V23 = 23, 
	V24 = 24, 
	V25 = 25, 
	V26 = 26, 
	V27 = 27, 
	V28 = 28, 
	V29 = 29, 
	V30 = 30, 
	V31 = 31, 
}

Vector_Mem :: struct #packed {
	base:    Register,
	// GPR base
	element: u8,
	// element selector (0-15; restricted by op)
	_:       u8,
	offset:  i32,
}

@(rodata)
DECODE_ENTRIES: []Decode_Entry = …

@(rodata)
DECODE_INDEX_COP2: []Decode_Index = …

@(rodata)
DECODE_INDEX_LWC2: []Decode_Index = …

@(rodata)
DECODE_INDEX_PRIMARY: []Decode_Index = …

@(rodata)
DECODE_INDEX_REGIMM: []Decode_Index = …

@(rodata)
DECODE_INDEX_SPECIAL: []Decode_Index = …

@(rodata)
DECODE_INDEX_SWC2: []Decode_Index = …

@(rodata)
ENCODE_FORMS: []Encoding = …

@(rodata)
ENCODE_RUNS: []Encode_Run = …