package core:rexcode/isa/rsp

Source

CP0_Reg :: enum u8 {
	SP_MEM_ADDR  = 0,  // DMEM/IMEM offset for DMA
	SP_DRAM_ADDR = 1,  // RDRAM address for DMA
	SP_RD_LEN    = 2,  // DMA read length
	SP_WR_LEN    = 3,  // DMA write length
	SP_STATUS    = 4,  // RSP status (halt/broke/busy)
	SP_DMA_FULL  = 5, 
	SP_DMA_BUSY  = 6, 
	SP_SEMAPHORE = 7, 
	DP_START     = 8,  // RDP command buffer start
	DP_END       = 9, 
	DP_CURRENT   = 10, 
	DP_STATUS    = 11, 
	DP_CLOCK     = 12, 
	DP_BUFBUSY   = 13, 
	DP_PIPEBUSY  = 14, 
	DP_TMEM      = 15, 
}

Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	flags:    Encoding_Flags,
}

Decode_Index :: struct #packed {
	start: u16,
	count: u16,
}

Encode_Run :: struct {
	start: u32,
	count: u32,
}

Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	flags:    Encoding_Flags,
}

Encoding_Flags :: distinct bit_field u8 {
	delay_slot: bool | 1,
	likely:     bool | 1,
	_:          u8 | 6,
}

Endianness :: enum u8 {
	LITTLE = 0, 
	BIG    = 1, 
}

Error :: rexcode_isa.Error

Error_Code :: rexcode_isa.Error_Code

Feature :: enum u8 {
	RSP_SCALAR, // scalar MIPS subset on the RSP core
	RSP_VU,     // RSP vector unit (COP2 with CO=1)
	RSP_VLS,    // RSP vector load/store (op=0x32/0x3A)
}

GPR :: enum u8 {
	ZERO = 0, 
	AT   = 1, 
	V0   = 2, 
	V1   = 3, 
	A0   = 4, 
	A1   = 5, 
	A2   = 6, 
	A3   = 7, 
	T0   = 8, 
	T1   = 9, 
	T2   = 10, 
	T3   = 11, 
	T4   = 12, 
	T5   = 13, 
	T6   = 14, 
	T7   = 15, 
	S0   = 16, 
	S1   = 17, 
	S2   = 18, 
	S3   = 19, 
	S4   = 20, 
	S5   = 21, 
	S6   = 22, 
	S7   = 23, 
	T8   = 24, 
	T9   = 25, 
	K0   = 26, 
	K1   = 27, 
	GP   = 28, 
	SP   = 29, 
	FP   = 30, 
	RA   = 31, 
}

Instruction :: struct #packed {
	ops:           [4]Operand `fmt:"v,operand_count"`,
	// 48 bytes
	mnemonic:      Mnemonic,
	//  2 bytes
	operand_count: u8,
	//  1 byte
	flags:         Instruction_Flags,
	//  1 byte
	length:        u8,
	//  1 byte (always 4)
	_:             [11]u8,
}

Instruction_Flags :: distinct bit_field u8 {
	_: u8 | 8,
}

Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}

Label_Definition :: rexcode_isa.Label_Definition

Label_Map :: rexcode_isa.Label_Map

Memory :: struct #packed {
	base: Register,
	// GPR base
	_:    u16,
	disp: i32,
}

Mnemonic :: enum u16 {
	INVALID = 0, 
	// R-type arithmetic / logical / shift
	ADD, 
	ADDU, 
	SUB, 
	SUBU, 
	AND, 
	OR, 
	XOR, 
	NOR, 
	SLT, 
	SLTU, 
	SLL, 
	SRL, 
	SRA, 
	SLLV, 
	SRLV, 
	SRAV, 
	// I-type
	ADDI, 
	ADDIU, 
	SLTI, 
	SLTIU, 
	ANDI, 
	ORI, 
	XORI, 
	LUI, 
	// Branches (with delay slot)
	BEQ, 
	BNE, 
	BLEZ, 
	BGTZ, 
	BLTZ, 
	BGEZ, 
	BLTZAL, 
	BGEZAL, 
	// Jumps
	J, 
	JAL, 
	JR, 
	JALR, 
	// Load / Store (no LWL/LWR/SWL/SWR on the RSP).
	LB, 
	LH, 
	LW, 
	LBU, 
	LHU, 
	SB, 
	SH, 
	SW, 
	// System
	BREAK, 
	NOP, 
	// Coprocessor moves
	MFC0, 
	MTC0, 
	MFC2, 
	MTC2, 
	CFC2, 
	CTC2, 
	VMULF, 
	VMULU, 
	VMUDL, 
	VMUDM, 
	VMUDN, 
	VMUDH, 
	VMACF, 
	VMACU, 
	VMADL, 
	VMADM, 
	VMADN, 
	VMADH, 
	VADD, 
	VSUB, 
	VABS, 
	VADDC, 
	VSUBC, 
	VSAR, 
	VLT, 
	VEQ, 
	VNE, 
	VGE, 
	VCL, 
	VCH, 
	VCR, 
	VMRG, 
	VAND, 
	VNAND, 
	VOR, 
	VNOR, 
	VXOR, 
	VNXOR, 
	VRCP, 
	VRCPL, 
	VRCPH, 
	VMOV, 
	VRSQ, 
	VRSQL, 
	VRSQH, 
	VNOP, 
	LBV, 
	LSV, 
	LLV, 
	LDV, 
	LQV, 
	LRV, 
	LPV, 
	LUV, 
	LHV, 
	LFV, 
	LWV, 
	LTV, 
	SBV, 
	SSV, 
	SLV, 
	SDV, 
	SQV, 
	SRV, 
	SPV, 
	SUV, 
	SHV, 
	SFV, 
	SWV, 
	STV, 
}

Operand :: struct #packed {
	using _: struct #raw_union {
		reg:       Register,
		// for REGISTER and VECTOR_REG
		mem:       Memory,
		vmem:      Vector_Mem,
		immediate: i64,
		relative:  i64,
	},
	kind:    Operand_Kind,
	// 1 byte
	size:    u8,
	// 1 byte
	element: u8,
	// 1 byte — for VECTOR_REG
	_:       [1]u8,
}

Operand_Encoding :: enum u8 {
	NONE, 
	RS,          // bits 25-21
	RT,          // bits 20-16
	RD,          // bits 15-11
	SHAMT,       // bits 10-6
	IMM_16,      // bits 15-0
	IMM_5,       // bits 10-6
	IMM_20,      // bits 25-6
	IMM_26,      // bits 25-0
	OFFSET_BASE, // scalar memory (rs + 16-bit offset)
	BRANCH_16, 
	IMPL, 
	// Vector-unit placements
	VT,          // bits 20-16 (vector source 2)
	VS,          // bits 15-11 (vector source 1)
	VD,          // bits 10-6  (vector destination)
	ELEM,        // bits 24-21 (element selector for vector ALU)
	// Vector L/S placements
	VT_LS,       // bits 20-16 (target vector reg)
	VOP,         // bits 15-11 (vector L/S op selector LBV..LTV)
	VELEM_LS,    // bits 10-7  (element offset for L/S)
	VOFFSET,     // bits  6-0  (signed 7-bit offset, element-scaled)
	VBASE,       // bits 25-21 (GPR base for vector L/S)
}

Operand_Kind :: enum u8 {
	NONE, 
	REGISTER, 
	VECTOR_REG, // vector register with element selector
	MEMORY, 
	VECTOR_MEM, // vector memory: base + 7-bit offset + element selector
	IMMEDIATE, 
	RELATIVE, 
}

Operand_Type :: enum u8 {
	NONE, 
	GPR,      // scalar GPR
	VR,       // vector register $v0..$v31
	VR_ELEM,  // vector register with element selector (e.g. $v3[4])
	CP0_REG,  // RSP CP0 (DMA/status registers)
	CP2_CTRL, // VCO / VCC / VCE
	IMM5, 
	IMM16S, 
	IMM16U, 
	IMM20, 
	IMM26, 
	REL16, 
	REL_J26, 
	MEM,      // scalar memory (base+disp16)
	VMEM,     // vector memory (base+offset7 with element)
}

Print_Options :: rexcode_isa.Print_Options

Print_Result :: rexcode_isa.Print_Result

Register :: distinct u16

Relocation :: struct #packed {
	offset:   u32,
	label_id: u32,
	addend:   i32,
	type:     Relocation_Type,
	size:     u8,
	inst_idx: u16,
}

Relocation_Type :: enum u8 {
	NONE  = 0, 
	REL16,     // 16-bit signed PC-rel branch (BEQ/BNE/BLEZ/BGTZ/...)
	J26,       // 26-bit J-type region target ((target_addr >> 2) & 0x3FFFFFF)
}

Token :: rexcode_isa.Token

Token_Kind :: rexcode_isa.Token_Kind

VR :: enum u8 {
	V0  = 0, 
	V1  = 1, 
	V2  = 2, 
	V3  = 3, 
	V4  = 4, 
	V5  = 5, 
	V6  = 6, 
	V7  = 7, 
	V8  = 8, 
	V9  = 9, 
	V10 = 10, 
	V11 = 11, 
	V12 = 12, 
	V13 = 13, 
	V14 = 14, 
	V15 = 15, 
	V16 = 16, 
	V17 = 17, 
	V18 = 18, 
	V19 = 19, 
	V20 = 20, 
	V21 = 21, 
	V22 = 22, 
	V23 = 23, 
	V24 = 24, 
	V25 = 25, 
	V26 = 26, 
	V27 = 27, 
	V28 = 28, 
	V29 = 29, 
	V30 = 30, 
	V31 = 31, 
}

Vector_Mem :: struct #packed {
	base:    Register,
	// GPR base
	element: u8,
	// element selector (0-15; restricted by op)
	_:       u8,
	offset:  i32,
}

A0 :: Register(REG_GPR | 4)

A1 :: Register(REG_GPR | 5)

A2 :: Register(REG_GPR | 6)

A3 :: Register(REG_GPR | 7)

AT :: Register(REG_GPR | 1)

DEFAULT_PRINT_OPTIONS: rexcode_isa.Print_Options : isa.DEFAULT_PRINT_OPTIONS

FP :: Register(REG_GPR | 30)

GP :: Register(REG_GPR | 28)

K0 :: Register(REG_GPR | 26)

K1 :: Register(REG_GPR | 27)

LABEL_UNDEFINED: rexcode_isa.Label_Definition : isa.LABEL_UNDEFINED

MASK_FUNCT :: u32(0x0000003F)

MASK_OPCODE :: u32(0xFC000000)

MASK_RD :: u32(0x0000F800)

MASK_RS :: u32(0x03E00000)

MASK_RT :: u32(0x001F0000)

MASK_SHAMT :: u32(0x000007C0)

MASK_VELEM :: u32(0x01E00000)

MASK_VOFFS7 :: u32(0x0000007F)

MAX_INST_SIZE :: 4

NONE :: Register(0xFFFF)

RA :: Register(REG_GPR | 31)

REG_CP0 :: 0x0400

REG_GPR :: 0x0100

REG_NONE :: 0x0000

REG_VC :: 0x0300

REG_VR :: 0x0200

S0 :: Register(REG_GPR | 16)

S1 :: Register(REG_GPR | 17)

S2 :: Register(REG_GPR | 18)

S3 :: Register(REG_GPR | 19)

S4 :: Register(REG_GPR | 20)

S5 :: Register(REG_GPR | 21)

S6 :: Register(REG_GPR | 22)

S7 :: Register(REG_GPR | 23)

SP :: Register(REG_GPR | 29)

T0 :: Register(REG_GPR | 8)

T1 :: Register(REG_GPR | 9)

T2 :: Register(REG_GPR | 10)

T3 :: Register(REG_GPR | 11)

T4 :: Register(REG_GPR | 12)

T5 :: Register(REG_GPR | 13)

T6 :: Register(REG_GPR | 14)

T7 :: Register(REG_GPR | 15)

T8 :: Register(REG_GPR | 24)

T9 :: Register(REG_GPR | 25)

V0 :: Register(REG_GPR | 2)

V1 :: Register(REG_GPR | 3)

VCC :: Register(REG_VC | 1)

VCE :: Register(REG_VC | 2)

VCO :: Register(REG_VC | 0)

VR0 :: Register(REG_VR | 0)

VR1 :: Register(REG_VR | 1)

VR10 :: Register(REG_VR | 10)

VR11 :: Register(REG_VR | 11)

VR12 :: Register(REG_VR | 12)

VR13 :: Register(REG_VR | 13)

VR14 :: Register(REG_VR | 14)

VR15 :: Register(REG_VR | 15)

VR16 :: Register(REG_VR | 16)

VR17 :: Register(REG_VR | 17)

VR18 :: Register(REG_VR | 18)

VR19 :: Register(REG_VR | 19)

VR2 :: Register(REG_VR | 2)

VR20 :: Register(REG_VR | 20)

VR21 :: Register(REG_VR | 21)

VR22 :: Register(REG_VR | 22)

VR23 :: Register(REG_VR | 23)

VR24 :: Register(REG_VR | 24)

VR25 :: Register(REG_VR | 25)

VR26 :: Register(REG_VR | 26)

VR27 :: Register(REG_VR | 27)

VR28 :: Register(REG_VR | 28)

VR29 :: Register(REG_VR | 29)

VR3 :: Register(REG_VR | 3)

VR30 :: Register(REG_VR | 30)

VR31 :: Register(REG_VR | 31)

VR4 :: Register(REG_VR | 4)

VR5 :: Register(REG_VR | 5)

VR6 :: Register(REG_VR | 6)

VR7 :: Register(REG_VR | 7)

VR8 :: Register(REG_VR | 8)

VR9 :: Register(REG_VR | 9)

ZERO :: Register(REG_GPR | 0)

@(rodata)
DECODE_ENTRIES: []Decode_Entry = …

@(rodata)
DECODE_INDEX_COP2: []Decode_Index = …

@(rodata)
DECODE_INDEX_LWC2: []Decode_Index = …

@(rodata)
DECODE_INDEX_PRIMARY: []Decode_Index = …

@(rodata)
DECODE_INDEX_REGIMM: []Decode_Index = …

@(rodata)
DECODE_INDEX_SPECIAL: []Decode_Index = …

@(rodata)
DECODE_INDEX_SWC2: []Decode_Index = …

@(rodata)
ENCODE_FORMS: []Encoding = …

@(rodata)
ENCODE_RUNS: []Encode_Run = …

aprint :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
	allocator := context.allocator, 
) -> string {…}

aprintln :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
	allocator := context.allocator, 
) -> string {…}

bprint :: proc(
	buf:          []u8, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

bprintln :: proc(
	buf:          []u8, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

decode :: proc(
	data:         []u8, 
	relocs:       []Relocation, 
	instructions: ^[dynamic]Instruction, 
	inst_info:    ^[dynamic]Instruction_Info, 
	label_defs:   ^[dynamic]rexcode_isa.Label_Definition, 
	errors:       ^[dynamic]rexcode_isa.Error, 
	endianness:   Endianness = .BIG, 
) -> (byte_count: u32, ok: bool) {…}

decode_estimate_instruction_count :: proc "contextless" (data: []u8) -> int {…}

decode_max_instruction_count :: proc "contextless" (data: []u8) -> int {…}

decode_reserve :: proc(instructions: ^[dynamic]Instruction, inst_info: ^[dynamic]Instruction_Info, label_defs: ^[dynamic]rexcode_isa.Label_Definition, data: []u8, exact: bool = false) {…}

emit_add :: emit_add_gpr_gpr_gpr

emit_add_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_addi :: emit_addi_gpr_gpr_imm16

emit_addi_gpr_gpr_imm16 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) {…}

emit_addiu :: emit_addiu_gpr_gpr_imm16

emit_addiu_gpr_gpr_imm16 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) {…}

emit_addu :: emit_addu_gpr_gpr_gpr

emit_addu_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_and :: emit_and_gpr_gpr_gpr

emit_and_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_andi :: emit_andi_gpr_gpr_imm16

emit_andi_gpr_gpr_imm16 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) {…}

emit_beq :: emit_beq_gpr_gpr_rel

emit_beq_gpr_gpr_rel :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, label_id: u32) {…}

emit_bgez :: emit_bgez_gpr_rel

emit_bgez_gpr_rel :: proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) {…}

emit_bgezal :: emit_bgezal_gpr_rel

emit_bgezal_gpr_rel :: proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) {…}

emit_bgtz :: emit_bgtz_gpr_rel

emit_bgtz_gpr_rel :: proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) {…}

emit_blez :: emit_blez_gpr_rel

emit_blez_gpr_rel :: proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) {…}

emit_bltz :: emit_bltz_gpr_rel

emit_bltz_gpr_rel :: proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) {…}

emit_bltzal :: emit_bltzal_gpr_rel

emit_bltzal_gpr_rel :: proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) {…}

emit_bne :: emit_bne_gpr_gpr_rel

emit_bne_gpr_gpr_rel :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, label_id: u32) {…}

emit_break :: emit_break_imm20

emit_break_imm20 :: proc(instructions: ^[dynamic]Instruction, imm: i64) {…}

emit_cfc2 :: emit_cfc2_gpr_cp2

emit_cfc2_gpr_cp2 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) {…}

emit_ctc2 :: emit_ctc2_gpr_cp2

emit_ctc2_gpr_cp2 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) {…}

emit_j :: emit_j_rel

emit_j_rel :: proc(instructions: ^[dynamic]Instruction, label_id: u32) {…}

emit_jal :: emit_jal_rel

emit_jal_rel :: proc(instructions: ^[dynamic]Instruction, label_id: u32) {…}

emit_jalr :: emit_jalr_gpr_gpr

emit_jalr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) {…}

emit_jr :: emit_jr_gpr

emit_jr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register) {…}

emit_lb :: emit_lb_gpr_mem

emit_lb_gpr_mem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) {…}

emit_lbu :: emit_lbu_gpr_mem

emit_lbu_gpr_mem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) {…}

emit_lbv :: emit_lbv_vr_vmem

emit_lbv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_ldv :: emit_ldv_vr_vmem

emit_ldv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_lfv :: emit_lfv_vr_vmem

emit_lfv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_lh :: emit_lh_gpr_mem

emit_lh_gpr_mem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) {…}

emit_lhu :: emit_lhu_gpr_mem

emit_lhu_gpr_mem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) {…}

emit_lhv :: emit_lhv_vr_vmem

emit_lhv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_llv :: emit_llv_vr_vmem

emit_llv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_lpv :: emit_lpv_vr_vmem

emit_lpv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_lqv :: emit_lqv_vr_vmem

emit_lqv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_lrv :: emit_lrv_vr_vmem

emit_lrv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_lsv :: emit_lsv_vr_vmem

emit_lsv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_ltv :: emit_ltv_vr_vmem

emit_ltv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_lui :: emit_lui_gpr_imm16

emit_lui_gpr_imm16 :: proc(instructions: ^[dynamic]Instruction, a: Register, imm: i64) {…}

emit_luv :: emit_luv_vr_vmem

emit_luv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_lw :: emit_lw_gpr_mem

emit_lw_gpr_mem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) {…}

emit_lwv :: emit_lwv_vr_vmem

emit_lwv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_mfc0 :: emit_mfc0_gpr_cp0

emit_mfc0_gpr_cp0 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) {…}

emit_mfc2 :: emit_mfc2_gpr_vr

emit_mfc2_gpr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) {…}

emit_mtc0 :: emit_mtc0_gpr_cp0

emit_mtc0_gpr_cp0 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) {…}

emit_mtc2 :: emit_mtc2_gpr_vr

emit_mtc2_gpr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) {…}

emit_nop :: emit_nop_none

emit_nop_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_nor :: emit_nor_gpr_gpr_gpr

emit_nor_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_or :: emit_or_gpr_gpr_gpr

emit_or_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_ori :: emit_ori_gpr_gpr_imm16

emit_ori_gpr_gpr_imm16 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) {…}

emit_sb :: emit_sb_gpr_mem

emit_sb_gpr_mem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) {…}

emit_sbv :: emit_sbv_vr_vmem

emit_sbv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_sdv :: emit_sdv_vr_vmem

emit_sdv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_sfv :: emit_sfv_vr_vmem

emit_sfv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_sh :: emit_sh_gpr_mem

emit_sh_gpr_mem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) {…}

emit_shv :: emit_shv_vr_vmem

emit_shv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_sll :: emit_sll_gpr_gpr_imm5

emit_sll_gpr_gpr_imm5 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) {…}

emit_sllv :: emit_sllv_gpr_gpr_gpr

emit_sllv_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_slt :: emit_slt_gpr_gpr_gpr

emit_slt_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_slti :: emit_slti_gpr_gpr_imm16

emit_slti_gpr_gpr_imm16 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) {…}

emit_sltiu :: emit_sltiu_gpr_gpr_imm16

emit_sltiu_gpr_gpr_imm16 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) {…}

emit_sltu :: emit_sltu_gpr_gpr_gpr

emit_sltu_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_slv :: emit_slv_vr_vmem

emit_slv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_spv :: emit_spv_vr_vmem

emit_spv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_sqv :: emit_sqv_vr_vmem

emit_sqv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_sra :: emit_sra_gpr_gpr_imm5

emit_sra_gpr_gpr_imm5 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) {…}

emit_srav :: emit_srav_gpr_gpr_gpr

emit_srav_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_srl :: emit_srl_gpr_gpr_imm5

emit_srl_gpr_gpr_imm5 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) {…}

emit_srlv :: emit_srlv_gpr_gpr_gpr

emit_srlv_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_srv :: emit_srv_vr_vmem

emit_srv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_ssv :: emit_ssv_vr_vmem

emit_ssv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_stv :: emit_stv_vr_vmem

emit_stv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_sub :: emit_sub_gpr_gpr_gpr

emit_sub_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_subu :: emit_subu_gpr_gpr_gpr

emit_subu_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_suv :: emit_suv_vr_vmem

emit_suv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_sw :: emit_sw_gpr_mem

emit_sw_gpr_mem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) {…}

emit_swv :: emit_swv_vr_vmem

emit_swv_vr_vmem :: proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) {…}

emit_vabs :: emit_vabs_vr_vr_vr

emit_vabs_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vadd :: emit_vadd_vr_vr_vr

emit_vadd_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vaddc :: emit_vaddc_vr_vr_vr

emit_vaddc_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vand :: emit_vand_vr_vr_vr

emit_vand_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vch :: emit_vch_vr_vr_vr

emit_vch_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vcl :: emit_vcl_vr_vr_vr

emit_vcl_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vcr :: emit_vcr_vr_vr_vr

emit_vcr_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_veq :: emit_veq_vr_vr_vr

emit_veq_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vge :: emit_vge_vr_vr_vr

emit_vge_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vlt :: emit_vlt_vr_vr_vr

emit_vlt_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmacf :: emit_vmacf_vr_vr_vr

emit_vmacf_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmacu :: emit_vmacu_vr_vr_vr

emit_vmacu_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmadh :: emit_vmadh_vr_vr_vr

emit_vmadh_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmadl :: emit_vmadl_vr_vr_vr

emit_vmadl_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmadm :: emit_vmadm_vr_vr_vr

emit_vmadm_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmadn :: emit_vmadn_vr_vr_vr

emit_vmadn_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmov :: emit_vmov_vr_vr

emit_vmov_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, element: u8 = 0) {…}

emit_vmrg :: emit_vmrg_vr_vr_vr

emit_vmrg_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmudh :: emit_vmudh_vr_vr_vr

emit_vmudh_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmudl :: emit_vmudl_vr_vr_vr

emit_vmudl_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmudm :: emit_vmudm_vr_vr_vr

emit_vmudm_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmudn :: emit_vmudn_vr_vr_vr

emit_vmudn_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmulf :: emit_vmulf_vr_vr_vr

emit_vmulf_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vmulu :: emit_vmulu_vr_vr_vr

emit_vmulu_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vnand :: emit_vnand_vr_vr_vr

emit_vnand_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vne :: emit_vne_vr_vr_vr

emit_vne_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vnop :: emit_vnop_none

emit_vnop_none :: proc(instructions: ^[dynamic]Instruction) {…}

emit_vnor :: emit_vnor_vr_vr_vr

emit_vnor_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vnxor :: emit_vnxor_vr_vr_vr

emit_vnxor_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vor :: emit_vor_vr_vr_vr

emit_vor_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vrcp :: emit_vrcp_vr_vr_vr

emit_vrcp_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vrcph :: emit_vrcph_vr_vr_vr

emit_vrcph_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vrcpl :: emit_vrcpl_vr_vr_vr

emit_vrcpl_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vrsq :: emit_vrsq_vr_vr_vr

emit_vrsq_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vrsqh :: emit_vrsqh_vr_vr_vr

emit_vrsqh_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vrsql :: emit_vrsql_vr_vr_vr

emit_vrsql_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vsar :: emit_vsar_vr_vr_vr

emit_vsar_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vsub :: emit_vsub_vr_vr_vr

emit_vsub_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vsubc :: emit_vsubc_vr_vr_vr

emit_vsubc_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_vxor :: emit_vxor_vr_vr_vr

emit_vxor_vr_vr_vr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) {…}

emit_xor :: emit_xor_gpr_gpr_gpr

emit_xor_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) {…}

emit_xori :: emit_xori_gpr_gpr_imm16

emit_xori_gpr_gpr_imm16 :: proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) {…}

encode :: proc(
	instructions: []Instruction, 
	label_defs:   []rexcode_isa.Label_Definition, 
	code:         []u8, 
	relocs:       ^[dynamic]Relocation, 
	errors:       ^[dynamic]rexcode_isa.Error, 
	endianness:   Endianness = .BIG, 
	resolve:      bool = true, 
	base_address: u64 = 0, 
) -> (byte_count: u32, ok: bool) {…}

encode_max_code_size :: proc "contextless" (instructions: []Instruction) -> int {…}

encode_max_relocation_count :: proc "contextless" (instructions: []Instruction) -> int {…}

encode_reserve :: proc(code: ^[dynamic]u8, relocs: ^[dynamic]Relocation, instructions: []Instruction) {…}

fprint :: proc(
	fd:           ^os.File, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

fprintln :: proc(
	fd:           ^os.File, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

gpr_from_num :: proc "contextless" (num: u8) -> Register {…}

inst_add :: inst_add_gpr_gpr_gpr

inst_add_gpr_gpr_gpr :: proc "contextless" (a: Register, b: Register, c: Register) -> Instruction {…}

inst_addi :: inst_addi_gpr_gpr_imm16

inst_addi_gpr_gpr_imm16 :: proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction {…}

inst_addiu :: inst_addiu_gpr_gpr_imm16

inst_addiu_gpr_gpr_imm16 :: proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction {…}

inst_addu :: inst_addu_gpr_gpr_gpr

inst_addu_gpr_gpr_gpr :: proc "contextless" (a: Register, b: Register, c: Register) -> Instruction {…}

inst_and :: inst_and_gpr_gpr_gpr

inst_and_gpr_gpr_gpr :: proc "contextless" (a: Register, b: Register, c: Register) -> Instruction {…}

inst_andi :: inst_andi_gpr_gpr_imm16

inst_andi_gpr_gpr_imm16 :: proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction {…}

inst_beq :: inst_beq_gpr_gpr_rel

inst_beq_gpr_gpr_rel :: proc "contextless" (a: Register, b: Register, label_id: u32) -> Instruction {…}

inst_bgez :: inst_bgez_gpr_rel

inst_bgez_gpr_rel :: proc "contextless" (a: Register, label_id: u32) -> Instruction {…}

inst_bgezal :: inst_bgezal_gpr_rel

inst_bgezal_gpr_rel :: proc "contextless" (a: Register, label_id: u32) -> Instruction {…}

inst_bgtz :: inst_bgtz_gpr_rel

inst_bgtz_gpr_rel :: proc "contextless" (a: Register, label_id: u32) -> Instruction {…}

inst_blez :: inst_blez_gpr_rel

inst_blez_gpr_rel :: proc "contextless" (a: Register, label_id: u32) -> Instruction {…}

inst_bltz :: inst_bltz_gpr_rel

inst_bltz_gpr_rel :: proc "contextless" (a: Register, label_id: u32) -> Instruction {…}

inst_bltzal :: inst_bltzal_gpr_rel

inst_bltzal_gpr_rel :: proc "contextless" (a: Register, label_id: u32) -> Instruction {…}

inst_bne :: inst_bne_gpr_gpr_rel

inst_bne_gpr_gpr_rel :: proc "contextless" (a: Register, b: Register, label_id: u32) -> Instruction {…}

inst_branch1 :: proc "contextless" (m: Mnemonic, rs: Register, label_id: u32) -> Instruction {…}

inst_branch2 :: proc "contextless" (m: Mnemonic, rs, rt: Register, label_id: u32) -> Instruction {…}

inst_break :: inst_break_imm20

inst_break_imm20 :: proc "contextless" (imm: i64) -> Instruction {…}

inst_cfc2 :: inst_cfc2_gpr_cp2

inst_cfc2_gpr_cp2 :: proc "contextless" (a: Register, b: Register) -> Instruction {…}

inst_ctc2 :: inst_ctc2_gpr_cp2