package core:rexcode/isa/mos6502

Source

Address_Mode :: enum u8 {
	ZP,        // $nn
	ZP_X,      // $nn,X
	ZP_Y,      // $nn,Y
	ABS,       // $nnnn
	ABS_X,     // $nnnn,X
	ABS_Y,     // $nnnn,Y
	IND,       // ($nnnn) -- JMP only
	IND_X,     // ($nn,X)
	IND_Y,     // ($nn),Y
	IND_ZP,    // ($nn) -- 65C02
	IND_ABS_X, // ($nnnn,X) -- 65C02 JMP only
}

CPU :: enum u8 {
	NMOS, 
	NMOS_UNDOC, 
	CMOS_65C02, 
	HUC6280, 
}

Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [3]Operand_Type,
	// 3
	enc:      [3]Operand_Encoding,
	// 3
	opcode:   u8,
	// 1
	length:   u8,
	// 1
	cpu:      CPU,
	// 1
	flags:    Encoding_Flags,
}

Decode_Index :: struct #packed {
	start: u16,
	count: u16,
}

Encode_Run :: struct {
	start: u32,
	count: u32,
}

Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	opcode:   u8,
	// 1
	length:   u8,
	// 1
	cpu:      CPU,
	// 1
	flags:    Encoding_Flags,
}

Encoding_Flags :: distinct bit_field u8 {
	decimal:     bool | 1,
	page_cross:  bool | 1,
	branch:      bool | 1,
	cond_branch: bool | 1,
	_:           u8 | 4,
}

Error :: rexcode_isa.Error

Error_Code :: rexcode_isa.Error_Code

GP :: enum u8 {
	A = 0, 
	X = 1, 
	Y = 2, 
}

Instruction :: struct #packed {
	ops:           [3]Operand `fmt:"v,operand_count"`,
	// 30 bytes
	mnemonic:      Mnemonic,
	// 2
	operand_count: u8,
	// 1
	flags:         Instruction_Flags,
	// 1
	length:        u8,
	// 1 (filled by decoder; 1..7)
	_:             [1]u8,
}

Instruction_Flags :: distinct bit_field u8 {
	_: u8 | 8,
}

Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}

Label_Definition :: rexcode_isa.Label_Definition

Label_Map :: rexcode_isa.Label_Map

Label_Names :: map[rexcode_isa.Label_Offset]string

Label_Offset :: rexcode_isa.Label_Offset

Memory :: struct #packed {
	address: u16,
	mode:    Address_Mode,
	_:       u8,
}

Mnemonic :: enum u16 {
	INVALID = 0, 
	// Arithmetic / logical
	ADC, 
	AND, 
	ASL, 
	BIT, 
	CMP, 
	CPX, 
	CPY, 
	DEC, 
	DEX, 
	DEY, 
	EOR, 
	INC, 
	INX, 
	INY, 
	LSR, 
	ORA, 
	ROL, 
	ROR, 
	SBC, 
	// Branches
	BCC, 
	BCS, 
	BEQ, 
	BMI, 
	BNE, 
	BPL, 
	BVC, 
	BVS, 
	// Jumps / subroutines / interrupts
	JMP, 
	JSR, 
	RTI, 
	RTS, 
	BRK, 
	// Flag ops
	CLC, 
	CLD, 
	CLI, 
	CLV, 
	SEC, 
	SED, 
	SEI, 
	// Loads / stores
	LDA, 
	LDX, 
	LDY, 
	STA, 
	STX, 
	STY, 
	// Stack / transfer
	PHA, 
	PHP, 
	PLA, 
	PLP, 
	TAX, 
	TAY, 
	TSX, 
	TXA, 
	TXS, 
	TYA, 
	// NOP
	NOP, 
	LAX,         // LDA + LDX (load A and X from memory)
	DCP,         // DEC + CMP (memory)
	ISC,         // INC + SBC (also ISB)
	RLA,         // ROL + AND
	RRA,         // ROR + ADC
	SLO,         // ASL + ORA
	SRE,         // LSR + EOR
	ALR,         // AND #imm + LSR A
	ANC,         // AND #imm with carry from N
	ARR,         // AND #imm + ROR A
	AXS,         // X = (A AND X) - imm  (also SBX)
	LAS,         // LDA / TSX / AND with stack pointer
	ANE,         // A = (A | $EE) AND X AND imm  -- unstable (also XAA)
	LXA,         // A = X = (A | $EE) AND imm    -- unstable
	SHA,         // store A AND X AND high+1
	SHX,         // store X AND high+1
	SHY,         // store Y AND high+1
	TAS,         // S = A AND X; store S AND high+1
	JAM,         // halt the CPU (also KIL / HLT)
	USBC,        // same as SBC #imm but at $EB (an undocumented alias)
	DOP,         // double NOP (skips one operand byte)
	TOP,         // triple NOP (skips two operand bytes)
	BRA,         // branch always
	INA,         // INC A
	DEA,         // DEC A
	PHX, 
	PHY, 
	PLX, 
	PLY, 
	STZ,         // store zero
	TRB, 
	TSB,         // test-and-reset / test-and-set bits
	STP, 
	WAI,         // WDC: stop, wait-for-interrupt
	// 65C02 Rockwell bit ops -- 32 distinct opcodes
	RMB0, 
	RMB1, 
	RMB2, 
	RMB3, 
	RMB4, 
	RMB5, 
	RMB6, 
	RMB7, 
	SMB0, 
	SMB1, 
	SMB2, 
	SMB3, 
	SMB4, 
	SMB5, 
	SMB6, 
	SMB7, 
	BBR0, 
	BBR1, 
	BBR2, 
	BBR3, 
	BBR4, 
	BBR5, 
	BBR6, 
	BBR7, 
	BBS0, 
	BBS1, 
	BBS2, 
	BBS3, 
	BBS4, 
	BBS5, 
	BBS6, 
	BBS7, 
	SXY,         // swap X, Y
	SAX,         // swap A,X (HuC6280) / store A AND X (NMOS undocumented)
	SAY,         // swap A, Y
	CLA, 
	CLX, 
	CLY,         // clear A / X / Y
	CSH, 
	CSL,         // CPU speed high / low (7.16 MHz vs 1.79 MHz)
	SET,         // set T flag (next op uses zp address as accumulator)
	ST0, 
	ST1, 
	ST2,         // store immediate to MMR0/1/2
	TAM, 
	TMA,         // transfer A to/from MMR (immediate-selected)
	TST,         // bit test of immediate against memory
	BSR,         // branch to subroutine (PC-relative)
	// HuC6280 block transfer instructions (7-byte encoding)
	//   src(2) -> dst(2), len(2) bytes
	TII,         // transfer increment-increment   (memcpy ascending)
	TDD,         // transfer decrement-decrement   (memcpy descending)
	TIN,         // transfer increment-no-change   (fill from src)
	TIA,         // transfer increment-alternate   (interleaved)
	TAI,         // transfer alternate-increment   (interleaved)
}

Operand :: struct #packed {
	using _: struct #raw_union {
		reg:       Register,
		// 2 bytes
		mem:       Memory,
		// 4 bytes
		immediate: i64,
		// 8 bytes
		relative:  i64,
	},
	kind: Operand_Kind,
	// 1
	size: u8,
}

Operand_Encoding :: enum u8 {
	NONE, 
	IMPL,        // implicit / accumulator -- no bytes emitted
	BYTE_1_IMM,  // 8-bit immediate at offset 1
	BYTE_1_ADDR, // 8-bit zero-page address at offset 1
	BYTE_1_REL,  // signed 8-bit PC-rel at offset 1
	WORD_1_ADDR, // 16-bit little-endian absolute at offset 1
	BYTE_2_REL,  // signed 8-bit PC-rel at offset 2 (BBR/BBS)
	WORD_1,      // 16-bit LE at offset 1 (HuC block xfer src)
	WORD_3,      // 16-bit LE at offset 3 (HuC block xfer dst)
	WORD_5,      // 16-bit LE at offset 5 (HuC block xfer len)
	BYTE_2_ADDR, // 8-bit zero-page address at offset 2 (HuC TST # zp)
	WORD_2_ADDR, // 16-bit LE absolute at offset 2 (HuC TST # abs)
}

Operand_Kind :: enum u8 {
	NONE, 
	REGISTER,  // mostly used for `A` in `ROL A` (implicit; rarely needed)
	IMMEDIATE, 
	MEMORY, 
	RELATIVE,  // PC-relative target (label or raw byte offset)
}

Operand_Type :: enum u8 {
	NONE, 
	A_IMPL,        // accumulator (e.g. ROL A) -- no operand bytes encoded
	IMM_8,         // #$nn
	REL,           // signed byte PC-rel branch target
	MEM_ZP,        // $nn
	MEM_ZP_X,      // $nn,X
	MEM_ZP_Y,      // $nn,Y
	MEM_ABS,       // $nnnn
	MEM_ABS_X,     // $nnnn,X
	MEM_ABS_Y,     // $nnnn,Y
	MEM_IND,       // ($nnnn) -- NMOS/65C02 JMP only
	MEM_IND_X,     // ($nn,X)
	MEM_IND_Y,     // ($nn),Y
	MEM_IND_ZP,    // ($nn) -- 65C02
	MEM_IND_ABS_X, // ($nnnn,X) -- 65C02 JMP only
	IMM_16,        // unsigned 16-bit literal (HuC6280 block xfer operands)
}

Print_Options :: rexcode_isa.Print_Options

Print_Result :: rexcode_isa.Print_Result

Register :: distinct u16

Relocation :: struct #packed {
	offset:   u32,
	label_id: u32,
	addend:   i32,
	type:     Relocation_Type,
	size:     u8,
	inst_idx: u16,
}

Relocation_Type :: enum u8 {
	NONE  = 0, 
	ABS16, 
	REL8, 
}

Token :: rexcode_isa.Token

Token_Kind :: rexcode_isa.Token_Kind

@(rodata)
DECODE_ENTRIES: []Decode_Entry = …

@(rodata)
DECODE_INDEX_OPCODE: []Decode_Index = …

@(rodata)
ENCODE_FORMS: []Encoding = …

@(rodata)
ENCODE_RUNS: []Encode_Run = …