package core:rexcode/isa/arm32

Source

Data_Type :: enum u8 {
	NONE, 
	S8, 
	S16, 
	S32, 
	S64,  // signed integer
	U8, 
	U16, 
	U32, 
	U64,  // unsigned integer
	I8, 
	I16, 
	I32, 
	I64,  // sign-agnostic integer
	F16, 
	F32, 
	F64,  // floating point
	P8, 
	P16,  // polynomial
	BF16, // bfloat16
	SZ8, 
	SZ16, 
	SZ32, 
	SZ64, // bare element size (`vmov.32`, `vstrb.8`)
}

Data_Types :: [2]Data_Type

Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [6]Operand_Type,
	// 6
	enc:      [6]Operand_Encoding,
	// 6
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	mode:     Mode,
	// 1
	flags:    Encoding_Flags,
	// 1
	dt:       [2]Data_Type,
}

Decode_Index :: struct #packed {
	start: u16,
	count: u16,
}

Encode_Run :: struct {
	start: u32,
	count: u32,
}

Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [6]Operand_Type,
	// 6
	enc:      [6]Operand_Encoding,
	// 6
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	mode:     Mode,
	// 1
	flags:    Encoding_Flags,
	// 1
	dt:       [2]Data_Type,
}

Encoding_Flags :: distinct bit_field u8 {
	sets_flags:  bool | 1,
	cond_in_28:  bool | 1,
	branch:      bool | 1,
	cond_branch: bool | 1,
	writes_pc:   bool | 1,
	thumb32:     bool | 1,
	deprecated:  bool | 1,
	cond_in_21:  bool | 1,
}

Error :: rexcode_isa.Error

Error_Code :: rexcode_isa.Error_Code

Feature :: enum u8 {
	BASE,         // ARMv4 base ISA (works on every ARM core including ARM7TDMI / GBA)
	THUMB,        // Thumb-1 (ARMv4T+)
	V5T,          // ARMv5T additions (BLX, CLZ, BKPT)
	V5TE,         // ARMv5TE DSP extensions (SMLAxy / SMULxy / etc.)
	V5TEJ,        // ARMv5TEJ (BXJ; Jazelle support)
	V6,           // ARMv6 SIMD-on-GPR + REV/SXTB/etc.
	V6K,          // ARMv6K (CLREX, multiprocessing hints)
	V6T2,         // ARMv6T2 (Thumb-2, MOVW/MOVT, bitfield)
	V7,           // ARMv7-A/R base (DMB/DSB/ISB, LDREX/STREX full set)
	V7VE,         // ARMv7-A Virtualisation Extensions (HVC, ERET)
	V8,           // ARMv8-A AArch32 (HLT, SEVL, MVN nzcvqg)
	DIV,          // SDIV/UDIV (ARMv7-A optional, ARMv7-R/M mandatory)
	VFPV2,        // VFP version 2 (double-precision FP)
	VFPV3,        // VFP version 3 (D32, VCVTB/T half-prec)
	VFPV4,        // VFP version 4 (VFMA family)
	HALF_FP,      // FP16 storage support
	NEON,         // Advanced SIMD
	NEON_HALF_FP, // FP16 NEON arithmetic
	CRYPTO,       // ARMv8 crypto (AES + SHA1 + SHA2)
	CRC32,        // ARMv8 CRC32B/H/W + CRC32CB/H/W
	DOT,          // ARMv8.2 dot product (VSDOT/VUDOT)
	BF16,         // ARMv8.6 BFloat16
	FCMA,         // ARMv8.3 complex number (VCMLA/VCADD)
	FHM,          // ARMv8.2 FP16 multiply-acc-long
	// ---- M-profile ARMv8-M extensions ----
	V8M,          // ARMv8-M baseline (Cortex-M23, M33, M55, M85)
	V8M_SE,       // ARMv8-M Security Extensions (TT/TTT/TTA/TTAT)
	V81M,         // ARMv8.1-M mainline (low-overhead loops, MVE)
	MVE_INT,      // M-profile Vector Extension (Helium) integer (Cortex-M55+)
	MVE_FP,       // M-profile Vector Extension floating-point
	CDE,          // Custom Datapath Extension (Cortex-M33+)
}

Index_Mode :: enum u8 {
	OFFSET     = 0, // [Rn, #imm]      -- no writeback
	PRE_INDEX  = 1, // [Rn, #imm]!     -- writeback after addr calc
	POST_INDEX = 2, // [Rn], #imm      -- writeback, base = Rn pre-update
}

Instruction :: struct #align (64) {
	// Six, because the coprocessor forms need six: MCR, MRC and CDP are
	// written `mcr p15, #0, r0, c0, c0, #0`, and dropping the last two
	// operands does not merely print short -- an opc2 that is not zero
	// encodes as zero, which is the wrong instruction. Six operands cannot
	// fit alongside the rest in 64 bytes (Operand is 11, and Memory cannot
	// go below 8), so this straddles two cache lines rather than one.
	ops:      [6]Operand `fmt:"v,operand_count"`,
	// 6 * 11 = 66
	mnemonic: Mnemonic,
	// cond, operand_count, mode, length and the two flag bits share one
	// 16-bit word -- together they need 13 bits, and spending six bytes on
	// them was what pushed Instruction over 48. `using` keeps inst.cond,
	// inst.operand_count, inst.mode, inst.length, inst.sets_flags and
	// inst.wide reading and writing exactly as they did as plain fields.
	using _:  bit_field u16 {
		cond:          u8 | 4,
		operand_count: u8 | 3,
		mode:          Mode | 1,
		length:        u8 | 3,
		sets_flags:    bool | 1,
		wide:          bool | 1,
		writeback:     bool | 1,
	},
	// Form-id hint: when non-zero, this is (1 + the index into
	// ENCODING_TABLE[mnemonic]) of the form the decoder produced. The encoder
	// uses it as a tie-breaker for the shape-ambiguous entries the data type
	// does not separate on its own -- register lists, LDM/STM addressing
	// modes. User-constructed instructions leave it at 0 and take the
	// first shape match.
	form_id:  u16,
	// The `.i32` / `.s32.f32` suffix. Zero (.NONE) means "unspecified": the
	// encoder then takes the first form of the matching shape, which is what
	// every instruction did before this field existed. Set it and the encoder
	// picks the encoding for that type.
	dt:       [2]Data_Type,
	// Spare, and free: the operands leave the tail of the second cache line
	// unused either way. New fields land here without changing the layout.
	_:        [54]u8,
}

Instruction_Flags :: distinct bit_field u8 {
	sets_flags: bool | 1,
	wide:       bool | 1,
	_:          u8 | 6,
}

Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}

Label_Definition :: rexcode_isa.Label_Definition

Label_Map :: rexcode_isa.Label_Map

Label_Names :: map[rexcode_isa.Label_Offset]string