package core:rexcode/isa/arm32

Source

Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	mode:     Mode,
	// 1
	flags:    Encoding_Flags,
}

Decode_Index :: struct #packed {
	start: u16,
	count: u16,
}

Encode_Run :: struct {
	start: u32,
	count: u32,
}

Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	mode:     Mode,
	// 1
	flags:    Encoding_Flags,
}

Encoding_Flags :: distinct bit_field u8 {
	sets_flags:  bool | 1,
	cond_in_28:  bool | 1,
	branch:      bool | 1,
	cond_branch: bool | 1,
	writes_pc:   bool | 1,
	thumb32:     bool | 1,
	deprecated:  bool | 1,
	_:           u8 | 1,
}

Error :: rexcode_isa.Error

Error_Code :: rexcode_isa.Error_Code

Feature :: enum u8 {
	BASE,         // ARMv4 base ISA (works on every ARM core including ARM7TDMI / GBA)
	THUMB,        // Thumb-1 (ARMv4T+)
	V5T,          // ARMv5T additions (BLX, CLZ, BKPT)
	V5TE,         // ARMv5TE DSP extensions (SMLAxy / SMULxy / etc.)
	V5TEJ,        // ARMv5TEJ (BXJ; Jazelle support)
	V6,           // ARMv6 SIMD-on-GPR + REV/SXTB/etc.
	V6K,          // ARMv6K (CLREX, multiprocessing hints)
	V6T2,         // ARMv6T2 (Thumb-2, MOVW/MOVT, bitfield)
	V7,           // ARMv7-A/R base (DMB/DSB/ISB, LDREX/STREX full set)
	V7VE,         // ARMv7-A Virtualisation Extensions (HVC, ERET)
	V8,           // ARMv8-A AArch32 (HLT, SEVL, MVN nzcvqg)
	DIV,          // SDIV/UDIV (ARMv7-A optional, ARMv7-R/M mandatory)
	VFPV2,        // VFP version 2 (double-precision FP)
	VFPV3,        // VFP version 3 (D32, VCVTB/T half-prec)
	VFPV4,        // VFP version 4 (VFMA family)
	HALF_FP,      // FP16 storage support
	NEON,         // Advanced SIMD
	NEON_HALF_FP, // FP16 NEON arithmetic
	CRYPTO,       // ARMv8 crypto (AES + SHA1 + SHA2)
	CRC32,        // ARMv8 CRC32B/H/W + CRC32CB/H/W
	DOT,          // ARMv8.2 dot product (VSDOT/VUDOT)
	BF16,         // ARMv8.6 BFloat16
	FCMA,         // ARMv8.3 complex number (VCMLA/VCADD)
	FHM,          // ARMv8.2 FP16 multiply-acc-long
	// ---- M-profile ARMv8-M extensions ----
	V8M,          // ARMv8-M baseline (Cortex-M23, M33, M55, M85)
	V8M_SE,       // ARMv8-M Security Extensions (TT/TTT/TTA/TTAT)
	V81M,         // ARMv8.1-M mainline (low-overhead loops, MVE)
	MVE_INT,      // M-profile Vector Extension (Helium) integer (Cortex-M55+)
	MVE_FP,       // M-profile Vector Extension floating-point
	CDE,          // Custom Datapath Extension (Cortex-M33+)
}

Index_Mode :: enum u8 {
	OFFSET     = 0, // [Rn, #imm]      -- no writeback
	PRE_INDEX  = 1, // [Rn, #imm]!     -- writeback after addr calc
	POST_INDEX = 2, // [Rn], #imm      -- writeback, base = Rn pre-update
}

Instruction :: struct #packed {
	ops:           [4]Operand `fmt:"v,operand_count"`,
	// 4 * 18 = 68
	mnemonic:      Mnemonic,
	// 2
	cond:          u8,
	// 0..15 (AL=14)
	operand_count: u8,
	// 0..4
	flags:         Instruction_Flags,
	// 1
	mode:          Mode,
	// 1 (A32 or T32)
	length:        u8,
	// Form-id hint: when non-zero, this is (1 + the index into
	// ENCODING_TABLE[mnemonic]) of the form the decoder produced. The encoder
	// uses it as a tie-breaker for shape-ambiguous entries (NEON size variants
	// share an operand shape but live in distinct entries with different fixed
	// bits). User-constructed instructions leave it at 0; the encoder then
	// falls back to first-shape-match. Stored as u16 over the two padding bytes.
	form_id:       u16,
	_:             [7]u8,
}

Instruction_Flags :: distinct bit_field u8 {
	sets_flags: bool | 1,
	wide:       bool | 1,
	_:          u8 | 6,
}

Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}

Label_Definition :: rexcode_isa.Label_Definition

Label_Map :: rexcode_isa.Label_Map

Memory :: struct #packed {
	base:       Register,
	// GPR base register
	index:      Register,
	// GPR or .NONE for imm-only forms
	shift_type: Shift_Type,
	shift_amt:  u8,
	// 0..31 immediate shift
	mode:       Index_Mode,
	sign:       i8,
	disp:       i32,
}