package core:rexcode/isa/riscv

Source

Alias_Src :: enum u8 {
	NONE,    // slot unused
	ARG0,    // user's 1st operand
	ARG1,    // user's 2nd operand
	ARG2,    // user's 3rd operand
	X0,      // hardwired zero (x0)
	X1,      // link register (ra / x1)
	LIT,     // the `lit` field below (immediate literal)
	CSR_LIT, // the `csr` field below (fixed 12-bit CSR address)
}

Clobber :: struct {
	written:      Operand_Set,
	// operand slots whose register/CSR is written
	read:         Operand_Set,
	// operand slots whose register/CSR/mem-base is read
	implicit_wr:  Clobber_Regs,
	// implicit reg writes (ra on C.JAL/C.JALR)
	implicit_rd:  Clobber_Regs,
	// implicit reg reads (sp on the *SP forms)
	fflags_wr:    FFlags,
	// accrued exception flags this op may raise
	reads_frm:    bool,
	// consumes the dynamic rounding mode from fcsr
	writes_mem:   bool,
	reads_mem:    bool,
	side_effects: Side_Effects,
}

Clobber_Reg :: enum u8 {
	RA, // x1, implicit link on C.JAL / C.JALR
	SP, // x2, implicit base on the *SP compressed forms
}

Clobber_Regs :: distinct bit_set[Clobber_Reg; u8]

Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	flags:    Encoding_Flags,
}

Decode_Index :: struct #packed {
	start: u16,
	count: u16,
}

Encode_Run :: struct {
	start: u32,
	count: u32,
}

Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	flags:    Encoding_Flags,
}

Encoding_Flags :: distinct bit_field u8 {
	rv32_only:      bool | 1,
	rv64_only:      bool | 1,
	branch:         bool | 1,
	fp_round:       bool | 1,
	explicit_count: u8 | 3,
	has_implicit:   bool | 1,
}

Error :: rexcode_isa.Error

Error_Code :: rexcode_isa.Error_Code

FFlag :: enum u8 {
	NV, // invalid operation
	DZ, // divide by zero
	OF, // overflow
	UF, // underflow
	NX, // inexact
}

FFlags :: distinct bit_set[FFlag; u8]

FPR :: enum u8 {
	FT0  = 0, 
	FT1  = 1, 
	FT2  = 2, 
	FT3  = 3, 
	FT4  = 4, 
	FT5  = 5, 
	FT6  = 6, 
	FT7  = 7, 
	FS0  = 8, 
	FS1  = 9, 
	FA0  = 10, 
	FA1  = 11, 
	FA2  = 12, 
	FA3  = 13, 
	FA4  = 14, 
	FA5  = 15, 
	FA6  = 16, 
	FA7  = 17, 
	FS2  = 18, 
	FS3  = 19, 
	FS4  = 20, 
	FS5  = 21, 
	FS6  = 22, 
	FS7  = 23, 
	FS8  = 24, 
	FS9  = 25, 
	FS10 = 26, 
	FS11 = 27, 
	FT8  = 28, 
	FT9  = 29, 
	FT10 = 30, 
	FT11 = 31, 
}

Feature :: enum u16 {
	I,        // RV32I / RV64I base integer
	M,        // multiply / divide
	A,        // atomics
	F,        // single-precision FP
	D,        // double-precision FP
	ZICSR,    // CSR access (CSRRW/S/C + immediate forms)
	ZIFENCEI, // FENCE.I (instruction-fetch fence)
	C,        // 16-bit compressed instructions
	ZBA,      // address-generation bit-manip
	ZBB,      // basic bit-manip
	ZBC,      // carry-less multiply
	ZBS,      // single-bit bit-manip
	ZICOND,   // conditional zeroing
	ZFH,      // half-precision (binary16) FP
	PRIV,     // privileged trap-return / TLB maintenance
}

GPR :: enum u8 {
	ZERO = 0, 
	RA   = 1, 
	SP   = 2, 
	GP   = 3, 
	TP   = 4, 
	T0   = 5, 
	T1   = 6, 
	T2   = 7, 
	S0   = 8, 
	S1   = 9, 
	A0   = 10, 
	A1   = 11, 
	A2   = 12, 
	A3   = 13, 
	A4   = 14, 
	A5   = 15, 
	A6   = 16, 
	A7   = 17, 
	S2   = 18, 
	S3   = 19, 
	S4   = 20, 
	S5   = 21, 
	S6   = 22, 
	S7   = 23, 
	S8   = 24, 
	S9   = 25, 
	S10  = 26, 
	S11  = 27, 
	T3   = 28, 
	T4   = 29, 
	T5   = 30, 
	T6   = 31, 
}

Instruction :: struct #packed {
	ops:           [4]Operand `fmt:"v,operand_count"`,
	// 40 bytes
	mnemonic:      Mnemonic,
	// 2
	operand_count: u8,
	// 1
	flags:         Instruction_Flags,
	// 1
	length:        u8,
	// 1 -- always 4 for non-C
	_:             [3]u8,
}

Instruction_Flags :: distinct bit_field u8 {
	_: u8 | 8,
}

Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}

Label_Definition :: rexcode_isa.Label_Definition

Label_Map :: rexcode_isa.Label_Map

Label_Names :: map[rexcode_isa.Label_Offset]string

Label_Offset :: rexcode_isa.Label_Offset

Memory :: struct #packed {
	base: Register,
	// GPR base
	_:    u16,
	disp: i32,
}

Mnemonic :: enum u16 {
	INVALID    = 0, 
	// Upper-immediate
	LUI, 
	AUIPC, 
	// Jumps
	JAL, 
	JALR, 
	// Branches
	BEQ, 
	BNE, 
	BLT, 
	BGE, 
	BLTU, 
	BGEU, 
	// Loads / stores
	LB, 
	LH, 
	LW, 
	LBU, 
	LHU, 
	SB, 
	SH, 
	SW, 
	LWU, 
	LD,             // RV64-only
	SD,             // RV64-only
	// Integer reg-imm
	ADDI, 
	SLTI, 
	SLTIU, 
	XORI, 
	ORI, 
	ANDI, 
	SLLI, 
	SRLI, 
	SRAI,           // shift-immediate (5-bit shamt RV32; 6-bit RV64)
	ADDIW, 
	SLLIW, 
	SRLIW, 
	SRAIW,          // RV64-only (32-bit ops)
	// Integer reg-reg
	ADD, 
	SUB, 
	SLL, 
	SLT, 
	SLTU, 
	XOR, 
	SRL, 
	SRA, 
	OR, 
	AND, 
	ADDW, 
	SUBW, 
	SLLW, 
	SRLW, 
	SRAW,           // RV64-only
	// Memory ordering
	FENCE, 
	FENCE_I, 
	// System
	ECALL, 
	EBREAK, 
	CSRRW, 
	CSRRS, 
	CSRRC, 
	CSRRWI, 
	CSRRSI, 
	CSRRCI, 
	MUL, 
	MULH, 
	MULHSU, 
	MULHU, 
	DIV, 
	DIVU, 
	REM, 
	REMU, 
	MULW, 
	DIVW, 
	DIVUW, 
	REMW, 
	REMUW,          // RV64-only
	LR_W, 
	SC_W, 
	AMOSWAP_W, 
	AMOADD_W, 
	AMOXOR_W, 
	AMOAND_W, 
	AMOOR_W, 
	AMOMIN_W, 
	AMOMAX_W, 
	AMOMINU_W, 
	AMOMAXU_W, 
	LR_D, 
	SC_D,           // RV64-only
	AMOSWAP_D, 
	AMOADD_D, 
	AMOXOR_D, 
	AMOAND_D, 
	AMOOR_D, 
	AMOMIN_D, 
	AMOMAX_D, 
	AMOMINU_D, 
	AMOMAXU_D, 
	FLW, 
	FSW, 
	FMADD_S, 
	FMSUB_S, 
	FNMSUB_S, 
	FNMADD_S, 
	FADD_S, 
	FSUB_S, 
	FMUL_S, 
	FDIV_S, 
	FSQRT_S, 
	FSGNJ_S, 
	FSGNJN_S, 
	FSGNJX_S, 
	FMIN_S, 
	FMAX_S, 
	FCVT_W_S, 
	FCVT_WU_S, 
	FMV_X_W, 
	FEQ_S, 
	FLT_S, 
	FLE_S, 
	FCLASS_S, 
	FCVT_S_W, 
	FCVT_S_WU, 
	FMV_W_X, 
	FCVT_L_S, 
	FCVT_LU_S, 
	FCVT_S_L, 
	FCVT_S_LU,      // RV64F
	FLD, 
	FSD, 
	FMADD_D, 
	FMSUB_D, 
	FNMSUB_D, 
	FNMADD_D, 
	FADD_D, 
	FSUB_D, 
	FMUL_D, 
	FDIV_D, 
	FSQRT_D, 
	FSGNJ_D, 
	FSGNJN_D, 
	FSGNJX_D, 
	FMIN_D, 
	FMAX_D, 
	FCVT_S_D, 
	FCVT_D_S, 
	FEQ_D, 
	FLT_D, 
	FLE_D, 
	FCLASS_D, 
	FCVT_W_D, 
	FCVT_WU_D, 
	FCVT_D_W, 
	FCVT_D_WU, 
	FCVT_L_D, 
	FCVT_LU_D, 
	FCVT_D_L, 
	FCVT_D_LU,      // RV64D
	FMV_X_D, 
	FMV_D_X,        // RV64D
	// -------------------------------------------------------------------------
	// C extension (16-bit compressed). Each C.* mnemonic expands semantically
	// to a 32-bit base ISA instruction; the encoder picks the compressed
	// form by mnemonic.
	// -------------------------------------------------------------------------
	C_NOP, 
	C_EBREAK, 
	C_ADDI4SPN,     // rd', sp, imm
	C_LW, 
	C_LD, 
	C_SW, 
	C_SD,           // (RV64 LD/SD; RV32 has LW/SW)
	C_FLW, 
	C_FSW, 
	C_FLD, 
	C_FSD,          // double-precision FP load/store
	C_ADDI, 
	C_ADDIW, 
	C_LI, 
	C_LUI, 
	C_ADDI16SP,     // sp, imm
	C_SRLI, 
	C_SRAI, 
	C_ANDI, 
	C_SUB, 
	C_XOR, 
	C_OR, 
	C_AND, 
	C_SUBW, 
	C_ADDW,         // RV64-only
	C_J, 
	C_JAL,          // C.JAL is RV32-only; RV64 has C.ADDIW
	C_BEQZ, 
	C_BNEZ, 
	C_SLLI, 
	C_LWSP, 
	C_LDSP, 
	C_SWSP, 
	C_SDSP, 
	C_FLDSP, 
	C_FSDSP, 
	C_JR, 
	C_JALR, 
	C_MV, 
	C_ADD, 
	C_FLWSP, 
	C_FSWSP, 
	SH1ADD, 
	SH2ADD, 
	SH3ADD, 
	ADD_UW, 
	SH1ADD_UW, 
	SH2ADD_UW, 
	SH3ADD_UW, 
	SLLI_UW, 
	ANDN, 
	ORN, 
	XNOR, 
	CLZ, 
	CTZ, 
	CPOP, 
	SEXT_B, 
	SEXT_H, 
	ZEXT_H, 
	MIN, 
	MINU, 
	MAX, 
	MAXU, 
	ROL, 
	ROR, 
	RORI, 
	ORC_B, 
	REV8, 
	CLZW, 
	CTZW, 
	CPOPW, 
	ROLW, 
	RORW, 
	RORIW, 
	CLMUL, 
	CLMULH, 
	CLMULR, 
	BCLR, 
	BCLRI, 
	BEXT, 
	BEXTI, 
	BINV, 
	BINVI, 
	BSET, 
	BSETI, 
	CZERO_EQZ, 
	CZERO_NEZ, 
	FLH, 
	FSH, 
	FMADD_H, 
	FMSUB_H, 
	FNMSUB_H, 
	FNMADD_H, 
	FADD_H, 
	FSUB_H, 
	FMUL_H, 
	FDIV_H, 
	FSQRT_H, 
	FSGNJ_H, 
	FSGNJN_H, 
	FSGNJX_H, 
	FMIN_H, 
	FMAX_H, 
	FCVT_W_H, 
	FCVT_WU_H, 
	FCVT_L_H, 
	FCVT_LU_H, 
	FCVT_H_W, 
	FCVT_H_WU, 
	FCVT_H_L, 
	FCVT_H_LU, 
	FCVT_S_H, 
	FCVT_H_S, 
	FCVT_D_H, 
	FCVT_H_D, 
	FMV_X_H, 
	FMV_H_X, 
	FCLASS_H, 
	FEQ_H, 
	FLT_H, 
	FLE_H, 
	MRET, 
	SRET, 
	WFI, 
	SFENCE_VMA, 
}

Operand :: struct #packed {
	using _: struct #raw_union {
		reg:       Register,
		// REGISTER (int or FP)
		mem:       Memory,
		immediate: i64,
		relative:  i64,
	},
	kind: Operand_Kind,
	size: u8,
}

Operand_Encoding :: enum u8 {
	NONE, 
	RD,              // bits 11-7   (any register, int or FP)
	RS1,             // bits 19-15
	RS2,             // bits 24-20
	RS3,             // bits 31-27  (R4-type, FMADD/FMSUB/FNMADD/FNMSUB)
	SHAMT5,          // bits 24-20  (5-bit shift)
	SHAMT6,          // bits 25-20  (6-bit shift, RV64 long shifts)
	IMM_I,           // bits 31-20  (signed I-type 12-bit)
	IMM_S,           // bits 31-25 || 11-7  (S-type scatter)
	IMM_B,           // B-type scatter: imm[12] @31, [10:5] @30-25, [4:1] @11-8, [11] @7
	IMM_U,           // bits 31-12  (U-type 20-bit upper)
	IMM_J,           // J-type scatter: imm[20] @31, [10:1] @30-21, [11] @20, [19:12] @19-12
	OFFSET_BASE_I,   // memory: rs1 @bits 19-15 + IMM_I disp (loads, JALR, FLW, FLD)
	OFFSET_BASE_S,   // memory: rs1 @bits 19-15 + IMM_S disp (stores, FSW, FSD)
	OFFSET_BASE_A,   // memory: rs1 @bits 19-15 only (atomics; disp must be 0)
	CSR_FIELD,       // bits 31-20  (12-bit CSR address)
	ZIMM_FIELD,      // bits 19-15  (zero-extended 5-bit imm; replaces rs1 in CSRRxI)
	FENCE_PRED,      // bits 27-24
	FENCE_SUCC,      // bits 23-20
	ROUND_FIELD,     // bits 14-12  (funct3 doubles as rm)
	AQRL,            // bits 26-25  (atomic acquire/release)
	// ---- C extension (compressed; bits fit in low 16 of the word) ----
	C_RD_RS1,        // bits 11-7  (CR/CI shared rd/rs1 slot)
	C_RS2,           // bits  6-2  (CR rs2)
	C_RD_PRIMED,     // bits  4-2  (CIW/CL/CB rd' encoded as x8+field)
	C_RS1_PRIMED,    // bits  9-7  (CL/CS/CA/CB rs1' encoded as x8+field)
	C_RS2_PRIMED,    // bits  4-2  (CS/CA rs2' encoded as x8+field)
	C_RD_RS1_PRIMED, // bits  9-7  (CA rd'/rs1' encoded as x8+field)
	C_IMM_CI_S,      // bits 12 || 6-2  (signed 6-bit CI imm)
	C_IMM_CI_U,      // bits 12 || 6-2  (unsigned 6-bit CI imm; SLLI shamt)
	C_IMM_CIW,       // bits 12-5  (C.ADDI4SPN: scrambled to imm[9:2])
	C_IMM_LUI,       // bits 12 || 6-2 (C.LUI: imm[17] || imm[16:12])
	C_IMM_ADDI16SP,  // bits 12,4,3,5,2,6  -> imm[9,4,6,8:7,5]
	C_IMM_CSS_W,     // bits 12-7  -> imm[5:2,7:6] (C.SWSP scaled by 4)
	C_IMM_CSS_D,     // bits 12-7  -> imm[5:3,8:6] (C.SDSP scaled by 8)
	C_IMM_CL_W,      // bits 12-10 || 6-5 -> imm[5:3,2,6] (C.LW/C.SW scaled by 4)
	C_IMM_CL_D,      // bits 12-10 || 6-5 -> imm[5:3,7:6] (C.LD/C.SD scaled by 8)
	C_BRANCH9,       // C.BEQZ/BNEZ: scatter to bits 12 || 10:9,2,7:6,5:4 || 11
	C_BRANCH12,      // C.J/C.JAL: scatter to bits 12 || 8 || 10:9 || 6 || 7 || 2 || 11 || 5:3 -> imm[11,4,9:8,10,6,7,3:1,5]
	C_OFFSET_BASE_W, // memory: rs1' at 9-7 + scaled-by-4 imm at 12-10 || 6-5
	C_OFFSET_BASE_D, // memory: rs1' at 9-7 + scaled-by-8 imm at 12-10 || 6-5
	C_SP_OFFSET_W,   // SP-relative: rd at 11-7 + scaled-by-4 imm at 12 || 6:4 || 3:2 -> imm[5,4:2,7:6]
	C_SP_OFFSET_D,   // SP-relative: rd at 11-7 + scaled-by-8 imm at 12 || 6:5 || 4:2 -> imm[5,4:3,8:6]
}

Operand_Kind :: enum u8 {
	NONE, 
	REGISTER,  // mostly used for `A` in `ROL A` (implicit; rarely needed)
	IMMEDIATE, 
	MEMORY, 
	RELATIVE,  // PC-relative target (label or raw byte offset)
}

Operand_Set :: distinct bit_set[int; u8]

Operand_Type :: enum u8 {
	NONE, 
	GPR, 
	FPR, 
	IMM12,       // signed 12-bit I-type immediate (ADDI/LOADS/JALR/...)
	IMM12U,      // unsigned 12-bit (CSR address; some pseudo-uses)
	IMM5,        // 5-bit shift amount (RV32 shifts; SLLIW/SRLIW/SRAIW)
	IMM6,        // 6-bit shift amount (RV64 SLLI/SRLI/SRAI)
	IMM20,       // 20-bit U-type immediate (LUI, AUIPC)
	REL13,       // 13-bit branch target (label or signed byte offset)
	REL21,       // 21-bit jump target (label or signed byte offset)
	MEM,         // base + signed 12-bit displacement
	CSR,         // 12-bit CSR address
	FENCE_FLAGS, // 4-bit pred or succ mask (for FENCE)
	ROUND_MODE,  // 3-bit FP rounding mode
	ZIMM5,       // 5-bit zero-extended immediate (CSRRWI/SI/CI)
	// ---- C extension (compressed) ----
	GPR_C,       // "primed" 3-bit register (x8..x15 only)
	GPR_SP,      // hardwired SP (x2) for C.ADDI16SP / C.LWSP / C.SWSP
	GPR_NONZERO, // GPR with hw != 0 (C.ADDI/C.LI/C.MV/etc. forbid x0)
	FPR_C,       // primed FP register (f8..f15 only)
	IMM_C6S,     // CI-form signed 6-bit (C.ADDI/C.LI)
	IMM_C6U,     // CI-form unsigned 6-bit (C.SLLI/SRLI/SRAI shamt)
	IMM_C8U,     // CIW-form 8-bit unsigned scaled (C.ADDI4SPN)
	IMM_C10S,    // C.ADDI16SP 10-bit signed scaled by 16
	IMM_C18S,    // C.LUI 18-bit signed scaled by 4096
	REL9,        // 9-bit signed PC-rel branch (C.BEQZ/BNEZ)
	REL12,       // 12-bit signed PC-rel jump (C.J/C.JAL)
	MEM_C_W,     // memory for C.LW/C.SW (rs1' + scaled imm by 4)
	MEM_C_D,     // memory for C.LD/C.SD (rs1' + scaled imm by 8)
	MEM_C_SP_W,  // SP-relative for C.LWSP/C.SWSP (scaled by 4)
	MEM_C_SP_D,  // SP-relative for C.LDSP/C.SDSP (scaled by 8)
}

Print_Options :: rexcode_isa.Print_Options

Print_Result :: rexcode_isa.Print_Result

Pseudo_Alias :: struct {
	target:    Mnemonic,
	// real instruction emitted
	src:       [4]Alias_Src,
	// how to fill target's four operand slots
	lit:       i16,
	// immediate when a src slot is .LIT
	csr:       u16,
	// CSR address when a src slot is .CSR_LIT
	nargs:     u8,
	// operands the user supplies (ARG0..<ARGn)
	rv32_only: bool,
}

Pseudo_Mnemonic :: enum u16 {
	INVALID, 
	// integer moves / arithmetic
	NOP, 
	MV, 
	NOT, 
	NEG, 
	NEGW, 
	SEXT_W, 
	ZEXT_B, 
	// set-if / compare-to-zero
	SEQZ, 
	SNEZ, 
	SLTZ, 
	SGTZ, 
	// branch-on-zero
	BEQZ, 
	BNEZ, 
	BLEZ, 
	BGEZ, 
	BLTZ, 
	BGTZ, 
	// branch with swapped operands
	BGT, 
	BLE, 
	BGTU, 
	BLEU, 
	// jumps
	J, 
	JAL_RA, 
	JR, 
	JALR_RA, 
	RET, 
	// generic CSR access
	CSRR, 
	CSRW, 
	CSRS, 
	CSRC, 
	CSRWI, 
	CSRSI, 
	CSRCI, 
	// named counter reads (CSR baked in)
	RDCYCLE, 
	RDTIME, 
	RDINSTRET, 
	RDCYCLEH, 
	RDTIMEH, 
	RDINSTRETH, 
	// fcsr / frm / fflags accessors
	FRCSR, 
	FSCSR, 
	FRRM, 
	FSRM, 
	FRFLAGS, 
	FSFLAGS, 
	FSRMI, 
	FSFLAGSI, 
	// FP sign-injection moves
	FMV_S, 
	FABS_S, 
	FNEG_S, 
	FMV_D, 
	FABS_D, 
	FNEG_D, 
	FMV_H, 
	FABS_H, 
	FNEG_H, 
	// memory ordering
	FENCE_ALL, 
}

Register :: distinct u16

Relocation :: struct #packed {
	offset:   u32,
	label_id: u32,
	addend:   i32,
	type:     Relocation_Type,
	size:     u8,
	inst_idx: u16,
}

Relocation_Type :: enum u8 {
	NONE         = 0, 
	// PC-relative branches and jumps
	BRANCH,           // 13-bit signed PC-rel, B-type scatter (BEQ/BNE/...)
	JAL,              // 21-bit signed PC-rel, J-type scatter (JAL)
	// PC-relative paired (AUIPC + ADDI/load/store)
	PCREL_HI20,       // upper 20 bits of (sym - pc), U-type
	PCREL_LO12_I,     // lower 12 bits, I-type form
	PCREL_LO12_S,     // lower 12 bits, S-type form
	// Absolute paired (LUI + ADDI/load/store)
	HI20,             // upper 20 of absolute, U-type
	LO12_I,           // lower 12, I-type
	LO12_S,           // lower 12, S-type
	// Helpful aggregate forms (the assembler can expand)
	CALL,             // AUIPC + JALR pair to call a far symbol
	// ---- C extension PC-relative ----
	C_BRANCH,         // 9-bit signed PC-rel for C.BEQZ / C.BNEZ
	C_JUMP,           // 12-bit signed PC-rel for C.J / C.JAL
}

Side_Effect :: enum u8 {
	CONTROL,     // writes pc: branches, jumps, and trap redirects
	TRAP,        // synchronous environment trap (ECALL / EBREAK)
	FENCE,       // explicit memory-ordering barrier (FENCE)
	IFENCE,      // instruction-fetch synchronization (FENCE.I)
	ATOMIC,      // indivisible memory RMW (AMO*, and the LR/SC pair)
	RESERVATION, // sets or tests an LR/SC reservation
}

Side_Effects :: distinct bit_set[Side_Effect; u8]

Token :: rexcode_isa.Token

Token_Kind :: rexcode_isa.Token_Kind

XLEN :: enum u8 {
	RV32, 
	RV64, 
}

@(rodata)
CLOBBER_FORMS: []Clobber = …

@(rodata)
DECODE_ENTRIES: []Decode_Entry = …

@(rodata)
DECODE_INDEX_OPCODE: []Decode_Index = …

@(rodata)
DECODE_INDEX_OP_FP: []Decode_Index = …

@(rodata)
DECODE_INDEX_RVC: []Decode_Index = …

@(rodata)
ENCODE_FORMS: []Encoding = …

@(rodata)
ENCODE_RUNS: []Encode_Run = …

@(rodata)
PSEUDO_ALIASES: [Pseudo_Mnemonic]Pseudo_Alias = …