package core:rexcode/isa/riscv
Source

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    Overview

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    rexcode · Brendan Punsky (dotbmp@github), original author

    Index

    Procedures (827)
    Procedure Groups (0)

    This section is empty.

    Types

    Decode_Entry ¶
    Source

    Decode_Entry :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	flags:    Encoding_Flags,
}

    Decode_Index ¶
    Source

    Decode_Index :: struct #packed {
	start: u16,
	count: u16,
}

    Encode_Run ¶
    Source

    Encode_Run :: struct {
	start: u32,
	count: u32,
}
     

    Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS.

    Encoding ¶
    Source

    Encoding :: struct #packed {
	mnemonic: Mnemonic,
	// 2
	ops:      [4]Operand_Type,
	// 4
	enc:      [4]Operand_Encoding,
	// 4
	bits:     u32,
	// 4
	mask:     u32,
	// 4
	feature:  Feature,
	// 1
	flags:    Encoding_Flags,
}

    Encoding_Flags ¶
    Source

    Encoding_Flags :: distinct bit_field u8 {
	rv32_only: bool | 1,
	rv64_only: bool | 1,
	branch:    bool | 1,
	fp_round:  bool | 1,
	_:         u8 | 4,
}

    Error ¶
    Source

    Error :: rexcode_isa.Error

    Error_Code ¶
    Source

    Error_Code :: rexcode_isa.Error_Code

    FPR ¶
    Source

    FPR :: enum u8 {
	FT0  = 0, 
	FT1  = 1, 
	FT2  = 2, 
	FT3  = 3, 
	FT4  = 4, 
	FT5  = 5, 
	FT6  = 6, 
	FT7  = 7, 
	FS0  = 8, 
	FS1  = 9, 
	FA0  = 10, 
	FA1  = 11, 
	FA2  = 12, 
	FA3  = 13, 
	FA4  = 14, 
	FA5  = 15, 
	FA6  = 16, 
	FA7  = 17, 
	FS2  = 18, 
	FS3  = 19, 
	FS4  = 20, 
	FS5  = 21, 
	FS6  = 22, 
	FS7  = 23, 
	FS8  = 24, 
	FS9  = 25, 
	FS10 = 26, 
	FS11 = 27, 
	FT8  = 28, 
	FT9  = 29, 
	FT10 = 30, 
	FT11 = 31, 
}
    Related Procedures With Parameters

    Feature ¶
    Source

    Feature :: enum u8 {
	I,        // RV32I / RV64I base integer
	M,        // multiply / divide
	A,        // atomics
	F,        // single-precision FP
	D,        // double-precision FP
	ZICSR,    // CSR access (CSRRW/S/C + immediate forms)
	ZIFENCEI, // FENCE.I (instruction-fetch fence)
	C,        // 16-bit compressed instructions
}
     

    Extension this entry belongs to (metadata, not used by the matcher).

    GPR ¶
    Source

    GPR :: enum u8 {
	ZERO = 0, 
	RA   = 1, 
	SP   = 2, 
	GP   = 3, 
	TP   = 4, 
	T0   = 5, 
	T1   = 6, 
	T2   = 7, 
	S0   = 8, 
	S1   = 9, 
	A0   = 10, 
	A1   = 11, 
	A2   = 12, 
	A3   = 13, 
	A4   = 14, 
	A5   = 15, 
	A6   = 16, 
	A7   = 17, 
	S2   = 18, 
	S3   = 19, 
	S4   = 20, 
	S5   = 21, 
	S6   = 22, 
	S7   = 23, 
	S8   = 24, 
	S9   = 25, 
	S10  = 26, 
	S11  = 27, 
	T3   = 28, 
	T4   = 29, 
	T5   = 30, 
	T6   = 31, 
}
    Related Procedures With Parameters
    Related Constants

    Instruction ¶
    Source

    Instruction :: struct #packed {
	ops:           [4]Operand `fmt:"v,operand_count"`,
	// 40 bytes
	mnemonic:      Mnemonic,
	// 2
	operand_count: u8,
	// 1
	flags:         Instruction_Flags,
	// 1
	length:        u8,
	// 1 -- always 4 for non-C
	_:             [3]u8,
}
    Related Procedures With Returns

    Instruction_Flags ¶
    Source

    Instruction_Flags :: distinct bit_field u8 {
	_: u8 | 8,
}

    Instruction_Info ¶
    Source

    Instruction_Info :: struct {
	offset:       u32,
	decode_entry: u16,
	_:            u16,
}

    Label_Definition ¶
    Source

    Label_Definition :: rexcode_isa.Label_Definition
    Related Constants

    Label_Map ¶
    Source

    Label_Map :: rexcode_isa.Label_Map

    Memory ¶
    Source

    Memory :: struct #packed {
	base: Register,
	// GPR base
	_:    u16,
	disp: i32,
}
    Related Procedures With Parameters
    Related Procedures With Returns

    Mnemonic ¶
    Source

    Mnemonic :: enum u16 {
	INVALID    = 0, 
	// Upper-immediate
	LUI, 
	AUIPC, 
	// Jumps
	JAL, 
	JALR, 
	// Branches
	BEQ, 
	BNE, 
	BLT, 
	BGE, 
	BLTU, 
	BGEU, 
	// Loads / stores
	LB, 
	LH, 
	LW, 
	LBU, 
	LHU, 
	SB, 
	SH, 
	SW, 
	LWU, 
	LD,             // RV64-only
	SD,             // RV64-only
	// Integer reg-imm
	ADDI, 
	SLTI, 
	SLTIU, 
	XORI, 
	ORI, 
	ANDI, 
	SLLI, 
	SRLI, 
	SRAI,           // shift-immediate (5-bit shamt RV32; 6-bit RV64)
	ADDIW, 
	SLLIW, 
	SRLIW, 
	SRAIW,          // RV64-only (32-bit ops)
	// Integer reg-reg
	ADD, 
	SUB, 
	SLL, 
	SLT, 
	SLTU, 
	XOR, 
	SRL, 
	SRA, 
	OR, 
	AND, 
	ADDW, 
	SUBW, 
	SLLW, 
	SRLW, 
	SRAW,           // RV64-only
	// Memory ordering
	FENCE, 
	FENCE_I, 
	// System
	ECALL, 
	EBREAK, 
	CSRRW, 
	CSRRS, 
	CSRRC, 
	CSRRWI, 
	CSRRSI, 
	CSRRCI, 
	MUL, 
	MULH, 
	MULHSU, 
	MULHU, 
	DIV, 
	DIVU, 
	REM, 
	REMU, 
	MULW, 
	DIVW, 
	DIVUW, 
	REMW, 
	REMUW,          // RV64-only
	LR_W, 
	SC_W, 
	AMOSWAP_W, 
	AMOADD_W, 
	AMOXOR_W, 
	AMOAND_W, 
	AMOOR_W, 
	AMOMIN_W, 
	AMOMAX_W, 
	AMOMINU_W, 
	AMOMAXU_W, 
	LR_D, 
	SC_D,           // RV64-only
	AMOSWAP_D, 
	AMOADD_D, 
	AMOXOR_D, 
	AMOAND_D, 
	AMOOR_D, 
	AMOMIN_D, 
	AMOMAX_D, 
	AMOMINU_D, 
	AMOMAXU_D, 
	FLW, 
	FSW, 
	FMADD_S, 
	FMSUB_S, 
	FNMSUB_S, 
	FNMADD_S, 
	FADD_S, 
	FSUB_S, 
	FMUL_S, 
	FDIV_S, 
	FSQRT_S, 
	FSGNJ_S, 
	FSGNJN_S, 
	FSGNJX_S, 
	FMIN_S, 
	FMAX_S, 
	FCVT_W_S, 
	FCVT_WU_S, 
	FMV_X_W, 
	FEQ_S, 
	FLT_S, 
	FLE_S, 
	FCLASS_S, 
	FCVT_S_W, 
	FCVT_S_WU, 
	FMV_W_X, 
	FCVT_L_S, 
	FCVT_LU_S, 
	FCVT_S_L, 
	FCVT_S_LU,      // RV64F
	FLD, 
	FSD, 
	FMADD_D, 
	FMSUB_D, 
	FNMSUB_D, 
	FNMADD_D, 
	FADD_D, 
	FSUB_D, 
	FMUL_D, 
	FDIV_D, 
	FSQRT_D, 
	FSGNJ_D, 
	FSGNJN_D, 
	FSGNJX_D, 
	FMIN_D, 
	FMAX_D, 
	FCVT_S_D, 
	FCVT_D_S, 
	FEQ_D, 
	FLT_D, 
	FLE_D, 
	FCLASS_D, 
	FCVT_W_D, 
	FCVT_WU_D, 
	FCVT_D_W, 
	FCVT_D_WU, 
	FCVT_L_D, 
	FCVT_LU_D, 
	FCVT_D_L, 
	FCVT_D_LU,      // RV64D
	FMV_X_D, 
	FMV_D_X,        // RV64D
	// -------------------------------------------------------------------------
	// C extension (16-bit compressed). Each C.* mnemonic expands semantically
	// to a 32-bit base ISA instruction; the encoder picks the compressed
	// form by mnemonic.
	// -------------------------------------------------------------------------
	C_NOP, 
	C_EBREAK, 
	C_ADDI4SPN,     // rd', sp, imm
	C_LW, 
	C_LD, 
	C_SW, 
	C_SD,           // (RV64 LD/SD; RV32 has LW/SW)
	C_FLD, 
	C_FSD,          // double-precision FP load/store
	C_ADDI, 
	C_ADDIW, 
	C_LI, 
	C_LUI, 
	C_ADDI16SP,     // sp, imm
	C_SRLI, 
	C_SRAI, 
	C_ANDI, 
	C_SUB, 
	C_XOR, 
	C_OR, 
	C_AND, 
	C_SUBW, 
	C_ADDW,         // RV64-only
	C_J, 
	C_JAL,          // C.JAL is RV32-only; RV64 has C.ADDIW
	C_BEQZ, 
	C_BNEZ, 
	C_SLLI, 
	C_LWSP, 
	C_LDSP, 
	C_SWSP, 
	C_SDSP, 
	C_FLDSP, 
	C_FSDSP, 
	C_JR, 
	C_JALR, 
	C_MV, 
	C_ADD, 
}
    Related Procedures With Parameters

    Operand ¶
    Source

    Operand :: struct #packed {
	using _: struct #raw_union {
		reg:       Register,
		// REGISTER (int or FP)
		mem:       Memory,
		immediate: i64,
		relative:  i64,
	},
	kind: Operand_Kind,
	size: u8,
}
    Related Procedures With Returns

    Operand_Encoding ¶
    Source

    Operand_Encoding :: enum u8 {
	NONE, 
	RD,              // bits 11-7   (any register, int or FP)
	RS1,             // bits 19-15
	RS2,             // bits 24-20
	RS3,             // bits 31-27  (R4-type, FMADD/FMSUB/FNMADD/FNMSUB)
	SHAMT5,          // bits 24-20  (5-bit shift)
	SHAMT6,          // bits 25-20  (6-bit shift, RV64 long shifts)
	IMM_I,           // bits 31-20  (signed I-type 12-bit)
	IMM_S,           // bits 31-25 || 11-7  (S-type scatter)
	IMM_B,           // B-type scatter: imm[12] @31, [10:5] @30-25, [4:1] @11-8, [11] @7
	IMM_U,           // bits 31-12  (U-type 20-bit upper)
	IMM_J,           // J-type scatter: imm[20] @31, [10:1] @30-21, [11] @20, [19:12] @19-12
	OFFSET_BASE_I,   // memory: rs1 @bits 19-15 + IMM_I disp (loads, JALR, FLW, FLD)
	OFFSET_BASE_S,   // memory: rs1 @bits 19-15 + IMM_S disp (stores, FSW, FSD)
	OFFSET_BASE_A,   // memory: rs1 @bits 19-15 only (atomics; disp must be 0)
	CSR_FIELD,       // bits 31-20  (12-bit CSR address)
	ZIMM_FIELD,      // bits 19-15  (zero-extended 5-bit imm; replaces rs1 in CSRRxI)
	FENCE_PRED,      // bits 27-24
	FENCE_SUCC,      // bits 23-20
	ROUND_FIELD,     // bits 14-12  (funct3 doubles as rm)
	AQRL,            // bits 26-25  (atomic acquire/release)
	// ---- C extension (compressed; bits fit in low 16 of the word) ----
	C_RD_RS1,        // bits 11-7  (CR/CI shared rd/rs1 slot)
	C_RS2,           // bits  6-2  (CR rs2)
	C_RD_PRIMED,     // bits  4-2  (CIW/CL/CB rd' encoded as x8+field)
	C_RS1_PRIMED,    // bits  9-7  (CL/CS/CA/CB rs1' encoded as x8+field)
	C_RS2_PRIMED,    // bits  4-2  (CS/CA rs2' encoded as x8+field)
	C_RD_RS1_PRIMED, // bits  9-7  (CA rd'/rs1' encoded as x8+field)
	C_IMM_CI_S,      // bits 12 || 6-2  (signed 6-bit CI imm)
	C_IMM_CI_U,      // bits 12 || 6-2  (unsigned 6-bit CI imm; SLLI shamt)
	C_IMM_CIW,       // bits 12-5  (C.ADDI4SPN: scrambled to imm[9:2])
	C_IMM_LUI,       // bits 12 || 6-2 (C.LUI: imm[17] || imm[16:12])
	C_IMM_ADDI16SP,  // bits 12,4,3,5,2,6  -> imm[9,4,6,8:7,5]
	C_IMM_CSS_W,     // bits 12-7  -> imm[5:2,7:6] (C.SWSP scaled by 4)
	C_IMM_CSS_D,     // bits 12-7  -> imm[5:3,8:6] (C.SDSP scaled by 8)
	C_IMM_CL_W,      // bits 12-10 || 6-5 -> imm[5:3,2,6] (C.LW/C.SW scaled by 4)
	C_IMM_CL_D,      // bits 12-10 || 6-5 -> imm[5:3,7:6] (C.LD/C.SD scaled by 8)
	C_BRANCH9,       // C.BEQZ/BNEZ: scatter to bits 12 || 10:9,2,7:6,5:4 || 11
	C_BRANCH12,      // C.J/C.JAL: scatter to bits 12 || 8 || 10:9 || 6 || 7 || 2 || 11 || 5:3 -> imm[11,4,9:8,10,6,7,3:1,5]
	C_OFFSET_BASE_W, // memory: rs1' at 9-7 + scaled-by-4 imm at 12-10 || 6-5
	C_OFFSET_BASE_D, // memory: rs1' at 9-7 + scaled-by-8 imm at 12-10 || 6-5
	C_SP_OFFSET_W,   // SP-relative: rd at 11-7 + scaled-by-4 imm at 12 || 6:4 || 3:2 -> imm[5,4:2,7:6]
	C_SP_OFFSET_D,   // SP-relative: rd at 11-7 + scaled-by-8 imm at 12 || 6:5 || 4:2 -> imm[5,4:3,8:6]
}
     

    Where the operand's bits land in the 32-bit instruction word.

    Operand_Kind ¶
    Source

    Operand_Kind :: enum u8 {
	NONE, 
	REGISTER,  // mostly used for `A` in `ROL A` (implicit; rarely needed)
	IMMEDIATE, 
	MEMORY, 
	RELATIVE,  // PC-relative target (label or raw byte offset)
}

    Operand_Type ¶
    Source

    Operand_Type :: enum u8 {
	NONE, 
	GPR, 
	FPR, 
	IMM12,       // signed 12-bit I-type immediate (ADDI/LOADS/JALR/...)
	IMM12U,      // unsigned 12-bit (CSR address; some pseudo-uses)
	IMM5,        // 5-bit shift amount (RV32 shifts; SLLIW/SRLIW/SRAIW)
	IMM6,        // 6-bit shift amount (RV64 SLLI/SRLI/SRAI)
	IMM20,       // 20-bit U-type immediate (LUI, AUIPC)
	REL13,       // 13-bit branch target (label or signed byte offset)
	REL21,       // 21-bit jump target (label or signed byte offset)
	MEM,         // base + signed 12-bit displacement
	CSR,         // 12-bit CSR address
	FENCE_FLAGS, // 4-bit pred or succ mask (for FENCE)
	ROUND_MODE,  // 3-bit FP rounding mode
	ZIMM5,       // 5-bit zero-extended immediate (CSRRWI/SI/CI)
	// ---- C extension (compressed) ----
	GPR_C,       // "primed" 3-bit register (x8..x15 only)
	GPR_SP,      // hardwired SP (x2) for C.ADDI16SP / C.LWSP / C.SWSP
	GPR_NONZERO, // GPR with hw != 0 (C.ADDI/C.LI/C.MV/etc. forbid x0)
	FPR_C,       // primed FP register (f8..f15 only)
	IMM_C6S,     // CI-form signed 6-bit (C.ADDI/C.LI)
	IMM_C6U,     // CI-form unsigned 6-bit (C.SLLI/SRLI/SRAI shamt)
	IMM_C8U,     // CIW-form 8-bit unsigned scaled (C.ADDI4SPN)
	IMM_C10S,    // C.ADDI16SP 10-bit signed scaled by 16
	IMM_C18S,    // C.LUI 18-bit signed scaled by 4096
	REL9,        // 9-bit signed PC-rel branch (C.BEQZ/BNEZ)
	REL12,       // 12-bit signed PC-rel jump (C.J/C.JAL)
	MEM_C_W,     // memory for C.LW/C.SW (rs1' + scaled imm by 4)
	MEM_C_D,     // memory for C.LD/C.SD (rs1' + scaled imm by 8)
	MEM_C_SP_W,  // SP-relative for C.LWSP/C.SWSP (scaled by 4)
	MEM_C_SP_D,  // SP-relative for C.LDSP/C.SDSP (scaled by 8)
}
     

    What the user passes in.

    Print_Options :: rexcode_isa.Print_Options
    Related Procedures With Parameters
    Related Constants
    Print_Result :: rexcode_isa.Print_Result

    Register ¶
    Source

    Register :: distinct u16
    Related Procedures With Parameters
    Related Procedures With Returns
    Related Constants

    Relocation ¶
    Source

    Relocation :: struct #packed {
	offset:   u32,
	label_id: u32,
	addend:   i32,
	type:     Relocation_Type,
	size:     u8,
	inst_idx: u16,
}

    Relocation_Type ¶
    Source

    Relocation_Type :: enum u8 {
	NONE         = 0, 
	// PC-relative branches and jumps
	BRANCH,           // 13-bit signed PC-rel, B-type scatter (BEQ/BNE/...)
	JAL,              // 21-bit signed PC-rel, J-type scatter (JAL)
	// PC-relative paired (AUIPC + ADDI/load/store)
	PCREL_HI20,       // upper 20 bits of (sym - pc), U-type
	PCREL_LO12_I,     // lower 12 bits, I-type form
	PCREL_LO12_S,     // lower 12 bits, S-type form
	// Absolute paired (LUI + ADDI/load/store)
	HI20,             // upper 20 of absolute, U-type
	LO12_I,           // lower 12, I-type
	LO12_S,           // lower 12, S-type
	// Helpful aggregate forms (the assembler can expand)
	CALL,             // AUIPC + JALR pair to call a far symbol
	// ---- C extension PC-relative ----
	C_BRANCH,         // 9-bit signed PC-rel for C.BEQZ / C.BNEZ
	C_JUMP,           // 12-bit signed PC-rel for C.J / C.JAL
}

    Token ¶
    Source

    Token :: rexcode_isa.Token

    Token_Kind ¶
    Source

    Token_Kind :: rexcode_isa.Token_Kind

    XLEN ¶
    Source

    XLEN :: enum u8 {
	RV32, 
	RV64, 
}
    Related Procedures With Parameters

    Constants

    A0 ¶
    Source

    A0 :: Register(REG_GPR | 10)

    A1 ¶
    Source

    A1 :: Register(REG_GPR | 11)

    A2 ¶
    Source

    A2 :: Register(REG_GPR | 12)

    A3 ¶
    Source

    A3 :: Register(REG_GPR | 13)

    A4 ¶
    Source

    A4 :: Register(REG_GPR | 14)

    A5 ¶
    Source

    A5 :: Register(REG_GPR | 15)

    A6 ¶
    Source

    A6 :: Register(REG_GPR | 16)

    A7 ¶
    Source

    A7 :: Register(REG_GPR | 17)

    DEFAULT_PRINT_OPTIONS ¶
    Source

    DEFAULT_PRINT_OPTIONS: rexcode_isa.Print_Options : isa.DEFAULT_PRINT_OPTIONS

    FA0 ¶
    Source

    FA0 :: Register(REG_FPR | 10)

    FA1 ¶
    Source

    FA1 :: Register(REG_FPR | 11)

    FA2 ¶
    Source

    FA2 :: Register(REG_FPR | 12)

    FA3 ¶
    Source

    FA3 :: Register(REG_FPR | 13)

    FA4 ¶
    Source

    FA4 :: Register(REG_FPR | 14)

    FA5 ¶
    Source

    FA5 :: Register(REG_FPR | 15)

    FA6 ¶
    Source

    FA6 :: Register(REG_FPR | 16)

    FA7 ¶
    Source

    FA7 :: Register(REG_FPR | 17)

    FP ¶
    Source

    FP :: GPR(8)
     

    S0 doubles as frame pointer in the ABI

    FS0 ¶
    Source

    FS0 :: Register(REG_FPR | 8)

    FS1 ¶
    Source

    FS1 :: Register(REG_FPR | 9)

    FS10 ¶
    Source

    FS10 :: Register(REG_FPR | 26)

    FS11 ¶
    Source

    FS11 :: Register(REG_FPR | 27)

    FS2 ¶
    Source

    FS2 :: Register(REG_FPR | 18)

    FS3 ¶
    Source

    FS3 :: Register(REG_FPR | 19)

    FS4 ¶
    Source

    FS4 :: Register(REG_FPR | 20)

    FS5 ¶
    Source

    FS5 :: Register(REG_FPR | 21)

    FS6 ¶
    Source

    FS6 :: Register(REG_FPR | 22)

    FS7 ¶
    Source

    FS7 :: Register(REG_FPR | 23)

    FS8 ¶
    Source

    FS8 :: Register(REG_FPR | 24)

    FS9 ¶
    Source

    FS9 :: Register(REG_FPR | 25)

    FT0 ¶
    Source

    FT0 :: Register(REG_FPR | 0)

    FT1 ¶
    Source

    FT1 :: Register(REG_FPR | 1)

    FT10 ¶
    Source

    FT10 :: Register(REG_FPR | 30)

    FT11 ¶
    Source

    FT11 :: Register(REG_FPR | 31)

    FT2 ¶
    Source

    FT2 :: Register(REG_FPR | 2)

    FT3 ¶
    Source

    FT3 :: Register(REG_FPR | 3)

    FT4 ¶
    Source

    FT4 :: Register(REG_FPR | 4)

    FT5 ¶
    Source

    FT5 :: Register(REG_FPR | 5)

    FT6 ¶
    Source

    FT6 :: Register(REG_FPR | 6)

    FT7 ¶
    Source

    FT7 :: Register(REG_FPR | 7)

    FT8 ¶
    Source

    FT8 :: Register(REG_FPR | 28)

    FT9 ¶
    Source

    FT9 :: Register(REG_FPR | 29)

    GP ¶
    Source

    GP :: Register(REG_GPR | 3)

    LABEL_UNDEFINED ¶
    Source

    LABEL_UNDEFINED: rexcode_isa.Label_Definition : isa.LABEL_UNDEFINED

    MASK_B ¶
    Source

    MASK_B: u32 : MASK_OPCODE | MASK_FUNCT3

    MASK_FUNCT3 ¶
    Source

    MASK_FUNCT3 :: u32(0x00007000)
     

    bits 14-12

    MASK_FUNCT7 ¶
    Source

    MASK_FUNCT7 :: u32(0xFE000000)
     

    bits 31-25

    MASK_I ¶
    Source

    MASK_I: u32 : MASK_OPCODE | MASK_FUNCT3

    MASK_IMM_I ¶
    Source

    MASK_IMM_I :: u32(0xFFF00000)
     

    bits 31-20

    MASK_I_SHIFT ¶
    Source

    MASK_I_SHIFT: u32 : MASK_OPCODE | MASK_FUNCT3 | (MASK_FUNCT7 &~ MASK_SHAMT6)
     

    ignore shamt

    MASK_J ¶
    Source

    MASK_J: u32 : MASK_OPCODE

    MASK_OPCODE ¶
    Source

    MASK_OPCODE :: u32(0x0000007F)
     

    Static field masks for handy reference in the table.

    MASK_R ¶
    Source

    MASK_R: u32 : MASK_OPCODE | MASK_FUNCT3 | MASK_FUNCT7
     

    Convenience composites

    MASK_RD ¶
    Source

    MASK_RD :: u32(0x00000F80)
     

    bits 11-7

    MASK_RS1 ¶
    Source

    MASK_RS1 :: u32(0x000F8000)
     

    bits 19-15

    MASK_RS2 ¶
    Source

    MASK_RS2 :: u32(0x01F00000)
     

    bits 24-20

    MASK_S ¶
    Source

    MASK_S: u32 : MASK_OPCODE | MASK_FUNCT3

    MASK_SHAMT5 ¶
    Source

    MASK_SHAMT5 :: u32(0x01F00000)
     

    bits 24-20

    MASK_SHAMT6 ¶
    Source

    MASK_SHAMT6 :: u32(0x03F00000)
     

    bits 25-20 (RV64)

    MASK_U ¶
    Source

    MASK_U: u32 : MASK_OPCODE

    MAX_INST_SIZE ¶
    Source

    MAX_INST_SIZE :: 4

    NONE ¶
    Source

    NONE :: Register(0xFFFF)

    RA ¶
    Source

    RA :: Register(REG_GPR | 1)

    REG_FPR ¶
    Source

    REG_FPR :: 0x0200
     

    f0..f31

    REG_GPR ¶
    Source

    REG_GPR :: 0x0100
     

    x0..x31

    REG_NONE ¶
    Source

    REG_NONE :: 0x0000

    S0 ¶
    Source

    S0 :: Register(REG_GPR | 8)

    S1 ¶
    Source

    S1 :: Register(REG_GPR | 9)

    S10 ¶
    Source

    S10 :: Register(REG_GPR | 26)

    S11 ¶
    Source

    S11 :: Register(REG_GPR | 27)

    S2 ¶
    Source

    S2 :: Register(REG_GPR | 18)

    S3 ¶
    Source

    S3 :: Register(REG_GPR | 19)

    S4 ¶
    Source

    S4 :: Register(REG_GPR | 20)

    S5 ¶
    Source

    S5 :: Register(REG_GPR | 21)

    S6 ¶
    Source

    S6 :: Register(REG_GPR | 22)

    S7 ¶
    Source

    S7 :: Register(REG_GPR | 23)

    S8 ¶
    Source

    S8 :: Register(REG_GPR | 24)

    S9 ¶
    Source

    S9 :: Register(REG_GPR | 25)

    SP ¶
    Source

    SP :: Register(REG_GPR | 2)

    T0 ¶
    Source

    T0 :: Register(REG_GPR | 5)

    T1 ¶
    Source

    T1 :: Register(REG_GPR | 6)

    T2 ¶
    Source

    T2 :: Register(REG_GPR | 7)

    T3 ¶
    Source

    T3 :: Register(REG_GPR | 28)

    T4 ¶
    Source

    T4 :: Register(REG_GPR | 29)

    T5 ¶
    Source

    T5 :: Register(REG_GPR | 30)

    T6 ¶
    Source

    T6 :: Register(REG_GPR | 31)

    TP ¶
    Source

    TP :: Register(REG_GPR | 4)

    ZERO ¶
    Source

    ZERO :: Register(REG_GPR | 0)

    Variables

    DECODE_ENTRIES ¶
    Source

    @(rodata)
DECODE_ENTRIES: []Decode_Entry = …

    DECODE_INDEX_OPCODE ¶
    Source

    @(rodata)
DECODE_INDEX_OPCODE: []Decode_Index = …

    DECODE_INDEX_OP_FP ¶
    Source

    @(rodata)
DECODE_INDEX_OP_FP: []Decode_Index = …

    DECODE_INDEX_RVC ¶
    Source

    @(rodata)
DECODE_INDEX_RVC: []Decode_Index = …

    ENCODE_FORMS ¶
    Source

    @(rodata)
ENCODE_FORMS: []Encoding = …

    ENCODE_RUNS ¶
    Source

    @(rodata)
ENCODE_RUNS: []Encode_Run = …

    Procedures

    aprint ¶
    Source

    aprint :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
	allocator := context.allocator, 
) -> string {…}

    aprintln ¶
    Source

    aprintln :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
	allocator := context.allocator, 
) -> string {…}

    bprint ¶
    Source

    bprint :: proc(
	buf:          []u8, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

    bprintln ¶
    Source

    bprintln :: proc(
	buf:          []u8, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

    decode ¶
    Source

    decode :: proc(
	data:         []u8, 
	relocs:       []Relocation, 
	instructions: ^[dynamic]Instruction, 
	inst_info:    ^[dynamic]Instruction_Info, 
	label_defs:   ^[dynamic]rexcode_isa.Label_Definition, 
	errors:       ^[dynamic]rexcode_isa.Error, 
	xlen:         XLEN = .RV64, 
) -> (byte_count: u32, ok: bool) {…}

    decode_estimate_instruction_count ¶
    Source

    decode_estimate_instruction_count :: proc "contextless" (data: []u8) -> int {…}
     

    Typical-case estimate of the instruction count for data.

    decode_max_instruction_count ¶
    Source

    decode_max_instruction_count :: proc "contextless" (data: []u8) -> int {…}
     

    Instruction-count ceiling for data (base is 4 bytes, compressed (C) 2; minimum 2).

    decode_reserve ¶
    Source

    decode_reserve :: proc(instructions: ^[dynamic]Instruction, inst_info: ^[dynamic]Instruction_Info, label_defs: ^[dynamic]rexcode_isa.Label_Definition, data: []u8, exact: bool = false) {…}
     

    Pre-size the caller's decode output arrays for data (reserves on top of any existing elements; nil to skip; exact=true for the ceiling, else the estimate).

    emit_add ¶
    Source

    emit_add :: emit_add_gpr_gpr_gpr

    emit_add_gpr_gpr_gpr ¶
    Source

    emit_add_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_addi ¶
    Source

    emit_addi_gpr_gpr_imm12 ¶
    Source

    emit_addi_gpr_gpr_imm12 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_addiw ¶
    Source

    emit_addiw :: emit_addiw_gpr_gpr_imm12

    emit_addiw_gpr_gpr_imm12 ¶
    Source

    emit_addiw_gpr_gpr_imm12 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_addw ¶
    Source

    emit_addw :: emit_addw_gpr_gpr_gpr

    emit_addw_gpr_gpr_gpr ¶
    Source

    emit_addw_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_amoadd_d ¶
    Source

    emit_amoadd_d :: emit_amoadd_d_gpr_gpr_mem

    emit_amoadd_d_gpr_gpr_mem ¶
    Source

    emit_amoadd_d_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amoadd_w ¶
    Source

    emit_amoadd_w :: emit_amoadd_w_gpr_gpr_mem

    emit_amoadd_w_gpr_gpr_mem ¶
    Source

    emit_amoadd_w_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amoand_d ¶
    Source

    emit_amoand_d :: emit_amoand_d_gpr_gpr_mem

    emit_amoand_d_gpr_gpr_mem ¶
    Source

    emit_amoand_d_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amoand_w ¶
    Source

    emit_amoand_w :: emit_amoand_w_gpr_gpr_mem

    emit_amoand_w_gpr_gpr_mem ¶
    Source

    emit_amoand_w_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amomax_d ¶
    Source

    emit_amomax_d :: emit_amomax_d_gpr_gpr_mem

    emit_amomax_d_gpr_gpr_mem ¶
    Source

    emit_amomax_d_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amomax_w ¶
    Source

    emit_amomax_w :: emit_amomax_w_gpr_gpr_mem

    emit_amomax_w_gpr_gpr_mem ¶
    Source

    emit_amomax_w_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amomaxu_d ¶
    Source

    emit_amomaxu_d :: emit_amomaxu_d_gpr_gpr_mem

    emit_amomaxu_d_gpr_gpr_mem ¶
    Source

    emit_amomaxu_d_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amomaxu_w ¶
    Source

    emit_amomaxu_w :: emit_amomaxu_w_gpr_gpr_mem

    emit_amomaxu_w_gpr_gpr_mem ¶
    Source

    emit_amomaxu_w_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amomin_d ¶
    Source

    emit_amomin_d :: emit_amomin_d_gpr_gpr_mem

    emit_amomin_d_gpr_gpr_mem ¶
    Source

    emit_amomin_d_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amomin_w ¶
    Source

    emit_amomin_w :: emit_amomin_w_gpr_gpr_mem

    emit_amomin_w_gpr_gpr_mem ¶
    Source

    emit_amomin_w_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amominu_d ¶
    Source

    emit_amominu_d :: emit_amominu_d_gpr_gpr_mem

    emit_amominu_d_gpr_gpr_mem ¶
    Source

    emit_amominu_d_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amominu_w ¶
    Source

    emit_amominu_w :: emit_amominu_w_gpr_gpr_mem

    emit_amominu_w_gpr_gpr_mem ¶
    Source

    emit_amominu_w_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amoor_d ¶
    Source

    emit_amoor_d :: emit_amoor_d_gpr_gpr_mem

    emit_amoor_d_gpr_gpr_mem ¶
    Source

    emit_amoor_d_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amoor_w ¶
    Source

    emit_amoor_w :: emit_amoor_w_gpr_gpr_mem

    emit_amoor_w_gpr_gpr_mem ¶
    Source

    emit_amoor_w_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amoswap_d ¶
    Source

    emit_amoswap_d :: emit_amoswap_d_gpr_gpr_mem

    emit_amoswap_d_gpr_gpr_mem ¶
    Source

    emit_amoswap_d_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amoswap_w ¶
    Source

    emit_amoswap_w :: emit_amoswap_w_gpr_gpr_mem

    emit_amoswap_w_gpr_gpr_mem ¶
    Source

    emit_amoswap_w_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amoxor_d ¶
    Source

    emit_amoxor_d :: emit_amoxor_d_gpr_gpr_mem

    emit_amoxor_d_gpr_gpr_mem ¶
    Source

    emit_amoxor_d_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_amoxor_w ¶
    Source

    emit_amoxor_w :: emit_amoxor_w_gpr_gpr_mem

    emit_amoxor_w_gpr_gpr_mem ¶
    Source

    emit_amoxor_w_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_and ¶
    Source

    emit_and :: emit_and_gpr_gpr_gpr

    emit_and_gpr_gpr_gpr ¶
    Source

    emit_and_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_andi ¶
    Source

    emit_andi_gpr_gpr_imm12 ¶
    Source

    emit_andi_gpr_gpr_imm12 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_auipc ¶
    Source

    emit_auipc :: emit_auipc_gpr_imm20

    emit_auipc_gpr_imm20 ¶
    Source

    emit_auipc_gpr_imm20 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64) {…}

    emit_beq ¶
    Source

    emit_beq_gpr_gpr_label ¶
    Source

    emit_beq_gpr_gpr_label :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, label: u32) {…}

    emit_bge ¶
    Source

    emit_bge_gpr_gpr_label ¶
    Source

    emit_bge_gpr_gpr_label :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, label: u32) {…}

    emit_bgeu ¶
    Source

    emit_bgeu_gpr_gpr_label ¶
    Source

    emit_bgeu_gpr_gpr_label :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, label: u32) {…}

    emit_blt ¶
    Source

    emit_blt_gpr_gpr_label ¶
    Source

    emit_blt_gpr_gpr_label :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, label: u32) {…}

    emit_bltu ¶
    Source

    emit_bltu_gpr_gpr_label ¶
    Source

    emit_bltu_gpr_gpr_label :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, label: u32) {…}

    emit_bne ¶
    Source

    emit_bne_gpr_gpr_label ¶
    Source

    emit_bne_gpr_gpr_label :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, label: u32) {…}

    emit_c_add ¶
    Source

    emit_c_add :: emit_c_add_gpr_gpr

    emit_c_add_gpr_gpr ¶
    Source

    emit_c_add_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR) {…}

    emit_c_addi ¶
    Source

    emit_c_addi :: emit_c_addi_gpr_imm6s

    emit_c_addi16sp ¶
    Source

    emit_c_addi16sp :: emit_c_addi16sp_gpr_imm10s

    emit_c_addi16sp_gpr_imm10s ¶
    Source

    emit_c_addi16sp_gpr_imm10s :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64) {…}

    emit_c_addi4spn ¶
    Source

    emit_c_addi4spn :: emit_c_addi4spn_gpr_gpr_imm8u

    emit_c_addi4spn_gpr_gpr_imm8u ¶
    Source

    emit_c_addi4spn_gpr_gpr_imm8u :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_c_addi_gpr_imm6s ¶
    Source

    emit_c_addi_gpr_imm6s :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64) {…}

    emit_c_addiw ¶
    Source

    emit_c_addiw :: emit_c_addiw_gpr_imm6s

    emit_c_addiw_gpr_imm6s ¶
    Source

    emit_c_addiw_gpr_imm6s :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64) {…}

    emit_c_addw ¶
    Source

    emit_c_addw :: emit_c_addw_gpr_gpr

    emit_c_addw_gpr_gpr ¶
    Source

    emit_c_addw_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR) {…}

    emit_c_and ¶
    Source

    emit_c_and :: emit_c_and_gpr_gpr

    emit_c_and_gpr_gpr ¶
    Source

    emit_c_and_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR) {…}

    emit_c_andi ¶
    Source

    emit_c_andi :: emit_c_andi_gpr_imm6s

    emit_c_andi_gpr_imm6s ¶
    Source

    emit_c_andi_gpr_imm6s :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64) {…}

    emit_c_beqz ¶
    Source

    emit_c_beqz :: emit_c_beqz_gpr_label

    emit_c_beqz_gpr_label ¶
    Source

    emit_c_beqz_gpr_label :: proc(instructions: ^[dynamic]Instruction, rd: GPR, label: u32) {…}

    emit_c_bnez ¶
    Source

    emit_c_bnez :: emit_c_bnez_gpr_label

    emit_c_bnez_gpr_label ¶
    Source

    emit_c_bnez_gpr_label :: proc(instructions: ^[dynamic]Instruction, rd: GPR, label: u32) {…}

    emit_c_ebreak ¶
    Source

    emit_c_ebreak :: emit_c_ebreak_none

    emit_c_ebreak_none ¶
    Source

    emit_c_ebreak_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_c_fld ¶
    Source

    emit_c_fld :: emit_c_fld_fpr_mem

    emit_c_fld_fpr_mem ¶
    Source

    emit_c_fld_fpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: FPR, mem: Memory) {…}

    emit_c_fldsp ¶
    Source

    emit_c_fldsp :: emit_c_fldsp_fpr_mem

    emit_c_fldsp_fpr_mem ¶
    Source

    emit_c_fldsp_fpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: FPR, mem: Memory) {…}

    emit_c_fsd ¶
    Source

    emit_c_fsd :: emit_c_fsd_fpr_mem

    emit_c_fsd_fpr_mem ¶
    Source

    emit_c_fsd_fpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: FPR, mem: Memory) {…}

    emit_c_fsdsp ¶
    Source

    emit_c_fsdsp :: emit_c_fsdsp_fpr_mem

    emit_c_fsdsp_fpr_mem ¶
    Source

    emit_c_fsdsp_fpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: FPR, mem: Memory) {…}

    emit_c_j ¶
    Source

    emit_c_j :: emit_c_j_label

    emit_c_j_label ¶
    Source

    emit_c_j_label :: proc(instructions: ^[dynamic]Instruction, label: u32) {…}

    emit_c_jal ¶
    Source

    emit_c_jal :: emit_c_jal_label

    emit_c_jal_label ¶
    Source

    emit_c_jal_label :: proc(instructions: ^[dynamic]Instruction, label: u32) {…}

    emit_c_jalr ¶
    Source

    emit_c_jalr :: emit_c_jalr_gpr

    emit_c_jalr_gpr ¶
    Source

    emit_c_jalr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR) {…}

    emit_c_jr ¶
    Source

    emit_c_jr :: emit_c_jr_gpr

    emit_c_jr_gpr ¶
    Source

    emit_c_jr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR) {…}

    emit_c_ld ¶
    Source

    emit_c_ld :: emit_c_ld_gpr_mem

    emit_c_ld_gpr_mem ¶
    Source

    emit_c_ld_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_c_ldsp ¶
    Source

    emit_c_ldsp :: emit_c_ldsp_gpr_mem

    emit_c_ldsp_gpr_mem ¶
    Source

    emit_c_ldsp_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_c_li ¶
    Source

    emit_c_li :: emit_c_li_gpr_imm6s

    emit_c_li_gpr_imm6s ¶
    Source

    emit_c_li_gpr_imm6s :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64) {…}

    emit_c_lui ¶
    Source

    emit_c_lui :: emit_c_lui_gpr_imm18s

    emit_c_lui_gpr_imm18s ¶
    Source

    emit_c_lui_gpr_imm18s :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64) {…}

    emit_c_lw ¶
    Source

    emit_c_lw :: emit_c_lw_gpr_mem

    emit_c_lw_gpr_mem ¶
    Source

    emit_c_lw_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_c_lwsp ¶
    Source

    emit_c_lwsp :: emit_c_lwsp_gpr_mem

    emit_c_lwsp_gpr_mem ¶
    Source

    emit_c_lwsp_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_c_mv ¶
    Source

    emit_c_mv :: emit_c_mv_gpr_gpr

    emit_c_mv_gpr_gpr ¶
    Source

    emit_c_mv_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR) {…}

    emit_c_nop ¶
    Source

    emit_c_nop :: emit_c_nop_none

    emit_c_nop_none ¶
    Source

    emit_c_nop_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_c_or ¶
    Source

    emit_c_or :: emit_c_or_gpr_gpr

    emit_c_or_gpr_gpr ¶
    Source

    emit_c_or_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR) {…}

    emit_c_sd ¶
    Source

    emit_c_sd :: emit_c_sd_gpr_mem

    emit_c_sd_gpr_mem ¶
    Source

    emit_c_sd_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_c_sdsp ¶
    Source

    emit_c_sdsp :: emit_c_sdsp_gpr_mem

    emit_c_sdsp_gpr_mem ¶
    Source

    emit_c_sdsp_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_c_slli ¶
    Source

    emit_c_slli :: emit_c_slli_gpr_imm6u

    emit_c_slli_gpr_imm6u ¶
    Source

    emit_c_slli_gpr_imm6u :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64) {…}

    emit_c_srai ¶
    Source

    emit_c_srai :: emit_c_srai_gpr_imm6u

    emit_c_srai_gpr_imm6u ¶
    Source

    emit_c_srai_gpr_imm6u :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64) {…}

    emit_c_srli ¶
    Source

    emit_c_srli :: emit_c_srli_gpr_imm6u

    emit_c_srli_gpr_imm6u ¶
    Source

    emit_c_srli_gpr_imm6u :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64) {…}

    emit_c_sub ¶
    Source

    emit_c_sub :: emit_c_sub_gpr_gpr

    emit_c_sub_gpr_gpr ¶
    Source

    emit_c_sub_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR) {…}

    emit_c_subw ¶
    Source

    emit_c_subw :: emit_c_subw_gpr_gpr

    emit_c_subw_gpr_gpr ¶
    Source

    emit_c_subw_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR) {…}

    emit_c_sw ¶
    Source

    emit_c_sw :: emit_c_sw_gpr_mem

    emit_c_sw_gpr_mem ¶
    Source

    emit_c_sw_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_c_swsp ¶
    Source

    emit_c_swsp :: emit_c_swsp_gpr_mem

    emit_c_swsp_gpr_mem ¶
    Source

    emit_c_swsp_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_c_xor ¶
    Source

    emit_c_xor :: emit_c_xor_gpr_gpr

    emit_c_xor_gpr_gpr ¶
    Source

    emit_c_xor_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR) {…}

    emit_csrrc ¶
    Source

    emit_csrrc :: emit_csrrc_gpr_csr_gpr

    emit_csrrc_gpr_csr_gpr ¶
    Source

    emit_csrrc_gpr_csr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64, rs1: GPR) {…}

    emit_csrrci ¶
    Source

    emit_csrrci :: emit_csrrci_gpr_csr_zimm5

    emit_csrrci_gpr_csr_zimm5 ¶
    Source

    emit_csrrci_gpr_csr_zimm5 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64, imm2: i64) {…}

    emit_csrrs ¶
    Source

    emit_csrrs :: emit_csrrs_gpr_csr_gpr

    emit_csrrs_gpr_csr_gpr ¶
    Source

    emit_csrrs_gpr_csr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64, rs1: GPR) {…}

    emit_csrrsi ¶
    Source

    emit_csrrsi :: emit_csrrsi_gpr_csr_zimm5

    emit_csrrsi_gpr_csr_zimm5 ¶
    Source

    emit_csrrsi_gpr_csr_zimm5 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64, imm2: i64) {…}

    emit_csrrw ¶
    Source

    emit_csrrw :: emit_csrrw_gpr_csr_gpr

    emit_csrrw_gpr_csr_gpr ¶
    Source

    emit_csrrw_gpr_csr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64, rs1: GPR) {…}

    emit_csrrwi ¶
    Source

    emit_csrrwi :: emit_csrrwi_gpr_csr_zimm5

    emit_csrrwi_gpr_csr_zimm5 ¶
    Source

    emit_csrrwi_gpr_csr_zimm5 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64, imm2: i64) {…}

    emit_div ¶
    Source

    emit_div :: emit_div_gpr_gpr_gpr

    emit_div_gpr_gpr_gpr ¶
    Source

    emit_div_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_divu ¶
    Source

    emit_divu :: emit_divu_gpr_gpr_gpr

    emit_divu_gpr_gpr_gpr ¶
    Source

    emit_divu_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_divuw ¶
    Source

    emit_divuw :: emit_divuw_gpr_gpr_gpr

    emit_divuw_gpr_gpr_gpr ¶
    Source

    emit_divuw_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_divw ¶
    Source

    emit_divw :: emit_divw_gpr_gpr_gpr

    emit_divw_gpr_gpr_gpr ¶
    Source

    emit_divw_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_ebreak ¶
    Source

    emit_ebreak :: emit_ebreak_none

    emit_ebreak_none ¶
    Source

    emit_ebreak_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_ecall ¶
    Source

    emit_ecall :: emit_ecall_none

    emit_ecall_none ¶
    Source

    emit_ecall_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_fadd_d ¶
    Source

    emit_fadd_d :: emit_fadd_d_fpr_fpr_fpr

    emit_fadd_d_fpr_fpr_fpr ¶
    Source

    emit_fadd_d_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fadd_s ¶
    Source

    emit_fadd_s :: emit_fadd_s_fpr_fpr_fpr

    emit_fadd_s_fpr_fpr_fpr ¶
    Source

    emit_fadd_s_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fclass_d ¶
    Source

    emit_fclass_d :: emit_fclass_d_gpr_fpr

    emit_fclass_d_gpr_fpr ¶
    Source

    emit_fclass_d_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fclass_s ¶
    Source

    emit_fclass_s :: emit_fclass_s_gpr_fpr

    emit_fclass_s_gpr_fpr ¶
    Source

    emit_fclass_s_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fcvt_d_l ¶
    Source

    emit_fcvt_d_l :: emit_fcvt_d_l_fpr_gpr

    emit_fcvt_d_l_fpr_gpr ¶
    Source

    emit_fcvt_d_l_fpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: GPR) {…}

    emit_fcvt_d_lu ¶
    Source

    emit_fcvt_d_lu :: emit_fcvt_d_lu_fpr_gpr

    emit_fcvt_d_lu_fpr_gpr ¶
    Source

    emit_fcvt_d_lu_fpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: GPR) {…}

    emit_fcvt_d_s ¶
    Source

    emit_fcvt_d_s :: emit_fcvt_d_s_fpr_fpr

    emit_fcvt_d_s_fpr_fpr ¶
    Source

    emit_fcvt_d_s_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR) {…}

    emit_fcvt_d_w ¶
    Source

    emit_fcvt_d_w :: emit_fcvt_d_w_fpr_gpr

    emit_fcvt_d_w_fpr_gpr ¶
    Source

    emit_fcvt_d_w_fpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: GPR) {…}

    emit_fcvt_d_wu ¶
    Source

    emit_fcvt_d_wu :: emit_fcvt_d_wu_fpr_gpr

    emit_fcvt_d_wu_fpr_gpr ¶
    Source

    emit_fcvt_d_wu_fpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: GPR) {…}

    emit_fcvt_l_d ¶
    Source

    emit_fcvt_l_d :: emit_fcvt_l_d_gpr_fpr

    emit_fcvt_l_d_gpr_fpr ¶
    Source

    emit_fcvt_l_d_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fcvt_l_s ¶
    Source

    emit_fcvt_l_s :: emit_fcvt_l_s_gpr_fpr

    emit_fcvt_l_s_gpr_fpr ¶
    Source

    emit_fcvt_l_s_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fcvt_lu_d ¶
    Source

    emit_fcvt_lu_d :: emit_fcvt_lu_d_gpr_fpr

    emit_fcvt_lu_d_gpr_fpr ¶
    Source

    emit_fcvt_lu_d_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fcvt_lu_s ¶
    Source

    emit_fcvt_lu_s :: emit_fcvt_lu_s_gpr_fpr

    emit_fcvt_lu_s_gpr_fpr ¶
    Source

    emit_fcvt_lu_s_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fcvt_s_d ¶
    Source

    emit_fcvt_s_d :: emit_fcvt_s_d_fpr_fpr

    emit_fcvt_s_d_fpr_fpr ¶
    Source

    emit_fcvt_s_d_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR) {…}

    emit_fcvt_s_l ¶
    Source

    emit_fcvt_s_l :: emit_fcvt_s_l_fpr_gpr

    emit_fcvt_s_l_fpr_gpr ¶
    Source

    emit_fcvt_s_l_fpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: GPR) {…}

    emit_fcvt_s_lu ¶
    Source

    emit_fcvt_s_lu :: emit_fcvt_s_lu_fpr_gpr

    emit_fcvt_s_lu_fpr_gpr ¶
    Source

    emit_fcvt_s_lu_fpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: GPR) {…}

    emit_fcvt_s_w ¶
    Source

    emit_fcvt_s_w :: emit_fcvt_s_w_fpr_gpr

    emit_fcvt_s_w_fpr_gpr ¶
    Source

    emit_fcvt_s_w_fpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: GPR) {…}

    emit_fcvt_s_wu ¶
    Source

    emit_fcvt_s_wu :: emit_fcvt_s_wu_fpr_gpr

    emit_fcvt_s_wu_fpr_gpr ¶
    Source

    emit_fcvt_s_wu_fpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: GPR) {…}

    emit_fcvt_w_d ¶
    Source

    emit_fcvt_w_d :: emit_fcvt_w_d_gpr_fpr

    emit_fcvt_w_d_gpr_fpr ¶
    Source

    emit_fcvt_w_d_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fcvt_w_s ¶
    Source

    emit_fcvt_w_s :: emit_fcvt_w_s_gpr_fpr

    emit_fcvt_w_s_gpr_fpr ¶
    Source

    emit_fcvt_w_s_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fcvt_wu_d ¶
    Source

    emit_fcvt_wu_d :: emit_fcvt_wu_d_gpr_fpr

    emit_fcvt_wu_d_gpr_fpr ¶
    Source

    emit_fcvt_wu_d_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fcvt_wu_s ¶
    Source

    emit_fcvt_wu_s :: emit_fcvt_wu_s_gpr_fpr

    emit_fcvt_wu_s_gpr_fpr ¶
    Source

    emit_fcvt_wu_s_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fdiv_d ¶
    Source

    emit_fdiv_d :: emit_fdiv_d_fpr_fpr_fpr

    emit_fdiv_d_fpr_fpr_fpr ¶
    Source

    emit_fdiv_d_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fdiv_s ¶
    Source

    emit_fdiv_s :: emit_fdiv_s_fpr_fpr_fpr

    emit_fdiv_s_fpr_fpr_fpr ¶
    Source

    emit_fdiv_s_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fence ¶
    Source

    emit_fence :: emit_fence_fence_fence

    emit_fence_fence_fence ¶
    Source

    emit_fence_fence_fence :: proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) {…}

    emit_fence_i ¶
    Source

    emit_fence_i :: emit_fence_i_none

    emit_fence_i_none ¶
    Source

    emit_fence_i_none :: proc(instructions: ^[dynamic]Instruction) {…}

    emit_feq_d ¶
    Source

    emit_feq_d :: emit_feq_d_gpr_fpr_fpr

    emit_feq_d_gpr_fpr_fpr ¶
    Source

    emit_feq_d_gpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR, rs2: FPR) {…}

    emit_feq_s ¶
    Source

    emit_feq_s :: emit_feq_s_gpr_fpr_fpr

    emit_feq_s_gpr_fpr_fpr ¶
    Source

    emit_feq_s_gpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR, rs2: FPR) {…}

    emit_fld ¶
    Source

    emit_fld :: emit_fld_fpr_mem

    emit_fld_fpr_mem ¶
    Source

    emit_fld_fpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: FPR, mem: Memory) {…}

    emit_fle_d ¶
    Source

    emit_fle_d :: emit_fle_d_gpr_fpr_fpr

    emit_fle_d_gpr_fpr_fpr ¶
    Source

    emit_fle_d_gpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR, rs2: FPR) {…}

    emit_fle_s ¶
    Source

    emit_fle_s :: emit_fle_s_gpr_fpr_fpr

    emit_fle_s_gpr_fpr_fpr ¶
    Source

    emit_fle_s_gpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR, rs2: FPR) {…}

    emit_flt_d ¶
    Source

    emit_flt_d :: emit_flt_d_gpr_fpr_fpr

    emit_flt_d_gpr_fpr_fpr ¶
    Source

    emit_flt_d_gpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR, rs2: FPR) {…}

    emit_flt_s ¶
    Source

    emit_flt_s :: emit_flt_s_gpr_fpr_fpr

    emit_flt_s_gpr_fpr_fpr ¶
    Source

    emit_flt_s_gpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR, rs2: FPR) {…}

    emit_flw ¶
    Source

    emit_flw :: emit_flw_fpr_mem

    emit_flw_fpr_mem ¶
    Source

    emit_flw_fpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: FPR, mem: Memory) {…}

    emit_fmadd_d ¶
    Source

    emit_fmadd_d_fpr_fpr_fpr_fpr ¶
    Source

    emit_fmadd_d_fpr_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) {…}

    emit_fmadd_s ¶
    Source

    emit_fmadd_s_fpr_fpr_fpr_fpr ¶
    Source

    emit_fmadd_s_fpr_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) {…}

    emit_fmax_d ¶
    Source

    emit_fmax_d :: emit_fmax_d_fpr_fpr_fpr

    emit_fmax_d_fpr_fpr_fpr ¶
    Source

    emit_fmax_d_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fmax_s ¶
    Source

    emit_fmax_s :: emit_fmax_s_fpr_fpr_fpr

    emit_fmax_s_fpr_fpr_fpr ¶
    Source

    emit_fmax_s_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fmin_d ¶
    Source

    emit_fmin_d :: emit_fmin_d_fpr_fpr_fpr

    emit_fmin_d_fpr_fpr_fpr ¶
    Source

    emit_fmin_d_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fmin_s ¶
    Source

    emit_fmin_s :: emit_fmin_s_fpr_fpr_fpr

    emit_fmin_s_fpr_fpr_fpr ¶
    Source

    emit_fmin_s_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fmsub_d ¶
    Source

    emit_fmsub_d_fpr_fpr_fpr_fpr ¶
    Source

    emit_fmsub_d_fpr_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) {…}

    emit_fmsub_s ¶
    Source

    emit_fmsub_s_fpr_fpr_fpr_fpr ¶
    Source

    emit_fmsub_s_fpr_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) {…}

    emit_fmul_d ¶
    Source

    emit_fmul_d :: emit_fmul_d_fpr_fpr_fpr

    emit_fmul_d_fpr_fpr_fpr ¶
    Source

    emit_fmul_d_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fmul_s ¶
    Source

    emit_fmul_s :: emit_fmul_s_fpr_fpr_fpr

    emit_fmul_s_fpr_fpr_fpr ¶
    Source

    emit_fmul_s_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fmv_d_x ¶
    Source

    emit_fmv_d_x :: emit_fmv_d_x_fpr_gpr

    emit_fmv_d_x_fpr_gpr ¶
    Source

    emit_fmv_d_x_fpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: GPR) {…}

    emit_fmv_w_x ¶
    Source

    emit_fmv_w_x :: emit_fmv_w_x_fpr_gpr

    emit_fmv_w_x_fpr_gpr ¶
    Source

    emit_fmv_w_x_fpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: GPR) {…}

    emit_fmv_x_d ¶
    Source

    emit_fmv_x_d :: emit_fmv_x_d_gpr_fpr

    emit_fmv_x_d_gpr_fpr ¶
    Source

    emit_fmv_x_d_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fmv_x_w ¶
    Source

    emit_fmv_x_w :: emit_fmv_x_w_gpr_fpr

    emit_fmv_x_w_gpr_fpr ¶
    Source

    emit_fmv_x_w_gpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: FPR) {…}

    emit_fnmadd_d ¶
    Source

    emit_fnmadd_d_fpr_fpr_fpr_fpr ¶
    Source

    emit_fnmadd_d_fpr_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) {…}

    emit_fnmadd_s ¶
    Source

    emit_fnmadd_s_fpr_fpr_fpr_fpr ¶
    Source

    emit_fnmadd_s_fpr_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) {…}

    emit_fnmsub_d ¶
    Source

    emit_fnmsub_d_fpr_fpr_fpr_fpr ¶
    Source

    emit_fnmsub_d_fpr_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) {…}

    emit_fnmsub_s ¶
    Source

    emit_fnmsub_s_fpr_fpr_fpr_fpr ¶
    Source

    emit_fnmsub_s_fpr_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) {…}

    emit_fsd ¶
    Source

    emit_fsd :: emit_fsd_fpr_mem

    emit_fsd_fpr_mem ¶
    Source

    emit_fsd_fpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: FPR, mem: Memory) {…}

    emit_fsgnj_d ¶
    Source

    emit_fsgnj_d :: emit_fsgnj_d_fpr_fpr_fpr

    emit_fsgnj_d_fpr_fpr_fpr ¶
    Source

    emit_fsgnj_d_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fsgnj_s ¶
    Source

    emit_fsgnj_s :: emit_fsgnj_s_fpr_fpr_fpr

    emit_fsgnj_s_fpr_fpr_fpr ¶
    Source

    emit_fsgnj_s_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fsgnjn_d ¶
    Source

    emit_fsgnjn_d :: emit_fsgnjn_d_fpr_fpr_fpr

    emit_fsgnjn_d_fpr_fpr_fpr ¶
    Source

    emit_fsgnjn_d_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fsgnjn_s ¶
    Source

    emit_fsgnjn_s :: emit_fsgnjn_s_fpr_fpr_fpr

    emit_fsgnjn_s_fpr_fpr_fpr ¶
    Source

    emit_fsgnjn_s_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fsgnjx_d ¶
    Source

    emit_fsgnjx_d :: emit_fsgnjx_d_fpr_fpr_fpr

    emit_fsgnjx_d_fpr_fpr_fpr ¶
    Source

    emit_fsgnjx_d_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fsgnjx_s ¶
    Source

    emit_fsgnjx_s :: emit_fsgnjx_s_fpr_fpr_fpr

    emit_fsgnjx_s_fpr_fpr_fpr ¶
    Source

    emit_fsgnjx_s_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fsqrt_d ¶
    Source

    emit_fsqrt_d :: emit_fsqrt_d_fpr_fpr

    emit_fsqrt_d_fpr_fpr ¶
    Source

    emit_fsqrt_d_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR) {…}

    emit_fsqrt_s ¶
    Source

    emit_fsqrt_s :: emit_fsqrt_s_fpr_fpr

    emit_fsqrt_s_fpr_fpr ¶
    Source

    emit_fsqrt_s_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR) {…}

    emit_fsub_d ¶
    Source

    emit_fsub_d :: emit_fsub_d_fpr_fpr_fpr

    emit_fsub_d_fpr_fpr_fpr ¶
    Source

    emit_fsub_d_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fsub_s ¶
    Source

    emit_fsub_s :: emit_fsub_s_fpr_fpr_fpr

    emit_fsub_s_fpr_fpr_fpr ¶
    Source

    emit_fsub_s_fpr_fpr_fpr :: proc(instructions: ^[dynamic]Instruction, rd: FPR, rs1: FPR, rs2: FPR) {…}

    emit_fsw ¶
    Source

    emit_fsw :: emit_fsw_fpr_mem

    emit_fsw_fpr_mem ¶
    Source

    emit_fsw_fpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: FPR, mem: Memory) {…}

    emit_jal ¶
    Source

    emit_jal :: emit_jal_gpr_label

    emit_jal_gpr_label ¶
    Source

    emit_jal_gpr_label :: proc(instructions: ^[dynamic]Instruction, rd: GPR, label: u32) {…}

    emit_jalr ¶
    Source

    emit_jalr_gpr_gpr_imm12 ¶
    Source

    emit_jalr_gpr_gpr_imm12 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_lb ¶
    Source

    emit_lb :: emit_lb_gpr_mem

    emit_lb_gpr_mem ¶
    Source

    emit_lb_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_lbu ¶
    Source

    emit_lbu :: emit_lbu_gpr_mem

    emit_lbu_gpr_mem ¶
    Source

    emit_lbu_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_ld ¶
    Source

    emit_ld :: emit_ld_gpr_mem

    emit_ld_gpr_mem ¶
    Source

    emit_ld_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_lh ¶
    Source

    emit_lh :: emit_lh_gpr_mem

    emit_lh_gpr_mem ¶
    Source

    emit_lh_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_lhu ¶
    Source

    emit_lhu :: emit_lhu_gpr_mem

    emit_lhu_gpr_mem ¶
    Source

    emit_lhu_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_lr_d ¶
    Source

    emit_lr_d :: emit_lr_d_gpr_mem

    emit_lr_d_gpr_mem ¶
    Source

    emit_lr_d_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_lr_w ¶
    Source

    emit_lr_w :: emit_lr_w_gpr_mem

    emit_lr_w_gpr_mem ¶
    Source

    emit_lr_w_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_lui ¶
    Source

    emit_lui :: emit_lui_gpr_imm20

    emit_lui_gpr_imm20 ¶
    Source

    emit_lui_gpr_imm20 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, imm: i64) {…}

    emit_lw ¶
    Source

    emit_lw :: emit_lw_gpr_mem

    emit_lw_gpr_mem ¶
    Source

    emit_lw_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_lwu ¶
    Source

    emit_lwu :: emit_lwu_gpr_mem

    emit_lwu_gpr_mem ¶
    Source

    emit_lwu_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_mul ¶
    Source

    emit_mul :: emit_mul_gpr_gpr_gpr

    emit_mul_gpr_gpr_gpr ¶
    Source

    emit_mul_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_mulh ¶
    Source

    emit_mulh :: emit_mulh_gpr_gpr_gpr

    emit_mulh_gpr_gpr_gpr ¶
    Source

    emit_mulh_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_mulhsu ¶
    Source

    emit_mulhsu :: emit_mulhsu_gpr_gpr_gpr

    emit_mulhsu_gpr_gpr_gpr ¶
    Source

    emit_mulhsu_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_mulhu ¶
    Source

    emit_mulhu :: emit_mulhu_gpr_gpr_gpr

    emit_mulhu_gpr_gpr_gpr ¶
    Source

    emit_mulhu_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_mulw ¶
    Source

    emit_mulw :: emit_mulw_gpr_gpr_gpr

    emit_mulw_gpr_gpr_gpr ¶
    Source

    emit_mulw_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_or ¶
    Source

    emit_or :: emit_or_gpr_gpr_gpr

    emit_or_gpr_gpr_gpr ¶
    Source

    emit_or_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_ori ¶
    Source

    emit_ori_gpr_gpr_imm12 ¶
    Source

    emit_ori_gpr_gpr_imm12 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_rem ¶
    Source

    emit_rem :: emit_rem_gpr_gpr_gpr

    emit_rem_gpr_gpr_gpr ¶
    Source

    emit_rem_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_remu ¶
    Source

    emit_remu :: emit_remu_gpr_gpr_gpr

    emit_remu_gpr_gpr_gpr ¶
    Source

    emit_remu_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_remuw ¶
    Source

    emit_remuw :: emit_remuw_gpr_gpr_gpr

    emit_remuw_gpr_gpr_gpr ¶
    Source

    emit_remuw_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_remw ¶
    Source

    emit_remw :: emit_remw_gpr_gpr_gpr

    emit_remw_gpr_gpr_gpr ¶
    Source

    emit_remw_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_sb ¶
    Source

    emit_sb :: emit_sb_gpr_mem

    emit_sb_gpr_mem ¶
    Source

    emit_sb_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_sc_d ¶
    Source

    emit_sc_d :: emit_sc_d_gpr_gpr_mem

    emit_sc_d_gpr_gpr_mem ¶
    Source

    emit_sc_d_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_sc_w ¶
    Source

    emit_sc_w :: emit_sc_w_gpr_gpr_mem

    emit_sc_w_gpr_gpr_mem ¶
    Source

    emit_sc_w_gpr_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, mem: Memory) {…}

    emit_sd ¶
    Source

    emit_sd :: emit_sd_gpr_mem

    emit_sd_gpr_mem ¶
    Source

    emit_sd_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_sh ¶
    Source

    emit_sh :: emit_sh_gpr_mem

    emit_sh_gpr_mem ¶
    Source

    emit_sh_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_sll ¶
    Source

    emit_sll :: emit_sll_gpr_gpr_gpr

    emit_sll_gpr_gpr_gpr ¶
    Source

    emit_sll_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_slli ¶
    Source

    emit_slli :: emit_slli_gpr_gpr_imm6

    emit_slli_gpr_gpr_imm6 ¶
    Source

    emit_slli_gpr_gpr_imm6 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_slliw ¶
    Source

    emit_slliw :: emit_slliw_gpr_gpr_imm5

    emit_slliw_gpr_gpr_imm5 ¶
    Source

    emit_slliw_gpr_gpr_imm5 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_sllw ¶
    Source

    emit_sllw :: emit_sllw_gpr_gpr_gpr

    emit_sllw_gpr_gpr_gpr ¶
    Source

    emit_sllw_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_slt ¶
    Source

    emit_slt :: emit_slt_gpr_gpr_gpr

    emit_slt_gpr_gpr_gpr ¶
    Source

    emit_slt_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_slti ¶
    Source

    emit_slti_gpr_gpr_imm12 ¶
    Source

    emit_slti_gpr_gpr_imm12 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_sltiu ¶
    Source

    emit_sltiu :: emit_sltiu_gpr_gpr_imm12

    emit_sltiu_gpr_gpr_imm12 ¶
    Source

    emit_sltiu_gpr_gpr_imm12 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_sltu ¶
    Source

    emit_sltu :: emit_sltu_gpr_gpr_gpr

    emit_sltu_gpr_gpr_gpr ¶
    Source

    emit_sltu_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_sra ¶
    Source

    emit_sra :: emit_sra_gpr_gpr_gpr

    emit_sra_gpr_gpr_gpr ¶
    Source

    emit_sra_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_srai ¶
    Source

    emit_srai :: emit_srai_gpr_gpr_imm6

    emit_srai_gpr_gpr_imm6 ¶
    Source

    emit_srai_gpr_gpr_imm6 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_sraiw ¶
    Source

    emit_sraiw :: emit_sraiw_gpr_gpr_imm5

    emit_sraiw_gpr_gpr_imm5 ¶
    Source

    emit_sraiw_gpr_gpr_imm5 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_sraw ¶
    Source

    emit_sraw :: emit_sraw_gpr_gpr_gpr

    emit_sraw_gpr_gpr_gpr ¶
    Source

    emit_sraw_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_srl ¶
    Source

    emit_srl :: emit_srl_gpr_gpr_gpr

    emit_srl_gpr_gpr_gpr ¶
    Source

    emit_srl_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_srli ¶
    Source

    emit_srli :: emit_srli_gpr_gpr_imm6

    emit_srli_gpr_gpr_imm6 ¶
    Source

    emit_srli_gpr_gpr_imm6 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_srliw ¶
    Source

    emit_srliw :: emit_srliw_gpr_gpr_imm5

    emit_srliw_gpr_gpr_imm5 ¶
    Source

    emit_srliw_gpr_gpr_imm5 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    emit_srlw ¶
    Source

    emit_srlw :: emit_srlw_gpr_gpr_gpr

    emit_srlw_gpr_gpr_gpr ¶
    Source

    emit_srlw_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_sub ¶
    Source

    emit_sub :: emit_sub_gpr_gpr_gpr

    emit_sub_gpr_gpr_gpr ¶
    Source

    emit_sub_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_subw ¶
    Source

    emit_subw :: emit_subw_gpr_gpr_gpr

    emit_subw_gpr_gpr_gpr ¶
    Source

    emit_subw_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_sw ¶
    Source

    emit_sw :: emit_sw_gpr_mem

    emit_sw_gpr_mem ¶
    Source

    emit_sw_gpr_mem :: proc(instructions: ^[dynamic]Instruction, rd: GPR, mem: Memory) {…}

    emit_xor ¶
    Source

    emit_xor :: emit_xor_gpr_gpr_gpr

    emit_xor_gpr_gpr_gpr ¶
    Source

    emit_xor_gpr_gpr_gpr :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, rs2: GPR) {…}

    emit_xori ¶
    Source

    emit_xori_gpr_gpr_imm12 ¶
    Source

    emit_xori_gpr_gpr_imm12 :: proc(instructions: ^[dynamic]Instruction, rd: GPR, rs1: GPR, imm: i64) {…}

    encode ¶
    Source

    encode :: proc(
	instructions: []Instruction, 
	label_defs:   []rexcode_isa.Label_Definition, 
	code:         []u8, 
	relocs:       ^[dynamic]Relocation, 
	errors:       ^[dynamic]rexcode_isa.Error, 
	resolve:      bool = true, 
	base_address: u64 = 0, 
) -> (byte_count: u32, ok: bool) {…}

    encode_max_code_size ¶
    Source

    encode_max_code_size :: proc "contextless" (instructions: []Instruction) -> int {…}

    encode_max_relocation_count ¶
    Source

    encode_max_relocation_count :: proc "contextless" (instructions: []Instruction) -> int {…}

    encode_reserve ¶
    Source

    encode_reserve :: proc(code: ^[dynamic]u8, relocs: ^[dynamic]Relocation, instructions: []Instruction) {…}
     

    Pre-size the caller's encode outputs (code grown by length so code[:] is a valid emit target; relocs reserved by capacity) so the encode hot path never reallocates. Allocates no new buffers; pass nil to skip either array.

    fpr_from_num ¶
    Source

    fpr_from_num :: proc "contextless" (n: u8) -> Register {…}

    fprint ¶
    Source

    fprint :: proc(
	fd:           ^os.File, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    fprintln ¶
    Source

    fprintln :: proc(
	fd:           ^os.File, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    gpr_from_num ¶
    Source

    gpr_from_num :: proc "contextless" (n: u8) -> Register {…}

    inst_add ¶
    Source

    inst_add :: inst_add_gpr_gpr_gpr

    inst_add_gpr_gpr_gpr ¶
    Source

    inst_add_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_addi ¶
    Source

    inst_addi_gpr_gpr_imm12 ¶
    Source

    inst_addi_gpr_gpr_imm12 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_addiw ¶
    Source

    inst_addiw :: inst_addiw_gpr_gpr_imm12

    inst_addiw_gpr_gpr_imm12 ¶
    Source

    inst_addiw_gpr_gpr_imm12 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_addw ¶
    Source

    inst_addw :: inst_addw_gpr_gpr_gpr

    inst_addw_gpr_gpr_gpr ¶
    Source

    inst_addw_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_amoadd_d ¶
    Source

    inst_amoadd_d :: inst_amoadd_d_gpr_gpr_mem

    inst_amoadd_d_gpr_gpr_mem ¶
    Source

    inst_amoadd_d_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amoadd_w ¶
    Source

    inst_amoadd_w :: inst_amoadd_w_gpr_gpr_mem

    inst_amoadd_w_gpr_gpr_mem ¶
    Source

    inst_amoadd_w_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amoand_d ¶
    Source

    inst_amoand_d :: inst_amoand_d_gpr_gpr_mem

    inst_amoand_d_gpr_gpr_mem ¶
    Source

    inst_amoand_d_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amoand_w ¶
    Source

    inst_amoand_w :: inst_amoand_w_gpr_gpr_mem

    inst_amoand_w_gpr_gpr_mem ¶
    Source

    inst_amoand_w_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amomax_d ¶
    Source

    inst_amomax_d :: inst_amomax_d_gpr_gpr_mem

    inst_amomax_d_gpr_gpr_mem ¶
    Source

    inst_amomax_d_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amomax_w ¶
    Source

    inst_amomax_w :: inst_amomax_w_gpr_gpr_mem

    inst_amomax_w_gpr_gpr_mem ¶
    Source

    inst_amomax_w_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amomaxu_d ¶
    Source

    inst_amomaxu_d :: inst_amomaxu_d_gpr_gpr_mem

    inst_amomaxu_d_gpr_gpr_mem ¶
    Source

    inst_amomaxu_d_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amomaxu_w ¶
    Source

    inst_amomaxu_w :: inst_amomaxu_w_gpr_gpr_mem

    inst_amomaxu_w_gpr_gpr_mem ¶
    Source

    inst_amomaxu_w_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amomin_d ¶
    Source

    inst_amomin_d :: inst_amomin_d_gpr_gpr_mem

    inst_amomin_d_gpr_gpr_mem ¶
    Source

    inst_amomin_d_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amomin_w ¶
    Source

    inst_amomin_w :: inst_amomin_w_gpr_gpr_mem

    inst_amomin_w_gpr_gpr_mem ¶
    Source

    inst_amomin_w_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amominu_d ¶
    Source

    inst_amominu_d :: inst_amominu_d_gpr_gpr_mem

    inst_amominu_d_gpr_gpr_mem ¶
    Source

    inst_amominu_d_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amominu_w ¶
    Source

    inst_amominu_w :: inst_amominu_w_gpr_gpr_mem

    inst_amominu_w_gpr_gpr_mem ¶
    Source

    inst_amominu_w_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amoor_d ¶
    Source

    inst_amoor_d :: inst_amoor_d_gpr_gpr_mem

    inst_amoor_d_gpr_gpr_mem ¶
    Source

    inst_amoor_d_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amoor_w ¶
    Source

    inst_amoor_w :: inst_amoor_w_gpr_gpr_mem

    inst_amoor_w_gpr_gpr_mem ¶
    Source

    inst_amoor_w_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amoswap_d ¶
    Source

    inst_amoswap_d :: inst_amoswap_d_gpr_gpr_mem

    inst_amoswap_d_gpr_gpr_mem ¶
    Source

    inst_amoswap_d_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amoswap_w ¶
    Source

    inst_amoswap_w :: inst_amoswap_w_gpr_gpr_mem

    inst_amoswap_w_gpr_gpr_mem ¶
    Source

    inst_amoswap_w_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amoxor_d ¶
    Source

    inst_amoxor_d :: inst_amoxor_d_gpr_gpr_mem

    inst_amoxor_d_gpr_gpr_mem ¶
    Source

    inst_amoxor_d_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_amoxor_w ¶
    Source

    inst_amoxor_w :: inst_amoxor_w_gpr_gpr_mem

    inst_amoxor_w_gpr_gpr_mem ¶
    Source

    inst_amoxor_w_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_and ¶
    Source

    inst_and :: inst_and_gpr_gpr_gpr

    inst_and_gpr_gpr_gpr ¶
    Source

    inst_and_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_andi ¶
    Source

    inst_andi_gpr_gpr_imm12 ¶
    Source

    inst_andi_gpr_gpr_imm12 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_auipc ¶
    Source

    inst_auipc :: inst_auipc_gpr_imm20

    inst_auipc_gpr_imm20 ¶
    Source

    inst_auipc_gpr_imm20 :: proc "contextless" (rd: GPR, imm: i64) -> Instruction {…}

    inst_beq ¶
    Source

    inst_beq_gpr_gpr_label ¶
    Source

    inst_beq_gpr_gpr_label :: proc "contextless" (rd: GPR, rs1: GPR, label: u32) -> Instruction {…}

    inst_bge ¶
    Source

    inst_bge_gpr_gpr_label ¶
    Source

    inst_bge_gpr_gpr_label :: proc "contextless" (rd: GPR, rs1: GPR, label: u32) -> Instruction {…}

    inst_bgeu ¶
    Source

    inst_bgeu_gpr_gpr_label ¶
    Source

    inst_bgeu_gpr_gpr_label :: proc "contextless" (rd: GPR, rs1: GPR, label: u32) -> Instruction {…}

    inst_blt ¶
    Source

    inst_blt_gpr_gpr_label ¶
    Source

    inst_blt_gpr_gpr_label :: proc "contextless" (rd: GPR, rs1: GPR, label: u32) -> Instruction {…}

    inst_bltu ¶
    Source

    inst_bltu_gpr_gpr_label ¶
    Source

    inst_bltu_gpr_gpr_label :: proc "contextless" (rd: GPR, rs1: GPR, label: u32) -> Instruction {…}

    inst_bne ¶
    Source

    inst_bne_gpr_gpr_label ¶
    Source

    inst_bne_gpr_gpr_label :: proc "contextless" (rd: GPR, rs1: GPR, label: u32) -> Instruction {…}

    inst_branch ¶
    Source

    inst_branch :: proc "contextless" (m: Mnemonic, rs1, rs2: Register, label_id: u32) -> Instruction {…}
     

    B-type branch: rs1, rs2, label

    inst_c_add ¶
    Source

    inst_c_add :: inst_c_add_gpr_gpr

    inst_c_add_gpr_gpr ¶
    Source

    inst_c_add_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR) -> Instruction {…}

    inst_c_addi ¶
    Source

    inst_c_addi :: inst_c_addi_gpr_imm6s

    inst_c_addi16sp ¶
    Source

    inst_c_addi16sp :: inst_c_addi16sp_gpr_imm10s

    inst_c_addi16sp_gpr_imm10s ¶
    Source

    inst_c_addi16sp_gpr_imm10s :: proc "contextless" (rd: GPR, imm: i64) -> Instruction {…}

    inst_c_addi4spn ¶
    Source

    inst_c_addi4spn :: inst_c_addi4spn_gpr_gpr_imm8u

    inst_c_addi4spn_gpr_gpr_imm8u ¶
    Source

    inst_c_addi4spn_gpr_gpr_imm8u :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_c_addi_gpr_imm6s ¶
    Source

    inst_c_addi_gpr_imm6s :: proc "contextless" (rd: GPR, imm: i64) -> Instruction {…}

    inst_c_addiw ¶
    Source

    inst_c_addiw :: inst_c_addiw_gpr_imm6s

    inst_c_addiw_gpr_imm6s ¶
    Source

    inst_c_addiw_gpr_imm6s :: proc "contextless" (rd: GPR, imm: i64) -> Instruction {…}

    inst_c_addw ¶
    Source

    inst_c_addw :: inst_c_addw_gpr_gpr

    inst_c_addw_gpr_gpr ¶
    Source

    inst_c_addw_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR) -> Instruction {…}

    inst_c_and ¶
    Source

    inst_c_and :: inst_c_and_gpr_gpr

    inst_c_and_gpr_gpr ¶
    Source

    inst_c_and_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR) -> Instruction {…}

    inst_c_andi ¶
    Source

    inst_c_andi :: inst_c_andi_gpr_imm6s

    inst_c_andi_gpr_imm6s ¶
    Source

    inst_c_andi_gpr_imm6s :: proc "contextless" (rd: GPR, imm: i64) -> Instruction {…}

    inst_c_beqz ¶
    Source

    inst_c_beqz :: inst_c_beqz_gpr_label

    inst_c_beqz_gpr_label ¶
    Source

    inst_c_beqz_gpr_label :: proc "contextless" (rd: GPR, label: u32) -> Instruction {…}

    inst_c_bnez ¶
    Source

    inst_c_bnez :: inst_c_bnez_gpr_label

    inst_c_bnez_gpr_label ¶
    Source

    inst_c_bnez_gpr_label :: proc "contextless" (rd: GPR, label: u32) -> Instruction {…}

    inst_c_ebreak ¶
    Source

    inst_c_ebreak :: inst_c_ebreak_none

    inst_c_ebreak_none ¶
    Source

    inst_c_ebreak_none :: proc "contextless" () -> Instruction {…}

    inst_c_fld ¶
    Source

    inst_c_fld :: inst_c_fld_fpr_mem

    inst_c_fld_fpr_mem ¶
    Source

    inst_c_fld_fpr_mem :: proc "contextless" (rd: FPR, mem: Memory) -> Instruction {…}

    inst_c_fldsp ¶
    Source

    inst_c_fldsp :: inst_c_fldsp_fpr_mem

    inst_c_fldsp_fpr_mem ¶
    Source

    inst_c_fldsp_fpr_mem :: proc "contextless" (rd: FPR, mem: Memory) -> Instruction {…}

    inst_c_fsd ¶
    Source

    inst_c_fsd :: inst_c_fsd_fpr_mem

    inst_c_fsd_fpr_mem ¶
    Source

    inst_c_fsd_fpr_mem :: proc "contextless" (rd: FPR, mem: Memory) -> Instruction {…}

    inst_c_fsdsp ¶
    Source

    inst_c_fsdsp :: inst_c_fsdsp_fpr_mem

    inst_c_fsdsp_fpr_mem ¶
    Source

    inst_c_fsdsp_fpr_mem :: proc "contextless" (rd: FPR, mem: Memory) -> Instruction {…}

    inst_c_j ¶
    Source

    inst_c_j :: inst_c_j_label

    inst_c_j_label ¶
    Source

    inst_c_j_label :: proc "contextless" (label: u32) -> Instruction {…}

    inst_c_jal ¶
    Source

    inst_c_jal :: inst_c_jal_label

    inst_c_jal_label ¶
    Source

    inst_c_jal_label :: proc "contextless" (label: u32) -> Instruction {…}

    inst_c_jalr ¶
    Source

    inst_c_jalr :: inst_c_jalr_gpr

    inst_c_jalr_gpr ¶
    Source

    inst_c_jalr_gpr :: proc "contextless" (rd: GPR) -> Instruction {…}

    inst_c_jr ¶
    Source

    inst_c_jr :: inst_c_jr_gpr

    inst_c_jr_gpr ¶
    Source

    inst_c_jr_gpr :: proc "contextless" (rd: GPR) -> Instruction {…}

    inst_c_ld ¶
    Source

    inst_c_ld :: inst_c_ld_gpr_mem

    inst_c_ld_gpr_mem ¶
    Source

    inst_c_ld_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_c_ldsp ¶
    Source

    inst_c_ldsp :: inst_c_ldsp_gpr_mem

    inst_c_ldsp_gpr_mem ¶
    Source

    inst_c_ldsp_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_c_li ¶
    Source

    inst_c_li :: inst_c_li_gpr_imm6s

    inst_c_li_gpr_imm6s ¶
    Source

    inst_c_li_gpr_imm6s :: proc "contextless" (rd: GPR, imm: i64) -> Instruction {…}

    inst_c_lui ¶
    Source

    inst_c_lui :: inst_c_lui_gpr_imm18s

    inst_c_lui_gpr_imm18s ¶
    Source

    inst_c_lui_gpr_imm18s :: proc "contextless" (rd: GPR, imm: i64) -> Instruction {…}

    inst_c_lw ¶
    Source

    inst_c_lw :: inst_c_lw_gpr_mem

    inst_c_lw_gpr_mem ¶
    Source

    inst_c_lw_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_c_lwsp ¶
    Source

    inst_c_lwsp :: inst_c_lwsp_gpr_mem

    inst_c_lwsp_gpr_mem ¶
    Source

    inst_c_lwsp_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_c_mv ¶
    Source

    inst_c_mv :: inst_c_mv_gpr_gpr

    inst_c_mv_gpr_gpr ¶
    Source

    inst_c_mv_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR) -> Instruction {…}

    inst_c_nop ¶
    Source

    inst_c_nop :: inst_c_nop_none

    inst_c_nop_none ¶
    Source

    inst_c_nop_none :: proc "contextless" () -> Instruction {…}

    inst_c_or ¶
    Source

    inst_c_or :: inst_c_or_gpr_gpr

    inst_c_or_gpr_gpr ¶
    Source

    inst_c_or_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR) -> Instruction {…}

    inst_c_sd ¶
    Source

    inst_c_sd :: inst_c_sd_gpr_mem

    inst_c_sd_gpr_mem ¶
    Source

    inst_c_sd_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_c_sdsp ¶
    Source

    inst_c_sdsp :: inst_c_sdsp_gpr_mem

    inst_c_sdsp_gpr_mem ¶
    Source

    inst_c_sdsp_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_c_slli ¶
    Source

    inst_c_slli :: inst_c_slli_gpr_imm6u

    inst_c_slli_gpr_imm6u ¶
    Source

    inst_c_slli_gpr_imm6u :: proc "contextless" (rd: GPR, imm: i64) -> Instruction {…}

    inst_c_srai ¶
    Source

    inst_c_srai :: inst_c_srai_gpr_imm6u

    inst_c_srai_gpr_imm6u ¶
    Source

    inst_c_srai_gpr_imm6u :: proc "contextless" (rd: GPR, imm: i64) -> Instruction {…}

    inst_c_srli ¶
    Source

    inst_c_srli :: inst_c_srli_gpr_imm6u

    inst_c_srli_gpr_imm6u ¶
    Source

    inst_c_srli_gpr_imm6u :: proc "contextless" (rd: GPR, imm: i64) -> Instruction {…}

    inst_c_sub ¶
    Source

    inst_c_sub :: inst_c_sub_gpr_gpr

    inst_c_sub_gpr_gpr ¶
    Source

    inst_c_sub_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR) -> Instruction {…}

    inst_c_subw ¶
    Source

    inst_c_subw :: inst_c_subw_gpr_gpr

    inst_c_subw_gpr_gpr ¶
    Source

    inst_c_subw_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR) -> Instruction {…}

    inst_c_sw ¶
    Source

    inst_c_sw :: inst_c_sw_gpr_mem

    inst_c_sw_gpr_mem ¶
    Source

    inst_c_sw_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_c_swsp ¶
    Source

    inst_c_swsp :: inst_c_swsp_gpr_mem

    inst_c_swsp_gpr_mem ¶
    Source

    inst_c_swsp_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_c_xor ¶
    Source

    inst_c_xor :: inst_c_xor_gpr_gpr

    inst_c_xor_gpr_gpr ¶
    Source

    inst_c_xor_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR) -> Instruction {…}

    inst_csr ¶
    Source

    inst_csr :: proc "contextless" (m: Mnemonic, rd: Register, csr: u16, rs1: Register) -> Instruction {…}
     

    CSR ops: rd, csr, rs1

    inst_csr_i ¶
    Source

    inst_csr_i :: proc "contextless" (m: Mnemonic, rd: Register, csr: u16, zimm5: u8) -> Instruction {…}
     

    CSR immediate ops: rd, csr, zimm5

    inst_csrrc ¶
    Source

    inst_csrrc :: inst_csrrc_gpr_csr_gpr

    inst_csrrc_gpr_csr_gpr ¶
    Source

    inst_csrrc_gpr_csr_gpr :: proc "contextless" (rd: GPR, imm: i64, rs1: GPR) -> Instruction {…}

    inst_csrrci ¶
    Source

    inst_csrrci :: inst_csrrci_gpr_csr_zimm5

    inst_csrrci_gpr_csr_zimm5 ¶
    Source

    inst_csrrci_gpr_csr_zimm5 :: proc "contextless" (rd: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_csrrs ¶
    Source

    inst_csrrs :: inst_csrrs_gpr_csr_gpr

    inst_csrrs_gpr_csr_gpr ¶
    Source

    inst_csrrs_gpr_csr_gpr :: proc "contextless" (rd: GPR, imm: i64, rs1: GPR) -> Instruction {…}

    inst_csrrsi ¶
    Source

    inst_csrrsi :: inst_csrrsi_gpr_csr_zimm5

    inst_csrrsi_gpr_csr_zimm5 ¶
    Source

    inst_csrrsi_gpr_csr_zimm5 :: proc "contextless" (rd: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_csrrw ¶
    Source

    inst_csrrw :: inst_csrrw_gpr_csr_gpr

    inst_csrrw_gpr_csr_gpr ¶
    Source

    inst_csrrw_gpr_csr_gpr :: proc "contextless" (rd: GPR, imm: i64, rs1: GPR) -> Instruction {…}

    inst_csrrwi ¶
    Source

    inst_csrrwi :: inst_csrrwi_gpr_csr_zimm5

    inst_csrrwi_gpr_csr_zimm5 ¶
    Source

    inst_csrrwi_gpr_csr_zimm5 :: proc "contextless" (rd: GPR, imm: i64, imm2: i64) -> Instruction {…}

    inst_div ¶
    Source

    inst_div :: inst_div_gpr_gpr_gpr

    inst_div_gpr_gpr_gpr ¶
    Source

    inst_div_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_divu ¶
    Source

    inst_divu :: inst_divu_gpr_gpr_gpr

    inst_divu_gpr_gpr_gpr ¶
    Source

    inst_divu_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_divuw ¶
    Source

    inst_divuw :: inst_divuw_gpr_gpr_gpr

    inst_divuw_gpr_gpr_gpr ¶
    Source

    inst_divuw_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_divw ¶
    Source

    inst_divw :: inst_divw_gpr_gpr_gpr

    inst_divw_gpr_gpr_gpr ¶
    Source

    inst_divw_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_ebreak ¶
    Source

    inst_ebreak :: inst_ebreak_none

    inst_ebreak_none ¶
    Source

    inst_ebreak_none :: proc "contextless" () -> Instruction {…}

    inst_ecall ¶
    Source

    inst_ecall :: inst_ecall_none

    inst_ecall_none ¶
    Source

    inst_ecall_none :: proc "contextless" () -> Instruction {…}

    inst_fadd_d ¶
    Source

    inst_fadd_d :: inst_fadd_d_fpr_fpr_fpr

    inst_fadd_d_fpr_fpr_fpr ¶
    Source

    inst_fadd_d_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fadd_s ¶
    Source

    inst_fadd_s :: inst_fadd_s_fpr_fpr_fpr

    inst_fadd_s_fpr_fpr_fpr ¶
    Source

    inst_fadd_s_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fclass_d ¶
    Source

    inst_fclass_d :: inst_fclass_d_gpr_fpr

    inst_fclass_d_gpr_fpr ¶
    Source

    inst_fclass_d_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fclass_s ¶
    Source

    inst_fclass_s :: inst_fclass_s_gpr_fpr

    inst_fclass_s_gpr_fpr ¶
    Source

    inst_fclass_s_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fcvt_d_l ¶
    Source

    inst_fcvt_d_l :: inst_fcvt_d_l_fpr_gpr

    inst_fcvt_d_l_fpr_gpr ¶
    Source

    inst_fcvt_d_l_fpr_gpr :: proc "contextless" (rd: FPR, rs1: GPR) -> Instruction {…}

    inst_fcvt_d_lu ¶
    Source

    inst_fcvt_d_lu :: inst_fcvt_d_lu_fpr_gpr

    inst_fcvt_d_lu_fpr_gpr ¶
    Source

    inst_fcvt_d_lu_fpr_gpr :: proc "contextless" (rd: FPR, rs1: GPR) -> Instruction {…}

    inst_fcvt_d_s ¶
    Source

    inst_fcvt_d_s :: inst_fcvt_d_s_fpr_fpr

    inst_fcvt_d_s_fpr_fpr ¶
    Source

    inst_fcvt_d_s_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR) -> Instruction {…}

    inst_fcvt_d_w ¶
    Source

    inst_fcvt_d_w :: inst_fcvt_d_w_fpr_gpr

    inst_fcvt_d_w_fpr_gpr ¶
    Source

    inst_fcvt_d_w_fpr_gpr :: proc "contextless" (rd: FPR, rs1: GPR) -> Instruction {…}

    inst_fcvt_d_wu ¶
    Source

    inst_fcvt_d_wu :: inst_fcvt_d_wu_fpr_gpr

    inst_fcvt_d_wu_fpr_gpr ¶
    Source

    inst_fcvt_d_wu_fpr_gpr :: proc "contextless" (rd: FPR, rs1: GPR) -> Instruction {…}

    inst_fcvt_l_d ¶
    Source

    inst_fcvt_l_d :: inst_fcvt_l_d_gpr_fpr

    inst_fcvt_l_d_gpr_fpr ¶
    Source

    inst_fcvt_l_d_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fcvt_l_s ¶
    Source

    inst_fcvt_l_s :: inst_fcvt_l_s_gpr_fpr

    inst_fcvt_l_s_gpr_fpr ¶
    Source

    inst_fcvt_l_s_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fcvt_lu_d ¶
    Source

    inst_fcvt_lu_d :: inst_fcvt_lu_d_gpr_fpr

    inst_fcvt_lu_d_gpr_fpr ¶
    Source

    inst_fcvt_lu_d_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fcvt_lu_s ¶
    Source

    inst_fcvt_lu_s :: inst_fcvt_lu_s_gpr_fpr

    inst_fcvt_lu_s_gpr_fpr ¶
    Source

    inst_fcvt_lu_s_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fcvt_s_d ¶
    Source

    inst_fcvt_s_d :: inst_fcvt_s_d_fpr_fpr

    inst_fcvt_s_d_fpr_fpr ¶
    Source

    inst_fcvt_s_d_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR) -> Instruction {…}

    inst_fcvt_s_l ¶
    Source

    inst_fcvt_s_l :: inst_fcvt_s_l_fpr_gpr

    inst_fcvt_s_l_fpr_gpr ¶
    Source

    inst_fcvt_s_l_fpr_gpr :: proc "contextless" (rd: FPR, rs1: GPR) -> Instruction {…}

    inst_fcvt_s_lu ¶
    Source

    inst_fcvt_s_lu :: inst_fcvt_s_lu_fpr_gpr

    inst_fcvt_s_lu_fpr_gpr ¶
    Source

    inst_fcvt_s_lu_fpr_gpr :: proc "contextless" (rd: FPR, rs1: GPR) -> Instruction {…}

    inst_fcvt_s_w ¶
    Source

    inst_fcvt_s_w :: inst_fcvt_s_w_fpr_gpr

    inst_fcvt_s_w_fpr_gpr ¶
    Source

    inst_fcvt_s_w_fpr_gpr :: proc "contextless" (rd: FPR, rs1: GPR) -> Instruction {…}

    inst_fcvt_s_wu ¶
    Source

    inst_fcvt_s_wu :: inst_fcvt_s_wu_fpr_gpr

    inst_fcvt_s_wu_fpr_gpr ¶
    Source

    inst_fcvt_s_wu_fpr_gpr :: proc "contextless" (rd: FPR, rs1: GPR) -> Instruction {…}

    inst_fcvt_w_d ¶
    Source

    inst_fcvt_w_d :: inst_fcvt_w_d_gpr_fpr

    inst_fcvt_w_d_gpr_fpr ¶
    Source

    inst_fcvt_w_d_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fcvt_w_s ¶
    Source

    inst_fcvt_w_s :: inst_fcvt_w_s_gpr_fpr

    inst_fcvt_w_s_gpr_fpr ¶
    Source

    inst_fcvt_w_s_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fcvt_wu_d ¶
    Source

    inst_fcvt_wu_d :: inst_fcvt_wu_d_gpr_fpr

    inst_fcvt_wu_d_gpr_fpr ¶
    Source

    inst_fcvt_wu_d_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fcvt_wu_s ¶
    Source

    inst_fcvt_wu_s :: inst_fcvt_wu_s_gpr_fpr

    inst_fcvt_wu_s_gpr_fpr ¶
    Source

    inst_fcvt_wu_s_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fdiv_d ¶
    Source

    inst_fdiv_d :: inst_fdiv_d_fpr_fpr_fpr

    inst_fdiv_d_fpr_fpr_fpr ¶
    Source

    inst_fdiv_d_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fdiv_s ¶
    Source

    inst_fdiv_s :: inst_fdiv_s_fpr_fpr_fpr

    inst_fdiv_s_fpr_fpr_fpr ¶
    Source

    inst_fdiv_s_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fence ¶
    Source

    inst_fence :: inst_fence_fence_fence

    inst_fence_fence_fence ¶
    Source

    inst_fence_fence_fence :: proc "contextless" (imm: i64, imm2: i64) -> Instruction {…}

    inst_fence_i ¶
    Source

    inst_fence_i :: inst_fence_i_none

    inst_fence_i_none ¶
    Source

    inst_fence_i_none :: proc "contextless" () -> Instruction {…}

    inst_feq_d ¶
    Source

    inst_feq_d :: inst_feq_d_gpr_fpr_fpr

    inst_feq_d_gpr_fpr_fpr ¶
    Source

    inst_feq_d_gpr_fpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_feq_s ¶
    Source

    inst_feq_s :: inst_feq_s_gpr_fpr_fpr

    inst_feq_s_gpr_fpr_fpr ¶
    Source

    inst_feq_s_gpr_fpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fld ¶
    Source

    inst_fld :: inst_fld_fpr_mem

    inst_fld_fpr_mem ¶
    Source

    inst_fld_fpr_mem :: proc "contextless" (rd: FPR, mem: Memory) -> Instruction {…}

    inst_fle_d ¶
    Source

    inst_fle_d :: inst_fle_d_gpr_fpr_fpr

    inst_fle_d_gpr_fpr_fpr ¶
    Source

    inst_fle_d_gpr_fpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fle_s ¶
    Source

    inst_fle_s :: inst_fle_s_gpr_fpr_fpr

    inst_fle_s_gpr_fpr_fpr ¶
    Source

    inst_fle_s_gpr_fpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_flt_d ¶
    Source

    inst_flt_d :: inst_flt_d_gpr_fpr_fpr

    inst_flt_d_gpr_fpr_fpr ¶
    Source

    inst_flt_d_gpr_fpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_flt_s ¶
    Source

    inst_flt_s :: inst_flt_s_gpr_fpr_fpr

    inst_flt_s_gpr_fpr_fpr ¶
    Source

    inst_flt_s_gpr_fpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_flw ¶
    Source

    inst_flw :: inst_flw_fpr_mem

    inst_flw_fpr_mem ¶
    Source

    inst_flw_fpr_mem :: proc "contextless" (rd: FPR, mem: Memory) -> Instruction {…}

    inst_fmadd_d ¶
    Source

    inst_fmadd_d_fpr_fpr_fpr_fpr ¶
    Source

    inst_fmadd_d_fpr_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) -> Instruction {…}

    inst_fmadd_s ¶
    Source

    inst_fmadd_s_fpr_fpr_fpr_fpr ¶
    Source

    inst_fmadd_s_fpr_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) -> Instruction {…}

    inst_fmax_d ¶
    Source

    inst_fmax_d :: inst_fmax_d_fpr_fpr_fpr

    inst_fmax_d_fpr_fpr_fpr ¶
    Source

    inst_fmax_d_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fmax_s ¶
    Source

    inst_fmax_s :: inst_fmax_s_fpr_fpr_fpr

    inst_fmax_s_fpr_fpr_fpr ¶
    Source

    inst_fmax_s_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fmin_d ¶
    Source

    inst_fmin_d :: inst_fmin_d_fpr_fpr_fpr

    inst_fmin_d_fpr_fpr_fpr ¶
    Source

    inst_fmin_d_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fmin_s ¶
    Source

    inst_fmin_s :: inst_fmin_s_fpr_fpr_fpr

    inst_fmin_s_fpr_fpr_fpr ¶
    Source

    inst_fmin_s_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fmsub_d ¶
    Source

    inst_fmsub_d_fpr_fpr_fpr_fpr ¶
    Source

    inst_fmsub_d_fpr_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) -> Instruction {…}

    inst_fmsub_s ¶
    Source

    inst_fmsub_s_fpr_fpr_fpr_fpr ¶
    Source

    inst_fmsub_s_fpr_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) -> Instruction {…}

    inst_fmul_d ¶
    Source

    inst_fmul_d :: inst_fmul_d_fpr_fpr_fpr

    inst_fmul_d_fpr_fpr_fpr ¶
    Source

    inst_fmul_d_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fmul_s ¶
    Source

    inst_fmul_s :: inst_fmul_s_fpr_fpr_fpr

    inst_fmul_s_fpr_fpr_fpr ¶
    Source

    inst_fmul_s_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fmv_d_x ¶
    Source

    inst_fmv_d_x :: inst_fmv_d_x_fpr_gpr

    inst_fmv_d_x_fpr_gpr ¶
    Source

    inst_fmv_d_x_fpr_gpr :: proc "contextless" (rd: FPR, rs1: GPR) -> Instruction {…}

    inst_fmv_w_x ¶
    Source

    inst_fmv_w_x :: inst_fmv_w_x_fpr_gpr

    inst_fmv_w_x_fpr_gpr ¶
    Source

    inst_fmv_w_x_fpr_gpr :: proc "contextless" (rd: FPR, rs1: GPR) -> Instruction {…}

    inst_fmv_x_d ¶
    Source

    inst_fmv_x_d :: inst_fmv_x_d_gpr_fpr

    inst_fmv_x_d_gpr_fpr ¶
    Source

    inst_fmv_x_d_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fmv_x_w ¶
    Source

    inst_fmv_x_w :: inst_fmv_x_w_gpr_fpr

    inst_fmv_x_w_gpr_fpr ¶
    Source

    inst_fmv_x_w_gpr_fpr :: proc "contextless" (rd: GPR, rs1: FPR) -> Instruction {…}

    inst_fnmadd_d ¶
    Source

    inst_fnmadd_d_fpr_fpr_fpr_fpr ¶
    Source

    inst_fnmadd_d_fpr_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) -> Instruction {…}

    inst_fnmadd_s ¶
    Source

    inst_fnmadd_s_fpr_fpr_fpr_fpr ¶
    Source

    inst_fnmadd_s_fpr_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) -> Instruction {…}

    inst_fnmsub_d ¶
    Source

    inst_fnmsub_d_fpr_fpr_fpr_fpr ¶
    Source

    inst_fnmsub_d_fpr_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) -> Instruction {…}

    inst_fnmsub_s ¶
    Source

    inst_fnmsub_s_fpr_fpr_fpr_fpr ¶
    Source

    inst_fnmsub_s_fpr_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR, rs3: FPR) -> Instruction {…}

    inst_fsd ¶
    Source

    inst_fsd :: inst_fsd_fpr_mem

    inst_fsd_fpr_mem ¶
    Source

    inst_fsd_fpr_mem :: proc "contextless" (rd: FPR, mem: Memory) -> Instruction {…}

    inst_fsgnj_d ¶
    Source

    inst_fsgnj_d :: inst_fsgnj_d_fpr_fpr_fpr

    inst_fsgnj_d_fpr_fpr_fpr ¶
    Source

    inst_fsgnj_d_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fsgnj_s ¶
    Source

    inst_fsgnj_s :: inst_fsgnj_s_fpr_fpr_fpr

    inst_fsgnj_s_fpr_fpr_fpr ¶
    Source

    inst_fsgnj_s_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fsgnjn_d ¶
    Source

    inst_fsgnjn_d :: inst_fsgnjn_d_fpr_fpr_fpr

    inst_fsgnjn_d_fpr_fpr_fpr ¶
    Source

    inst_fsgnjn_d_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fsgnjn_s ¶
    Source

    inst_fsgnjn_s :: inst_fsgnjn_s_fpr_fpr_fpr

    inst_fsgnjn_s_fpr_fpr_fpr ¶
    Source

    inst_fsgnjn_s_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fsgnjx_d ¶
    Source

    inst_fsgnjx_d :: inst_fsgnjx_d_fpr_fpr_fpr

    inst_fsgnjx_d_fpr_fpr_fpr ¶
    Source

    inst_fsgnjx_d_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fsgnjx_s ¶
    Source

    inst_fsgnjx_s :: inst_fsgnjx_s_fpr_fpr_fpr

    inst_fsgnjx_s_fpr_fpr_fpr ¶
    Source

    inst_fsgnjx_s_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fsqrt_d ¶
    Source

    inst_fsqrt_d :: inst_fsqrt_d_fpr_fpr

    inst_fsqrt_d_fpr_fpr ¶
    Source

    inst_fsqrt_d_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR) -> Instruction {…}

    inst_fsqrt_s ¶
    Source

    inst_fsqrt_s :: inst_fsqrt_s_fpr_fpr

    inst_fsqrt_s_fpr_fpr ¶
    Source

    inst_fsqrt_s_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR) -> Instruction {…}

    inst_fsub_d ¶
    Source

    inst_fsub_d :: inst_fsub_d_fpr_fpr_fpr

    inst_fsub_d_fpr_fpr_fpr ¶
    Source

    inst_fsub_d_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fsub_s ¶
    Source

    inst_fsub_s :: inst_fsub_s_fpr_fpr_fpr

    inst_fsub_s_fpr_fpr_fpr ¶
    Source

    inst_fsub_s_fpr_fpr_fpr :: proc "contextless" (rd: FPR, rs1: FPR, rs2: FPR) -> Instruction {…}

    inst_fsw ¶
    Source

    inst_fsw :: inst_fsw_fpr_mem

    inst_fsw_fpr_mem ¶
    Source

    inst_fsw_fpr_mem :: proc "contextless" (rd: FPR, mem: Memory) -> Instruction {…}

    inst_jal ¶
    Source

    inst_jal :: inst_jal_gpr_label

    inst_jal_gpr_label ¶
    Source

    inst_jal_gpr_label :: proc "contextless" (rd: GPR, label: u32) -> Instruction {…}

    inst_jalr ¶
    Source

    inst_jalr_gpr_gpr_imm12 ¶
    Source

    inst_jalr_gpr_gpr_imm12 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_lb ¶
    Source

    inst_lb :: inst_lb_gpr_mem

    inst_lb_gpr_mem ¶
    Source

    inst_lb_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_lbu ¶
    Source

    inst_lbu :: inst_lbu_gpr_mem

    inst_lbu_gpr_mem ¶
    Source

    inst_lbu_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_ld ¶
    Source

    inst_ld :: inst_ld_gpr_mem

    inst_ld_gpr_mem ¶
    Source

    inst_ld_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_lh ¶
    Source

    inst_lh :: inst_lh_gpr_mem

    inst_lh_gpr_mem ¶
    Source

    inst_lh_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_lhu ¶
    Source

    inst_lhu :: inst_lhu_gpr_mem

    inst_lhu_gpr_mem ¶
    Source

    inst_lhu_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_load ¶
    Source

    inst_load :: proc "contextless" (m: Mnemonic, rd: Register, mm: Memory) -> Instruction {…}
     

    I-type load: rd, disp(base)

    inst_lr_d ¶
    Source

    inst_lr_d :: inst_lr_d_gpr_mem

    inst_lr_d_gpr_mem ¶
    Source

    inst_lr_d_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_lr_w ¶
    Source

    inst_lr_w :: inst_lr_w_gpr_mem

    inst_lr_w_gpr_mem ¶
    Source

    inst_lr_w_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_lui ¶
    Source

    inst_lui :: inst_lui_gpr_imm20

    inst_lui_gpr_imm20 ¶
    Source

    inst_lui_gpr_imm20 :: proc "contextless" (rd: GPR, imm: i64) -> Instruction {…}

    inst_lw ¶
    Source

    inst_lw :: inst_lw_gpr_mem

    inst_lw_gpr_mem ¶
    Source

    inst_lw_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_lwu ¶
    Source

    inst_lwu :: inst_lwu_gpr_mem

    inst_lwu_gpr_mem ¶
    Source

    inst_lwu_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_mul ¶
    Source

    inst_mul :: inst_mul_gpr_gpr_gpr

    inst_mul_gpr_gpr_gpr ¶
    Source

    inst_mul_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_mulh ¶
    Source

    inst_mulh :: inst_mulh_gpr_gpr_gpr

    inst_mulh_gpr_gpr_gpr ¶
    Source

    inst_mulh_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_mulhsu ¶
    Source

    inst_mulhsu :: inst_mulhsu_gpr_gpr_gpr

    inst_mulhsu_gpr_gpr_gpr ¶
    Source

    inst_mulhsu_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_mulhu ¶
    Source

    inst_mulhu :: inst_mulhu_gpr_gpr_gpr

    inst_mulhu_gpr_gpr_gpr ¶
    Source

    inst_mulhu_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_mulw ¶
    Source

    inst_mulw :: inst_mulw_gpr_gpr_gpr

    inst_mulw_gpr_gpr_gpr ¶
    Source

    inst_mulw_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_none ¶
    Source

    inst_none :: proc "contextless" (m: Mnemonic) -> Instruction {…}

    inst_or ¶
    Source

    inst_or :: inst_or_gpr_gpr_gpr

    inst_or_gpr_gpr_gpr ¶
    Source

    inst_or_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_ori ¶
    Source

    inst_ori_gpr_gpr_imm12 ¶
    Source

    inst_ori_gpr_gpr_imm12 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_r4 ¶
    Source

    inst_r4 :: proc "contextless" (m: Mnemonic, rd, rs1, rs2, rs3: Register) -> Instruction {…}
     

    FP R4-type: rd, rs1, rs2, rs3 (FMADD/FMSUB/FNMADD/FNMSUB)

    inst_r_r ¶
    Source

    inst_r_r :: proc "contextless" (m: Mnemonic, rd, rs1: Register) -> Instruction {…}
     

    FP R-type with 2 regs: rd, rs1 (FSQRT, FCVT, FMV, FCLASS, ...)

    inst_r_r_i ¶
    Source

    inst_r_r_i :: proc "contextless" (m: Mnemonic, rd, rs1: Register, imm: i64) -> Instruction {…}
     

    I-type (ALU): rd, rs1, imm12

    inst_r_r_r ¶
    Source

    inst_r_r_r :: proc "contextless" (m: Mnemonic, rd, rs1, rs2: Register) -> Instruction {…}
     

    R-type: rd, rs1, rs2

    inst_rem ¶
    Source

    inst_rem :: inst_rem_gpr_gpr_gpr

    inst_rem_gpr_gpr_gpr ¶
    Source

    inst_rem_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_remu ¶
    Source

    inst_remu :: inst_remu_gpr_gpr_gpr

    inst_remu_gpr_gpr_gpr ¶
    Source

    inst_remu_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_remuw ¶
    Source

    inst_remuw :: inst_remuw_gpr_gpr_gpr

    inst_remuw_gpr_gpr_gpr ¶
    Source

    inst_remuw_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_remw ¶
    Source

    inst_remw :: inst_remw_gpr_gpr_gpr

    inst_remw_gpr_gpr_gpr ¶
    Source

    inst_remw_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_sb ¶
    Source

    inst_sb :: inst_sb_gpr_mem

    inst_sb_gpr_mem ¶
    Source

    inst_sb_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_sc_d ¶
    Source

    inst_sc_d :: inst_sc_d_gpr_gpr_mem

    inst_sc_d_gpr_gpr_mem ¶
    Source

    inst_sc_d_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_sc_w ¶
    Source

    inst_sc_w :: inst_sc_w_gpr_gpr_mem

    inst_sc_w_gpr_gpr_mem ¶
    Source

    inst_sc_w_gpr_gpr_mem :: proc "contextless" (rd: GPR, rs1: GPR, mem: Memory) -> Instruction {…}

    inst_sd ¶
    Source

    inst_sd :: inst_sd_gpr_mem

    inst_sd_gpr_mem ¶
    Source

    inst_sd_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_sh ¶
    Source

    inst_sh :: inst_sh_gpr_mem

    inst_sh_gpr_mem ¶
    Source

    inst_sh_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_shift ¶
    Source

    inst_shift :: proc "contextless" (m: Mnemonic, rd, rs1: Register, shamt: u8) -> Instruction {…}
     

    I-type (shift): rd, rs1, shamt

    inst_size_from_bits ¶
    Source

    inst_size_from_bits :: proc "contextless" (bits: u32) -> u8 {…}
     

    inst_size_from_bits returns 2 for compressed (RVC) instructions, 4 for the standard 32-bit base ISA. RISC-V uses a length-encoding convention where the low 2 bits of the first halfword identify the instruction length: 11 = 32-bit (the standard base ISA), anything else = 16-bit (compressed).

    inst_sll ¶
    Source

    inst_sll :: inst_sll_gpr_gpr_gpr

    inst_sll_gpr_gpr_gpr ¶
    Source

    inst_sll_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_slli ¶
    Source

    inst_slli :: inst_slli_gpr_gpr_imm6

    inst_slli_gpr_gpr_imm6 ¶
    Source

    inst_slli_gpr_gpr_imm6 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_slliw ¶
    Source

    inst_slliw :: inst_slliw_gpr_gpr_imm5

    inst_slliw_gpr_gpr_imm5 ¶
    Source

    inst_slliw_gpr_gpr_imm5 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_sllw ¶
    Source

    inst_sllw :: inst_sllw_gpr_gpr_gpr

    inst_sllw_gpr_gpr_gpr ¶
    Source

    inst_sllw_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_slt ¶
    Source

    inst_slt :: inst_slt_gpr_gpr_gpr

    inst_slt_gpr_gpr_gpr ¶
    Source

    inst_slt_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_slti ¶
    Source

    inst_slti_gpr_gpr_imm12 ¶
    Source

    inst_slti_gpr_gpr_imm12 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_sltiu ¶
    Source

    inst_sltiu :: inst_sltiu_gpr_gpr_imm12

    inst_sltiu_gpr_gpr_imm12 ¶
    Source

    inst_sltiu_gpr_gpr_imm12 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_sltu ¶
    Source

    inst_sltu :: inst_sltu_gpr_gpr_gpr

    inst_sltu_gpr_gpr_gpr ¶
    Source

    inst_sltu_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_sra ¶
    Source

    inst_sra :: inst_sra_gpr_gpr_gpr

    inst_sra_gpr_gpr_gpr ¶
    Source

    inst_sra_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_srai ¶
    Source

    inst_srai :: inst_srai_gpr_gpr_imm6

    inst_srai_gpr_gpr_imm6 ¶
    Source

    inst_srai_gpr_gpr_imm6 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_sraiw ¶
    Source

    inst_sraiw :: inst_sraiw_gpr_gpr_imm5

    inst_sraiw_gpr_gpr_imm5 ¶
    Source

    inst_sraiw_gpr_gpr_imm5 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_sraw ¶
    Source

    inst_sraw :: inst_sraw_gpr_gpr_gpr

    inst_sraw_gpr_gpr_gpr ¶
    Source

    inst_sraw_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_srl ¶
    Source

    inst_srl :: inst_srl_gpr_gpr_gpr

    inst_srl_gpr_gpr_gpr ¶
    Source

    inst_srl_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_srli ¶
    Source

    inst_srli :: inst_srli_gpr_gpr_imm6

    inst_srli_gpr_gpr_imm6 ¶
    Source

    inst_srli_gpr_gpr_imm6 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_srliw ¶
    Source

    inst_srliw :: inst_srliw_gpr_gpr_imm5

    inst_srliw_gpr_gpr_imm5 ¶
    Source

    inst_srliw_gpr_gpr_imm5 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    inst_srlw ¶
    Source

    inst_srlw :: inst_srlw_gpr_gpr_gpr

    inst_srlw_gpr_gpr_gpr ¶
    Source

    inst_srlw_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_store ¶
    Source

    inst_store :: proc "contextless" (m: Mnemonic, rs2: Register, mm: Memory) -> Instruction {…}
     

    S-type store: rs2 (data), disp(base)

    inst_sub ¶
    Source

    inst_sub :: inst_sub_gpr_gpr_gpr

    inst_sub_gpr_gpr_gpr ¶
    Source

    inst_sub_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_subw ¶
    Source

    inst_subw :: inst_subw_gpr_gpr_gpr

    inst_subw_gpr_gpr_gpr ¶
    Source

    inst_subw_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_sw ¶
    Source

    inst_sw :: inst_sw_gpr_mem

    inst_sw_gpr_mem ¶
    Source

    inst_sw_gpr_mem :: proc "contextless" (rd: GPR, mem: Memory) -> Instruction {…}

    inst_u ¶
    Source

    inst_u :: proc "contextless" (m: Mnemonic, rd: Register, imm: i64) -> Instruction {…}
     

    U-type: rd, imm20

    inst_xor ¶
    Source

    inst_xor :: inst_xor_gpr_gpr_gpr

    inst_xor_gpr_gpr_gpr ¶
    Source

    inst_xor_gpr_gpr_gpr :: proc "contextless" (rd: GPR, rs1: GPR, rs2: GPR) -> Instruction {…}

    inst_xori ¶
    Source

    inst_xori_gpr_gpr_imm12 ¶
    Source

    inst_xori_gpr_gpr_imm12 :: proc "contextless" (rd: GPR, rs1: GPR, imm: i64) -> Instruction {…}

    mem ¶
    Source

    mem :: proc "contextless" (base: Register, disp: i32) -> Memory {…}

    mnemonic_to_string ¶
    Source

    mnemonic_to_string :: proc(m: Mnemonic, lowercase: bool = true, allocator := context.temp_allocator) -> string {…}

    op_fpr ¶
    Source

    op_fpr :: proc "contextless" (f: FPR) -> Operand {…}

    op_gpr ¶
    Source

    op_gpr :: proc "contextless" (g: GPR) -> Operand {…}
     

    Typed constructors

    op_imm ¶
    Source

    op_imm :: proc "contextless" (v: i64, size: u8) -> Operand {…}

    op_label ¶
    Source

    op_label :: proc "contextless" (label_id: u32, size: u8 = 2) -> Operand {…}

    op_mem ¶
    Source

    op_mem :: proc "contextless" (m: Memory) -> Operand {…}

    op_reg ¶
    Source

    op_reg :: proc "contextless" (r: Register) -> Operand {…}

    op_rel_offset ¶
    Source

    op_rel_offset :: proc "contextless" (off: i64) -> Operand {…}

    print ¶
    Source

    print :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    println ¶
    Source

    println :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    reg_class ¶
    Source

    reg_class :: proc "contextless" (r: Register) -> u16 {…}

    reg_hw ¶
    Source

    reg_hw :: proc "contextless" (r: Register) -> u8 {…}

    reg_is_fpr ¶
    Source

    reg_is_fpr :: proc "contextless" (r: Register) -> bool {…}

    reg_is_gpr ¶
    Source

    reg_is_gpr :: proc "contextless" (r: Register) -> bool {…}

    register_name ¶
    Source

    register_name :: proc(r: Register, lowercase: bool = true, allocator := context.temp_allocator) -> string {…}

    sbprint ¶
    Source

    sbprint :: proc(
	sb:           ^strings.Builder, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    sbprintln ¶
    Source

    sbprintln :: proc(
	sb:           ^strings.Builder, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    tprint ¶
    Source

    tprint :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

    tprintln ¶
    Source

    tprintln :: proc(
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) -> string {…}

    wprint ¶
    Source

    wprint :: proc(
	w:            io.Stream, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    wprintln ¶
    Source

    wprintln :: proc(
	w:            io.Stream, 
	instructions: []Instruction, 
	inst_info:    []Instruction_Info, 
	label_defs:   []rexcode_isa.Label_Definition, 
	tokens:       ^[dynamic]rexcode_isa.Token = nil, 
	options:      ^rexcode_isa.Print_Options = nil, 
	label_names:  ^map[u32]string = nil, 
) {…}

    Procedure Groups

    This section is empty.

    Source Files

    Generation Information

    Generated with odin version dev-2026-07 (vendor "odin") Windows_amd64 @ 2026-07-20 21:55:41.506051800 +0000 UTC